Abstract: A thin oxide region is introduced to a surface of a GaN layer prior to contact meal evaporation by carefully controlling the oxidation of the surface. This results in the normally present surface states to be smothered and thus a low band offset is observed in an ohmic contact comprising the contact metal and the GaN layer. The thickness of the oxide region preferably is about 8 .ANG. to 25 .ANG.. Other elements such as S, Se, Te, As, P and Hf can be used as an alternative to O. Devices using the thin region in the ohmic contact may include semiconductor laser devices, light emitting diodes, and III-V based transistors.

Abstract: Self stabilizing concentration profiles are achieved in solids. More particularly, semiconductor devices are made from n- or p-type mercury cadmium telluride (MCT) of the general formula Hg.sub.x Cd.sub.1-x Te where x=0.2 to 0.5 and n- or p-type zinc mercury telluride (ZMT) of the general formula Zn.sub.x Hg.sub.1-x Te where x=0.4 to 0.6. Silver, incorporated as a doping impurity or applied as an evaporated spot electromigrated within the MCT or ZMT to create one or more p-n junctions, usually under the influence of a pulsed positive bias. The resulting concentration profiles of silver and opposing internal electric fields of the p-n junctions achieve a balancing equilibrium that preserves and maintains the stability of the concentration profiles. For a specific telluride composition, Hg.sub.0.3 Cd.sub.0.7 Te, indium is the n-type dopant of choice.

Abstract: An ohmic electrode structure is produced by developing an In.sub.x Ga.sub.1-x As layer epitaxially on a compound semiconductor (n-Ga As), and providing a barrier layer composed of a tungsten nitride (high melting point metallic nitride) by sputtering. Then, electrode patterning is performed on the top of the tungsten nitride barrier layer by the photo-resist technique. After the process, unnecessary portion of the tungsten nitride barrier layer is removed by the reactive ion etching (RIE). On the top of this a Ti layer, a Pt layer and an Au layer are deposited in layers in that order by the lift-off technique to form a metal layer. Here, molybdenum nitride or titanium nitride may be used in place of tungsten nitride.

Abstract: By using fusion of a heat spreader layer, a large bandwidth, high power semiconductor laser can be fabricated. The use of multiple metals with low thermal resistance allows for higher power because heat flow is conducted away from the active region easily. The extraction of heat from the active region makes the resultant laser more stable with the capability for higher power outputs.

Abstract: By treating the silicon-oxide insulating layer of a semiconductor device with an aqueous metal-salt solution of a metal of an ion radius of less than 0.110 nm, for example, Sc, La or Zr, before a platinum electrode layer is provided on the insulating layer, the platinum layer shows excellent adhesive properties.

Abstract: A buried contact structure is provided for forming a contact between a source/drain region of a MOSFET and polysilicon conducting line. The polysilicon conducting line is formed on a field oxide region and extends onto the surface of the semiconductor substrate near the source/drain region. A polysilicon sidewall structure is formed in contact with the vertical edge of the polysilicon conducting line and the horizontal surface of the source/drain region to provide contact between the polysilicon conducting line and the source/drain region.

Abstract: An Au layer 3 and a Sn layer 5 are laminated on a barrier layer 8 which is formed on an optical circuit substrate 1. An Au layer 5 having a predetermined thickness is formed on the laminated layers as a top layer. A junction portion 2 is constituted of these layers. An electrode layer of an optical semiconductor element 9 is made to contact with the top Au layer 5 and the optical semiconductor element 9 is pressed to the optical circuit substrate 1. Then, by heating, the optical semiconductor element 9 is joined on the optical circuit substrate. A weight % of Au and Sn in the junction portion 2 of the optical circuit substrate 1 is about 80%:20% before the joining. The electrode layer is formed as a thin Au layer. The optical circuit substrate 1 is heated at a temperature of 280.degree. C. or more such that the Au layer and the Sn layer are melted and is cooled such that Au and Sn are solidified.

Abstract: The bipolar transistor includes an emitter layer at least a part of which is composed of AlGaAs, a collector layer at least a part of which is composed of GaAs, a base contact layer disposed in at least a part of an area between a base electrode and a base layer, and a base layer at least a part of which is composed of an InGaAs graded layer in which the concentration of In gradually increases from an emitter-base junction towards a base-collector junction.

Abstract: A p-type electrode structure having low resistance and a high yield light emitting element operable at low operating voltage is disclosed. On a substrate is formed an n-type clad layer, an active layer, a p-type semiconductor layer, a current structure layer, an n-type semiconductor layer and a metal layer. The energy level of a conduction band edge of the n-type semiconductor layer is deeper than that of a valence band edge of the p-type semiconductor layer, and the Fermi level of the metal layer is shallower than the energy level of a conduction band edge of the n-type semiconductor layer.

Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.

Abstract: An ohmic contact to a p-type zinc selenide (ZnSe) layer in a Group II-VI semiconductor device, includes a zinc mercury selenide (Zn.sub.x Hg.sub.1-x Se) layer on the zinc selenide layer, a mercury selenide (HgSe) layer on the zinc mercury selenide layer and a conductor (such as metal) layer on the mercury selenide layer. The zinc mercury selenide and mercury selenide layers between the p-type zinc selenide and the conductor layer provide an ohmic contact by eliminating the band offset between the wide bandgap zinc selenide and the conductor. Step graded, linear graded, and parabolic graded layers of zinc mercury selenide may be provided. A layer of mercury selenide without the mercury zinc selenide layer may also provide an ohmic contact. The ohmic contact of the present invention produces nearly ideal voltage-current relation, so that high efficiency Group II-VI optoelectronic devices may be obtained.

Abstract: A semiconductor structure (10) uses a clamp (16) disposed at an edge (27) of a dielectric structure (14) in a semiconductor device. The clamp substantially reduces the separation or peeling of the dielectric structure or layer away from the underlying semiconductor material (20,24). The clamp also provides the benefit of protecting the interface between the dielectric layer and the underlying semiconductor material from chemical or moisture attack, either during later processing or after final manufacture. Such chemical or moisture attack and internal film stress are factors leading to separation of the dielectric film from the underlying semiconductor material. The clamp is useful, for example, in preventing separation of silicon nitride or oxide passivation from gallium arsenide substrates in power rectifier diodes.

Abstract: A low temperature annealed Cu silicide or germanide layer on the surface of a single crystalline semiconductor substrate of Si or Ge is used in interconnection metallization for integrated circuits. The Cu silicide or germanide layer is preferably formed by heating Cu deposited on a Si or Ge substrate up to about 200.degree. C. for about 30 minutes. The layer demonstrates superior (near ideal) current/voltage characteristics and can be used as a high temperature (600-800.degree. C.) stable Ohmic/Schottky contact to Si or as a Cu diffusion barrier. Additional embodiments involve a Cu layer on a Ge layer on Si substrate, a Cu layer on a Si.sub.x Ge.sub.1-x layer on a substrate, and the use of an intermediate layer of a refractory metal such as W.

Abstract: A method for fabricating a semiconductor device includes: successively laminating a pair or more pairs of Ti and Al thin films on an n type GaAs substrate thereby to form Ti/Al laminated films; and performing thermal processing to the n type GaAs substrate and the Ti/Al laminated films at a temperature lower than the temperature at which Al of the Ti/Al laminated films and GaAs of the n type GaAs layer react with each other, to make the Ti/Al laminated films have ohmic junction with the n type GaAs layer thereby to form an ohmic electrode. Therefore, the Ti/Al laminated layer film comprising materials which are not likely to intrude into the n type GaAs layer is alloyed to Al.sub.3 Ti alloy by the annealing, and during the annealing, Ga atoms are out-migrated from the n type GaAs layer, and the Si atoms as dopants in the n type GaAs layer are present in the junction interface of the n type GaAs layer with the Ti/Al laminated layer film, thereby to form an ohmic contact.

Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.

Abstract: A II-VI semiconductor device includes a stack of semiconductor layers. An ohmic contact is provided that electrically couples to the stack. The ohmic contact has an oxidation rate when exposed to an oxidizing substance. A passivation capping layer overlies the ohmic contact and has an oxidation rate that is less than the oxidation rate of the ohmic contact.

Abstract: A II-VI group compound semiconductor device comprising a Zn.sub.X Mg.sub.1-X S.sub.Y Se.sub.1-Y (0.ltoreq.X.ltoreq.1, 0.ltoreq.Y.ltoreq.1) semiconductor layer, an intermediate layer comprising a compound of an element constituting the semiconductor layer and an additive element of Cd, Te or Hg formed on the semiconductor layer, and an electrode layer containing Ni, Pt or Pd formed on the intermediate layer.

Abstract: The invention provides an electrode material having the low contact resistance against a III-V group compound semiconductor, thereby realizing a light emitting device having a high luminance and driven at low voltages. The electrode material of the invention is applied to a III-V group compound semiconductor, which is expressed as a general formula of In.sub.x Ga.sub.y Al.sub.z N, where x+y+z=1, 0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, and 0.ltoreq.z.ltoreq.1, and doped with p-type impurities. The electrode material comprises an alloy of Au and at least one metal selected from the group consisting of Mg and Zn.

Abstract: The electrode structure of the invention includes a p-type Al.sub.x Ga.sub.y In.sub.1-x-y N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, x+y.ltoreq.1) semiconductor layer and an electrode layer formed on the semiconductor layer. In the electrode structure, the electrode layer contains a mixture of a metal nitride and a metal hydride.

Abstract: A periodic table group III-IV field-effect transistor device is described. The disclosed device uses a single metalization for ohmic and Schottky barrier contacts, permanent plural etch stop layers, employs a non-alloyed ohmic connection semiconductor layer and includes a permanent semiconductor material-comprised secondary mask element, a mask element which can be grown epitaxially during wafer fabrication to perform useful functions in both the device processing and device utilization environments. The device of the invention may be achieved with both an all optical lithographic process and a combined optical and electron beam lithographic process The disclosed device provides a field-effect transistor of reduced fabrication cost, increased dimensional accuracy and state of the art electrical performance.

Abstract: A periodic table group III-IV HEMT/PHEMT field-effect transistor device and its fabrication is described. The disclosed fabrication arrangement uses a single metallization for ohmic and Schottky barrier contacts, employs selective etching with a permanent etch stop layer, employs a non-alloyed ohmic contact semiconductor layer and includes a permanent non photoresponsive secondary mask element affording several practical advantages during fabrication and in the completed transistor. The invention includes provisions for both an all-optical lithographic fabrication process and a combined optical and electron beam lithographic process. These concepts are combined to provide a field-effect transistor device of reduced fabrication cost, increased dimensional accuracy and state of the art electrical performance.

Abstract: An electrode in contact with a n-type semiconductor for use in an electronic or optoelectronic device is disclosed. The electrode includes a non-conducting layer contacting the semiconductor; a conductive layer contacting the non-conducting layer, and the materials and the thickness of the non-conducting layer being selected so that the bilayer forms a low-resistance contact to the semiconductor, the bilayer providing stability against atmospheric corrosion.

Abstract: A structure and method for making HEMTs with a gate metal having a layer comprising titanium, a layer comprising vanadium over the layer comprising titanium, and a layer comprising gold over the layer comprising vanadium. Such HEMTs are insensitive to hydrogen.

Abstract: A p-type ohmic metal electrode for use with a group II-VI semiconductor device. The p-type ohmic metal electrode is made of a group II-IV p-type semiconductor layer having a group II element other than zinc dispersed in that layer disposed on the group II-IV semiconductor device, and a metal electrode layer disposed on the group II-IV semiconductor layer including the group II element other than zinc. Also disclosed is a group II-IV semiconductor device including a p-type group II-IV semiconductor containing zinc and selenium and the above ohmic metal electrode disposed on the group II-IV semiconductor device. Additionally, a group II-IV semiconductor device including a p-type group II-IV semiconductor containing zinc and selenium, a layer of a group II element other than zinc disposed on the group II-IV semiconductor device, and a metal electrode layer disposed on the layer of the group II element other than zinc is disclosed.

Abstract: A II-VI group compound semiconductor device having a p-type Zn.sub.x Mg.sub.1-x S.sub.y Se.sub.1-y (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1) semiconductor layer, on which an electrode layer is formed with at least metallic nitride layer lying between the semiconductor layer and the electrode layer.

Abstract: An ohmically conductive contact for a thin film p-type semiconductor compound formed of at least one of the metal elements of Class IIB of the Periodic Table of Elements and at least one of the non-metal elements of Class VIA of the Periodic Table of Elements and photovoltaic devices incorporating such contacts. An ohmic contact, according to the invention, includes a layer of conductive binder paste having mercury telluride and/or copper telluride dispersed therein. The invention also relates to a method of forming such ohmic contacts.

Abstract: A lower electrode, a first inorganic insulating film of SiN, and an organic insulating film of polyimide are formed on a GaAs substrate serving as an underlie, in this order. The organic insulating film is selectively etched to form a capacitor opening. A second norganic insulating film covering the surface of the organic insulating film and the bottom and side wall of the capacitor opening, and an upper electrode are formed. As the selective etching of the organic insulating film, wet etching may be used for simplifying manufacturing processes. Alternatively, dry etching may be used for improving etching accuracy. The organic insulating film 4 may be formed by a multi-layer film so that a circuit can be formed across multi-layers, improving the degree of integration.

Abstract: An ohmic contact to a III-V semiconductor material is fabricated. First, a III-V semiconductor material is provided. Source/drain regions are then formed in the III-V semiconductor material. On the III-V semiconductor material, a contact system is formed which is dry etchable using reactive ions such as chlorine or fluorine and substantially free of arsenic. Subsequently, a portion of the contact system is dry etched using reactive ions such as chlorine or fluorine to leave a portion of the contact system remaining on the source/drain regions. Then, the III-V semiconductor material and the contact system are annealed in an atmosphere substantially free of arsenic at a temperature at which at least a part of the contact system is alloyed with the source/drain regions to form an ohmic contact with the source/drain regions of the III-V semiconductor material.

Abstract: Self stabilizing concentration profiles are achieved in solids. More particularly, semiconductor devices are made from n- or p-type mercury cadmium telluride (MCT) of the general formula Hg.sub.x Cd.sub.1-x Te and especially using Hg.sub.0.3 Cd.sub.0.7 Te. Silver, incorporated as a doping impurity or applied as an evaporated spot electromigrates within the MCT to create one or more p-n junctions, usually under the influence of a pulsed positive bias. The resulting concentration profiles of silver and opposing internal electric fields of the p-n junctions achieve a balancing equilibrium that preserves and maintains the stability of the concentration profiles. For the specific telluride composition, indium is the n-type dopant of choice.

Abstract: A buried-ridge or buried-heterostructure II-VI laser diode. Polycrystalline II-VI semiconductor such as ZnS, ZnSSe, ZnSe or CdS deposited by vacuum evaporation buries the etched ridge.

Abstract: A II-VI laser diode including a substrate, a device layer of p-type II-VI semiconductor, an electrode and an ohmic contact layer between the electrode and device layer. The ohmic contact layer comprises a graded composition semiconductor compound including ZnTe. The relative amount of ZnTe in the semiconductor compound increases with increasing distance of the ohmic contact layer from the device layer. In a first embodiment the ohmic contact layer comprises a graded composition semiconductor alloy including the semiconductor compound of the device layer and ZnTe. The amount of ZnTe in the alloy increases with increasing distance of the ohmic contact layer from the device layer in the first embodiment. In a second embodiment the ohmic contact layer includes layers of ZnTe spaced between layers of the semiconductor compound of the device layer.

Abstract: Disclosed is a semiconductor device such as a light emitting diode, a MOS transistor, a Schottky diode, and CCD. The semiconductor device comprises a SiC layer of a first conductivity type and another SiC layer of a second conductivity type. At least one of the SiC layers of the first and second conductivity types is doped with at least one element selected from the group consisting of Cr, Mo and W.

Abstract: An ohmic electrode to p-type II-VI compound semiconductor and its fabricating method are disclosed. The ohmic electrode comprises: a layer made of Pd or an alloy containing Pd; and a metal layer provided thereon. The fabricating method of an ohmic electrode comprises the steps of: providing a layer made of Pd or an alloy containing Pd on a p-type II-VI compound semiconductor layer; and providing a metal layer on the layer made of Pd or an alloy containing Pd. Light emitting devices such as a semiconductor laser and a light emitting diode which use the ohmic electrode as the p-side electrode are also disclosed.

Abstract: An ohmic contact to a p-type zinc selenide (ZnSe) layer in a Group II-VI semiconductor device, includes a zinc telluride selenide (ZnTe.sub.x Se.sub.1-x) layer on the zinc selenide layer, a mercury selenide (HgSe) layer on the zinc telluride selenide layer and a conductor (such as metal) layer on the mercury selenide layer. The zinc telluride selenide and mercury selenide layers between the p-type zinc selenide and the conductor layer provide an ohmic contact by eliminating the band offset between the wide bandgap zinc selenide and the conductor. Step graded, linear graded, and parabolic graded layers of zinc telluride selenide may be provided. An integrated heterostructure is formed by epitaxially depositing the ohmic contact on the Group II-VI device. A removable overcoat layer may be formed on the Group II-VI device to allow room temperature atmospheric pressure transfer of the device from a zinc based deposition chamber to a mercury based deposition chamber, for deposition of the ohmic contact.

Abstract: A low resistance contact for p-type GaAs is provided by Pd/Zn/Pd/Au structure 1. The contact is suitable for device substrates having carrier concentrations in the range of about 10.sup.18 to about 10.sup.20 cm.sup.-3. The ohmic contact has a Pd layer of depth 3 nm to 15 nm, a Zn layer with a depth of between 5 nm and 40 nm, a second Pd layer with a depth greater than about 50 nm and an Au layer with a depth greater than about 300 nm. A preferred construction (1) is 5 nm/10 nm/100 nm/400 nm of Pd/Zn/Pd/Au. The ohmic contact deposition must be followed by annealing, with preferred annealing carried out at a temperature of about 200.degree. C. Annealing times are dependent upon annealing temperature, with a typical minimum annealing times of greater than 5 minutes at annealing temperatures of about 200.degree. C.

Abstract: A method and resulting ohmic contact structure between a high work function metal and a wide bandgap semiconductor for which the work function of the metal would ordinarily be insufficient to form an ohmic contact between the metal and the semiconductor. The structure can withstand annealing while retaining ohmic characteristics. The ohmic contact structure comprises a portion of single crystal wide bandgap semiconductor material; a contact formed of a high work function metal on the semiconductor portion; and a layer of doped p-type semiconductor material between the single crystal portion and the metal contact. The doped layer has a sufficient concentration of p-type dopant to provide ohmic behavior between the metal and the semiconductor material.

Abstract: A region of a second conductivity type is selectively formed in a portion of a semiconductive layer of a first conductivity type to form a pn junction area which serves as a photo-sensing region. A metal film is formed on a surface of the semiconductive layer of the first conductivity type to surround the photo-sensing region. When light to be directed to the photo-sensing region spreads outside the photo-sensing region, the light is reflected by the metal film provided on the surface of the semiconductive crystal layer around the photo-sensing region. Accordingly, the light does not reach the photo-sensing layer of the semiconductive crystal layer and the generation of undesired carriers is prevented.

Abstract: A semiconductor structure with a p-type ZnSe layer has an improved ohmic contact consisting of a layer of Hg.sub.x Zn.sub.1-x Te.sub.a Se.sub.b Sc where x=0-1 with x being 0 at the surface of the ZnSe layer and increasing thereafter, a, b and c each =0-1 and a+b+c=1.

Abstract: A ZnSe semiconductor device includes a ZnSe pn junction having p-type and n-type layers, and an ohmic contact to both layers. The ohmic contact to the p-type layer includes a p-type ZnSe crystalline semiconductor contact layer, and a conductive electrode layer characterized by a Fermi energy. The contact layer is doped with nitrogen shallow acceptors, characterized by a shallow acceptor energy, to a net acceptor concentration of at least 5.times.10.sup.17 cm.sup.-3. The contact layer also includes sufficient deep energy states between the shallow acceptor energy and the electrode layer Fermi energy to enable cascade tunneling by charge carriers.

Abstract: The semiconductor device somprises a silicon substrate, a boron-doped high resistant silicon carbide layer formed on said silicon substrate and a silicon carbide layer formed on said high resistant silicon carbide layer.

Abstract: On the surface of n-type layer of Ga.sub.1-x Al.sub.x As (0.ltoreq.x.ltoreq.1) having n-type layer, Au layer is formed as a first layer, and alloying treatment is performed after Ge layer, Ni layer and Au layer are sequentially formed. The first Au layer, the second Ge layer, the third Ni layer and the fourth Au layer have the following thickness:______________________________________ 1st layer Au 10-100 .ANG. 2nd layer Ge 50-200 .ANG. 3rd layer Ni 50-200 .ANG. 4th layer Au 200-1000 .ANG. ______________________________________Thus, it is possible to form an ohmic electrode, which has low contact resistance and does not develop ball-up phenomenon.

Abstract: An ohmic electrode for n-type cubic boron nitride made of two thin films; the first being at least one alloy material selected from the group consisting of Au-Si alloy, Au-Ge alloy and Au-Si-Ge alloy, and the second being at least one metallic material selected from the group consisting of Ni, Cr, Mo and Pt and process for the production thereof.