Abstract: Discussed are a lamp or a lamp device employing a semiconductor light-emitting element to have a high degree of luminance uniformity. A lamp includes a circuit board; a bus electrode formed along one direction on the circuit board; electrode lines on the circuit board to extend from the bus electrode; semiconductor light-emitting elements arranged in the direction in which the electrode lines are formed, and spaced a predetermined distance apart from a nearby electrode line; transparent electrodes for electrically connecting the semiconductor light-emitting elements to the electrode lines; a current input unit formed along the one direction in parallel to the bus electrode; and connecting electrodes arranged between the bus electrode and the current input unit along the one direction, to electrically connect the bus electrode to the current input unit, wherein a resistance value of certain of the connecting electrodes is different from a resistance value of the rest.

Abstract: A manufacturing method of a semiconductor apparatus includes preparing an intermediate member that includes a first member having a first substrate comprising a semiconductor element formed thereon, a second member having a second substrate, the second substrate including a part of a circuit electrically connected to the semiconductor element and having a linear expansion coefficient different from that of the first substrate, and a third member having a third substrate showing such a linear expansion coefficient that a difference between itself and the linear expansion coefficient of the first substrate is smaller than a difference between the linear expansion coefficients of the first substrate and the second substrate, and includes bonding the first member and the second member together. A first bonding electrode containing copper electrically connected to the semiconductor element and a second bonding electrode containing copper electrically connected to the circuit are bonded together.

Abstract: A radiation-emitting semiconductor chip may include a semiconductor body, a reflector, at least one cavity, and a seal. The semiconductor body may include an active region configured to generate electronic radiation. The reflector may be configured to reflect a portion of the electromagnetic radiation. The cavity may be filled with a material having a refractive index not exceeding 1.1. The seal may be impermeable to the material. The cavity may be arranged between the reflector and the semiconductor body, and the seal may cover the underside of the reflector.

Abstract: Optical components and associated methods of manufacturing are provided. An example optical component includes a body defined by an optical interposer substrate and a passivation layer applied to the optical interposer substrate. The optical interposer substrate defines a first surface of the body, and the passivation layer defines a second surface of the body opposite the first surface. The passivation layer includes a metallic shielding element configured to prevent interference between the first surface and the second surface. The optical component further includes an opening extending from the second surface to the optical interposer substrate, the opening defining an optical path through the passivation layer. The optical interposer substrate receives an optical signal from an optical transmitter supported by the second surface via the optical path.

Abstract: The present invention relates to a circuit protection device including: a device comprising a heating element configured to comprise a body and a pair of electrodes formed on the body, and a pair of lead wires connected, respectively, to the pair of electrodes; and a case having an independent accommodating space formed therein to accommodate at least the heating element, wherein the case includes at least one heat insulating layer disposed in the vicinity of the accommodating space.

Abstract: Methods of etching a metal layer and a metal-containing barrier layer to a predetermined depth are described. In some embodiments, the metal layer and metal-containing barrier layer are formed on a substrate with a first dielectric and a second dielectric thereon. The metal layer and the metal-containing barrier layer formed within a feature in the first dielectric and the second dielectric. In some embodiments, the metal layer and metal-containing barrier layer can be sequentially etched from a feature formed in a dielectric material. In some embodiments, the sidewalls of the feature formed in a dielectric material are passivated to change the adhesion properties of the dielectric material.

Abstract: Various strained channel transistors are disclosed herein. An exemplary semiconductor device includes a substrate and a fin structure disposed over the substrate. The fin structure includes a first epitaxial layer disposed on the substrate, a second epitaxial layer disposed on the first epitaxial layer, and a third epitaxial layer disposed on the second epitaxial layer. The second epitaxial layer includes a relaxed transversal stress component and a longitudinal compressive stress component, and the third epitaxial layer has uni-axial strain. A gate structure is disposed on a channel region of the fin structure, such that the gate structure interposes a source region and a drain region of the fin structure.

Abstract: The present disclosure provides an HBT that includes (i) a semiconductor support layer; at least four wall structures side-by-side on the support layer; (iii) a semiconductor collector-material ridge structure disposed on the support layer between two adjacent wall structures of the at least four wall structures; (iv) a semiconductor base-material layer, wherein a first part of the base-material layer is disposed on a first region of the ridge structure and a second part of the base-material layer is disposed across the wall structures, wherein the base-material layer is supported by the wall structures; (v) a semiconductor emitter-material layer disposed on the first part of the base-material layer; (vi) a base contact layer disposed on the second part of the base-material layer; an emitter contact layer disposed on the emitter-material layer; and (viii) a collector contact layer disposed on a second region of the ridge structure.

Abstract: A semiconductor structure includes a group IV substrate and a patterned group III-V device over the group IV substrate. Precursor stacks having at least one precursor metal are situated over at least one portion of the patterned group III-V device. A blanket dielectric layer is situated over the patterned group III-V device. Contact holes in the blanket dielectric layer are situated over each precursor stack. A filler metal is situated in each contact hole and over each precursor stack. The patterned group III-V device can be optically and/or electrically connected to group IV devices in the group IV substrate. Additional contact holes in the blanket dielectric layer can be situated over the group IV devices and filled with the filler metals.

Abstract: A power transistor includes multiple substantially parallel transistor fingers, where each finger includes a conductive source stripe and a conductive drain stripe. The power transistor also includes multiple substantially parallel conductive connection lines, where each conductive connection line connects at least one source stripe to a common source connection or at least one drain stripe to a common drain connection. The conductive connection lines are disposed substantially perpendicular to the transistor fingers. At least one of the source or drain stripes is segmented into multiple portions, where adjacent portions are separated by a cut location having a higher electrical resistance than remaining portions of the at least one segmented source or drain stripe.

Abstract: Circuit-Under-Pad (CUP) device topologies for high current lateral GaN power transistors comprise first and second levels of on-chip metallization M1 and M2; M1 defines source, drain and gate finger electrodes of a plurality of sections of a multi-section transistor and a gate bus; M2 defines an overlying contact structure comprising a drain pad and source pads extending over active regions of each section. The drain and source pads of M2 are interconnected by conductive micro-vias to respective underlying drain and source finger electrodes of M1. The pad structure and the micro-via interconnections are configured to reduce current density in self-supported widths of source and drain finger electrodes, i.e. to optimize a maximum current density for each section. For reduced gate loop inductance, part of each source pad is routed over the gate bus. Proposed CUP device structures provide for higher current carrying capability and reduced drain-source resistance.

Abstract: A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervene

Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 ?m-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by, for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

Abstract: A laser array including at least one line of lasers. The at least one line of lasers includes a first laser and a second laser which are adjacent to each other. A first laser beam emitted by the first laser and a second laser beam emitted by the second laser are both in a first color, and the first laser beam has a wavelength less than that of the second laser beam.

Abstract: A light emitting diode, the light emitting diode including: a first semiconductor layer, an active layer, a second semiconductor layer, wherein a surface of the second semiconductor layer defines a first area; a metallic plasma generating layer; a first electrode; a second electrode; wherein the metallic plasma generating layer includes a plurality of three-dimensional nanostructures, the three-dimensional nanostructure includes a first rectangular structure, a second rectangular structure, and a triangular prism structure, the first rectangular structure, the second rectangular structure, and the triangular prism structure are stacked, the width of the triangular prism structure is equal to the width of the second rectangular structure, and is greater than the width of the first rectangular structure, the first rectangular structure is a metal layer, and the triangular prism structure is a metal layer.

Abstract: The characteristics of a semiconductor device are enhanced. In a semiconductor device (MISFET) having a gate electrode GE formed on a nitride semiconductor layer CH via a gate insulating film GI, the gate insulating film GI is configured to have a first gate insulating film (oxide film of a first metal) GIa formed on the nitride semiconductor layer CH and a second gate insulating film (oxide film of a second metal) GIb. And, the second metal (e.g., Hf) has lower electronegativity than the first metal (e.g., Al). By thus making the electronegativity of the second metal lower than the electronegativity of the first metal, a threshold voltage (Vth) can be shifted in a positive direction. Moreover, the gate electrode GE is configured to have a first gate electrode (nitride film of a third metal) GEa formed on the second gate insulating film GIb and a second gate electrode (fourth metal) GEb.

Abstract: A method of producing a solid state battery includes pre-coating a solid electrolyte surface with a metal to form a sacrificial layer and contacting a metal alloy with the sacrificial layer such that the sacrificial layer and the metal alloy react to form a eutectic liquid metal interface layer, at room temperature and between the electrolyte and a lithium anode, configured to alloy with the liquid metal interface layer at operating potential.

Abstract: A device is specified, said device comprising a first component (1), a second component (2), and a connecting component (3) comprising at least a first region (31) and at least a second region (32). The composition of the first region (31) differs from the composition of the second region (32). The connecting component (3) is arranged between the first component (1) and the second component (2). The connecting component (3) comprises different kinds of metals, the first region (31) of the connecting component (3) comprises a first metal (41), and the concentration of the first metal (41) is greater in the first region (31) than the concentration of the first metal (41) in the second region (32).

Abstract: A semiconductor structure is provided that includes a silicon germanium alloy fin having a second germanium content located on a first portion of a substrate. The structure further includes a laterally graded silicon germanium alloy material portion located on a second portion of the substrate. The laterally graded silicon germanium alloy material portion is spaced apart from the silicon germanium alloy fin and has end portions having the second germanium content and a middle portion located between the end portions that has a first germanium content that is less than the second germanium content.

Abstract: In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time.

Abstract: A vertical III-nitride thin-film power diode can hold off high voltages (kV's) when operated under reverse bias. The III-nitride device layers can be grown on a wider bandgap template layer and growth substrate, which can be removed by laser lift-off of the epitaxial device layers grown thereon.

Abstract: A light emitting device according to the embodiment includes a support substrate; a first light emitting structure disposed on the support substrate and including a first conductive type first semiconductor layer, a first active layer, and a second conductive type second semiconductor layer; a first reflective electrode under the first light emitting structure; a first metal layer around the first reflective electrode; a second light emitting structure disposed on the support substrate and including a first conductive type third semiconductor layer, a second active layer, and a second conductive type fourth semiconductor layer; a second reflective electrode under the second light emitting structure; a second metal layer around the second reflective electrode; and a contact part making contact with an inner portion of the first conductive type first semiconductor layer of the first light emitting structure and electrically connected to the second reflective electrode.

Abstract: A circuit system includes: a first optoelectronic semiconductor component situated with an n-conductive surface facing an electrically conductive support surface and connected to the support surface in an electrically conductive manner; and a second optoelectronic semiconductor component situated with a p-conductive surface facing the support surface and connected to the support surface in an electrically conductive manner.

Abstract: The present invention relates to a UV photodetector having a high sensitivity and a low dark current. The object of the present invention is to specify a UV photodetector that has a high sensitivity and a low dark current. According to the invention, the fingers of the first electrode structure and the fingers of the second electrode structure have a cover layer made of a second semiconducting material, wherein the cover layer is arranged on the absorber layer and directly contacts the absorber layer in the region of the fingers, and the first semiconducting material and the second semiconducting material are designed in such a manner that a two-dimensional electron gas (2DEG) is formed at the boundary layer between the absorber layer and the cover layer in the region of the fingers.

Abstract: A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.

Abstract: A light-emitting diode (LED) lighting device includes a substrate, a first bottom electrode, a second bottom electrode, a first bottom transparent isolation layer, a second bottom transparent isolation layer, a first vertical LED, a second vertical LED, and a top transparent electrode. The substrate has a first recess and a second recess therein. The first bottom electrode and the second bottom electrode are respectively disposed in the first recess and the second recess and are reflective. The first vertical LED is disposed in the first recess and on the first bottom electrode. The second vertical LED is disposed in the second recess and on the second bottom electrode. The first bottom transparent isolation layer and the second bottom transparent isolation layer are respectively disposed in the first recess and the second recess. The top transparent electrode electrically connects the first vertical LED and the second bottom electrode.

Abstract: The present invention relates to a p-doped contact for use in a light-emitting diode for the ultraviolet spectral range, comprising a p-contact layer having a first surface for contacting a radiation zone and a second surface comprising, on the side facing away from the first surface: a) a coating, which directly contacts 5%-99.99% of the second surface of the p-contact layer and contains or consists of a material having a maximum reflectivity of at least 60% for light with a wavelength of 200 nm to 400 nm; b) a plurality of p-injectors, which are disposed directly on the second surface of the p-contact layer.

Abstract: A method for forming a metal electrode and a method for manufacturing semiconductor light emitting elements include providing a substrate having a semiconductor layer formed thereon; forming a bonding metal layer and a reflective metal layer on the semiconductor layer; and forming a metal electrode by layer inversion of the bonding metal layer and the reflective metal layer through a heat treatment process. An interface characteristic between a semiconductor layer and an electrode having a reflective metal layer is enhanced by a layer inversion phenomenon. High reflectivity can be obtained, because a reflection metal layer is uniformly distributed on a semiconductor layer. Further, out-diffusion of a reflective metal layer is prevented through layer inversion to enhance the thermal stability of an electrode. And the number of accepters for generating holes is increased through heat treatment under an oxygen atmosphere, so that contact resistance can be lowered.

Abstract: A method of manufacturing a device comprises depositing one or more metallization layers to a substrate, locally heating an area of the one or more metallization layers to obtain a substrate/metallization-layer compound or a metallization-layer compound, the compound comprising an etch-selectivity toward an etching medium which is different to that of the one or more metallization layers outside the area, and removing the one or more metallization layers in the area or outside the area, depending on the etching selectivity in the area or outside the area, by etching with the etching medium to form the device.

Abstract: A light-emitting element includes a semiconductor portion, an upper electrode and a lower electrode. The upper electrode includes a plurality of first external connectors, a plurality of second external connectors, a first inward elongated portion extending from each of the first external connectors, a second inward elongated portion extending from each of the second external connectors, a first outward elongated portion extending from each of the first external connectors toward a side opposite to a side where the second external connectors are disposed, and connecting two first external connectors next to each other, and a second outward elongated portion extending from each of the second external connectors toward a side opposite to a side where the first external connectors are disposed, and connecting two second external connectors next to each other.

Abstract: A semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer formed between the n-type semiconductor layer and the p-type semiconductor layer, and emitting light. The device further includes a p-electrode contacting to the p-type semiconductor layer, and including a first conductive oxide layer having an oxygen content lower than 40 atomic % and a second conductive oxide layer contacting to the first conductive oxide layer and having a higher oxygen content than the oxygen content of the first conductive oxide layer. The device also includes an n-electrode connecting electrically to the n-type semiconductor layer.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a first semiconductor region, a second semiconductor region, a first electrode, a first electrode and a conducting section. The substrate includes a conductive region and has a first surface. The first semiconductor region is provided on the first surface side of the substrate and includes AlXGa1-XN (0?X?1). The second semiconductor region is provided on a side opposite to the substrate of the first semiconductor region and includes AlYGa1-YN (0?Y?1, X?Y). The first electrode is provided on a side opposite to the first semiconductor region of the second semiconductor region and ohmically connects to the second semiconductor region. The conducting section electrically connects between the first electrode and the conductive region.

Abstract: A semiconductor device and a method of forming an airbridge extending from a conductive area of the semiconductor device are provided. The semiconductor device includes a device pattern formed on a semiconductor substrate, a seed layer formed on the device pattern, and an airbridge formed on the seed layer, where the airbridge includes a plated conductive material and defines an opening exposing a portion of the device pattern. The semiconductor device further includes an adhesion layer formed on the airbridge layer and extending over at least a portion of sidewalls of the opening defined by the airbridge, and an insulating layer formed on the adhesion layer, where the adhesion layer enhances adhesion of the insulating layer to the plated conductive material of the airbridge.

Abstract: Methods of modifying a patterned semiconductor substrate are presented including: providing a patterned semiconductor substrate surface including a dielectric region and a conductive region; and applying an amphiphilic surface modifier to the dielectric region to modify the dielectric region. In some embodiments, modifying the dielectric region includes modifying a wetting angle of the dielectric region. In some embodiments, modifying the wetting angle includes making a surface of the dielectric region hydrophilic. In some embodiments, methods further include applying an aqueous solution to the patterned semiconductor substrate surface. In some embodiments, the conductive region is selectively enhanced by the aqueous solution. In some embodiments, methods further include providing the dielectric region formed of a low-k dielectric material. In some embodiments, applying the amphiphilic surface modifier modifies an interaction of the low-k dielectric region with a subsequent process.

Abstract: According to one embodiment, a semiconductor light emitting device includes a stacked structural body, a first, a second and a third conductive layer. The stacked structural body includes first and second semiconductors and a light emitting layer provided therebetween. The second semiconductor layer is disposed between the first conductive layer and the light emitting layer. The first conductive layer is transparent. The first conductive layer has a first major surface on a side opposite to the second semiconductor layer. The second conductive layer is in contact with the first major surface. The third conductive layer is in contact with the first major surface and has a reflectance higher than a reflectance of the second conductive layer. The third conductive layer includes an extending part extending in parallel to the first major surface. At least a portion of the extending part is not covered by the second conductive layer.

Abstract: A method of at least partially releasing an epitaxial layer of a material from a substrate. The method comprises the steps of: forming a patterned sacrificial layer on the substrate such that the substrate is partially exposed and partially covered by the sacrificial layer; growing the epitaxial layer on the patterned sacrificial layer by nano-epitaxial lateral overgrowth such that the epitaxial layer is formed above an intermediate layer comprising the patterned sacrificial layer and said material; and selectively etching the patterned sacrificial layer such that the epitaxial layer is at least partially released from the substrate.

Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer.

Abstract: A flip-chip semiconductor based Light Emitting Device (LED) can include an n-type semiconductor substrate and an n-type GaN epi-layer on the substrate. A p-type GaN epi-layer can be on the n-type GaN epi-layer and a metal ohmic contact p-electrode can be on the p-type GaN epi-layer, where the metal ohmic contact p-electrode can have an average thickness less than about 25 ?. A reflector can be on the metal ohmic contact p-electrode and a metal stack can be on the reflector. An n-electrode can be on the substrate opposite the n-type GaN epi-layer and a bonding pad can be on the n-electrode.

Abstract: An electrical contact is formed on a III-V semiconductor comprising gallium. The contact is formed by depositing a first layer comprising In, Au, and a dopant on the surface of a III-V semiconductor and a second layer comprising a conductive oxide on the first layer. The deposited layers are annealed in an inert atmosphere. The annealing causes the formation of a Ga—Au compound at the interface between the III-V semiconductor and the first layer. At least a portion of the dopant migrates into the III-V semiconductor such that the dopant provides n-type or p-type conductivity to the III-V semiconductor. The specific contact resistivity between the III-V semiconductor and the second layer is less than about 10?5 ?cm2. The layers are further annealed in an oxidizing atmosphere such that the indium in the first layer is oxidized to form indium oxide.

Abstract: A nitride-based semiconductor light-emitting device 100 includes a GaN substrate 10, of which the principal surface is an m-plane 12, a semiconductor multilayer structure 20 that has been formed on the m-plane 12 of the GaN-based substrate 10, and an electrode 30 arranged on the semiconductor multilayer structure 20. The electrode 30 includes an Mg layer 32, which contacts with the surface of a p-type semiconductor region in the semiconductor multilayer structure 20.

Abstract: A flip-chip semiconductor based Light Emitting Device (LED) can include an n-type semiconductor substrate and an n-type GaN epi-layer on the substrate. A p-type GaN epi-layer can be on the n-type GaN epi-layer and a metal ohmic contact p-electrode can be on the p-type GaN epi-layer, where the metal ohmic contact p-electrode can have an average thickness less than about 25 ?. A reflector can be on the metal ohmic contact p-electrode and a metal stack can be on the reflector. An n-electrode can be on the substrate opposite the n-type GaN epi-layer and a bonding pad can be on the n-electrode.

Abstract: A method for manufacturing an optoelectronic apparatus includes attaching bottom surfaces of first and second packaged optoelectronic semiconductor devices (POSDs) to a carrier substrate (e.g., a tape) so that there is a space between the first and second POSDs. An opaque molding compound is molded around portions of the first and second POSDs attached to the carrier substrate, so that peripheral surfaces of the first POSD and the second POSD are surrounded by the opaque molding compound, the space between the first and second POSDs is filled with the opaque molding compound, and the first and second POSDs are attached to one another by the opaque molding compound. The carrier substrate is thereafter removed so that electrical contacts on the bottom surfaces of the first and second POSDs are exposed. A window for each of the POSDs is formed during the molding process or thereafter.

Abstract: The present disclosure provides methods for forming semiconductor devices with laser-etched vias and apparatus including the same. In one embodiment, a method of fabricating a semiconductor device includes providing a substrate having a frontside and a backside, and providing a layer above the frontside of the substrate, the layer having a different composition from the substrate. The method further includes controlling a laser power and a laser pulse number to laser etch an opening through the layer and at least a portion of the frontside of the substrate, filling the opening with a conductive material to form a via, removing a portion of the backside of the substrate to expose the via, and electrically coupling a first element to a second element with the via. A semiconductor device fabricated by such a method is also disclosed.

Abstract: In an n-type semiconductor layer that contains gallium (Ga), contact resistance is to be suppressed at a low level. An n-side electrode is provided on a surface of the n-type semiconductor layer containing Ga. The electrode includes a metal layer having a Ga content of equal to or more than 1 at % and equal to or less than 25 at %. The metal layer is disposed in contact with the n-type semiconductor layer.

Abstract: The present invention provides a copper interconnect for III-V compound semiconductor devices, which comprises a metal contact layer and a copper-containing metal layer, in which the metal contact layer is formed of a material selected from a group consisting of Ti/Pd/Cu, Ti/NiV/Cu, TiW/TiWN/TiW/Cu, TiW/TiWN/TiW/Au, TiW/Cu, and TiW/Au, and the copper-containing metal layer comprises a copper layer. The copper-containing metal layer further includes a metal protection layer covering on the copper layer to prevent the copper layer from oxidation. The metal protection layer is formed of Ni/Au, Ni/Pd/Au, NiV/Au, or solder.

Abstract: A semiconductor structure is provided having: a semiconductor; a gold-free electrically conductive structure in ohmic contact with the semiconductor; and a pair of electrically conductive layers separated by a layer of silicon. The structure includes: a refractory metal layer disposed in contact with the semiconductor; and wherein one of the pair of electrically conductive layers separated by the layer of silicon is the refractory metal layer. A second layer of silicon is disposed on a second one of the pair of pair of electrically conductive layers and including a third electrically conducive layer on the second layer of silicon. In one embodiment, the semiconductor includes a III-V material.

Abstract: According to one embodiment, a semiconductor light-emitting device using an ITON layer for a transparent conductor and realizing low drive voltage, high luminance efficiency, and uniformed light emission intensity distribution is provided. The semiconductor light-emitting device includes: a substrate; an n-type semiconductor layer formed on the substrate; an active layer formed on the n-type semiconductor layer; a p-type semiconductor layer formed on the active layer and whose uppermost part is a p-type GaN layer; an ITON (Indium Tin Oxynitride) layer formed on the p-type GaN layer; an ITO (Indium Tin Oxide) layer formed on the ITON layer; a first metal electrode formed on a part on the ITO layer; and a second metal electrode formed in contact with the n-type semiconductor layer.

Abstract: Disclosed herein is a nitride based semiconductor device. There is provided a nitride based semiconductor device including: a base substrate; an epitaxial growth layer disposed on the base substrate and generating 2-dimensional electron gas (2DEG) therein; and an electrode structure disposed on the epitaxial growth layer and having an extension extending into the epitaxial growth layer, wherein the epitaxial growth layer includes a depressing part depressed thereinto from the surface of the epitaxial growth layer, and the depressing part includes: a first area in which the extension is disposed; and a second area that is an area other than the first area.

Abstract: A low resistance electrode and a compound semiconductor light emitting device including the same are provided. The low resistance electrode deposited on a p-type semiconductor layer of a compound semiconductor light emitting device including an n-type semiconductor layer, an active layer, and the p-type semiconductor layer, including: a reflective electrode which is disposed on the p-type semiconductor layer and reflects light being emitted from the active layer; and an agglomeration preventing electrode which is disposed on the reflective electrode layer in order to prevent an agglomeration of the reflective electrode layer during an annealing process.

Abstract: A gallium nitride-based HEMT device, comprising a channel layer formed of an InGaN alloy. Such device may comprise an AlGaN/InGaN heterostructure, e.g., in a structure including a GaN layer, an InGaN layer over the GaN layer, and a (doped or undoped) AlGaN layer over the InGaN layer. Alternatively, the HEMT device of the invention may be fabricated as a device which does not comprise any aluminum-containing layer, e.g., a GaN/InGaN HEMT device or an InGaN/InGaN HEMT device.