Abstract: A component includes a carrier substrate having a coefficient of thermal expansion ?p and a chip mounted on the carrier substrate by a plurality of bumps. The chip has a first coefficient of thermal expansion ?1 in a first direction x1 and a first expansion difference, ??1 equal to the absolute value of ?p??1. The chip also has a second coefficient of thermal expansion ?2 in a second direction x2 and a second expansion difference ??2 is equal to the absolute value of ?p??2,. The bumps are arranged such that a first distance, ?x1, corresponding to a normal projection of a line between centers of terminally situated bumps in the first direction onto an axis running parallel to direction x1 is less than a second distance corresponding to a normal projection of a line between centers of terminally situated bumps in the second direction onto an axis parallel to direction x2.

Abstract: A system and method is disclosed for bonding a substrate to a semiconductor die that is prone to curling when subjected to an elevated temperature in a solder reflow oven, for example, thereby improving the electrical and mechanical bonding for large dies, wafers, chips, and photovoltaic cells. In one embodiment, the substrate is adapted to curl to the same degree as the die to form a uniform gap between the substrate and die across the boundary there between. In another embodiment, solder used to bond the die and substrate is applied such that the volume deposited varies based on the expected gap between the die and substrate when heated to the melting temperature of the solder.

Abstract: A Negative Thermal Expansion system (NTEs) device for TCE compensation or CTE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging. One aspect of the present invention provides a method for fabricating micromachine devices that have negative thermal expansion coefficients that can be made into a composite for manipulation of the TCE of the material. These devices and composites made with these devices are in the categories of materials called “smart materials” or “responsive materials.” Another aspect of the present invention provides microdevices comprised of dual opposed bilayers of material where the two bilayers are attached to one another at the peripheral edges only, and where the bilayers themselves are at a minimum stress conditions at a reference temperature defined by the temperature at which the bilayers are formed.

Abstract: An apparatus and system, as well as fabrication methods therefor, may include a substrate coupled to a first material and a second material. The first and second materials may comprise adjacent metals, and may have different coefficients of thermal expansion sufficient to reduce the amount of substrate warp that can occur due to heating and cooling.

Abstract: Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.

Abstract: The present invention provides a semiconductor apparatus having the improved thermal fatigue life against temperature change by lowering the maximum temperature on a jointing member existing between a semiconductor element and an electrode terminal and reducing the range of the temperature change.

Abstract: The invention relates to a trench filled with a thermally conducting material in a semiconductor substrate. In one embodiment, the semiconductor device has a trench defining a cell region, wherein a portion of the trench includes a thermally conducting material, and a contact to the thermally conducting material. The invention further relates to a semiconductor device and a method of forming a semiconductor device with an interlayer dielectric that is a thermally conducting material.

Abstract: An electronic assembly includes a first substrate and a second substrate. The first substrate includes a first surface having a first plurality of conductive traces formed on an electrically non-conductive layer. The second substrate includes a first surface having a second plurality of conductive traces formed thereon and a second surface having a third plurality of conductive traces formed thereon. A first electronic component is electrically coupled to one or more of the plurality of conductive traces on the first surface of the second substrate. At least one of a plurality of conductive interconnects is incorporated within each solder joint that electrically couples one or more of the conductive traces formed on the second surface of the second substrate to one or more of the conductive traces formed on the first substrate.

Abstract: A method is provided to enhance the connection reliability in three-dimensional mounting while considering the warping of packages. Opening diameters of the openings provided corresponding to protruding electrodes, respectively, are set so as to gradually decrease from the central portion toward the outer peripheral portion of a carrier substrate, and the opening diameters of openings provided corresponding to the protruding electrodes, respectively, are set so as to gradually decrease from the central portion toward the outer peripheral portion of another carrier substrate.

Abstract: A microelectromechanical device and a method for producing it having at least one layer on a substrate, in particular a thermoelectric layer on a substrate, the thermal expansion coefficient of the at least one layer and the thermal expansion coefficient of the substrate differing greatly. The at least one layer is coupled to at least one stress reduction means for the targeted reduction of lateral mechanical stresses present in the layer. This achieves a stress-free layer or enables stress-free growth.

Abstract: A method and structure for coupling a semiconductor substrate (e.g., a semiconductor chip) to an organic substrate (e.g., a chip carrier). The coupling interfaces a solder member (e.g., a solder ball) to both a conductive pad on the semiconductor substrate and a conductive pad on the organic substrate. Thermal strains on the solder member during thermal cycling may be reduced by having a surface area of the pad on the semiconductor substrate exceed a surface area of the pad on the organic substrate. Thermal strains on the solder member during thermal cycling may also be reduced by having a distance from a centerline of the solder member to a closest lateral edge of the semiconductor substrate exceed about 0.25 mm.

Abstract: A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The stress-relaxation layer of a first semiconductor chip is thicker than the stress-relaxation layer of a second semiconductor chip having a distance from a center thereof to an external terminal positioned at an outermost end portion thereof smaller than that of the first semiconductor chip.

Abstract: A method and apparatus for preventing thermo-mechanical damage to an electrostatic discharge (ESD) protection device is disclosed. The method and apparatus of the invention use materials with superior thermo-mechanical properties, in particular, the Coefficient of Thermal Expansion (CTE), melting temperature, tensile strength and fracture toughness. The thermo-mechanical energy absorber materials are incorporated in, or replace, components of the ESD device that are susceptible to thermo-mechanical stress and cracking due to localized heating and thermal expansion.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the aforementioned semiconductor device. The semiconductor device, in accordance with the principles of the present invention, may include a substrate, and a graded capping layer located over the substrate, wherein the graded capping layer includes at least two different layers, wherein first and second layers of the at least two different layers have different stress values.

Abstract: Tensile or compressive stress may be added in one or more selected locations to the biaxial residual stress existing in the channel of a semiconductor device, such as a MOSFET. The periphery of the active area containing the channel is modified by following layout procedures that result in forming outward protrusions of or inward depressions in the periphery of the active area and its surrounding shallow trench isolation during generally otherwise conventional fabrication of the device.

Abstract: An object of this invention is to provide an electrode for p-type SiC which can provide improved surface morphology and less thermal damage for a semiconductor crystal layer due to formation of an electrode. In this invention, a p-type electrode is manufactured to contain at least one selected from the group consisting of nickel (Ni), cobalt (Co), palladium (Pd) and platinum (Pt).

Abstract: A lid material (1) according to the present invention comprises: a base layer (2) composed of a low thermal expansion metal; an intermediate metal layer (3) provided on one surface of the base layer (2) and composed of a low proof stress metal having a proof stress of not greater than 110 N/mm2; and a brazing material layer (4) provided on the intermediate metal layer (3) and composed of a silver brazing alloy mainly comprising silver. The intermediate metal layer (3) and the brazing material layer (4) are press- and diffusion-bonded to each other, and the brazing material layer (4) has a blistered area ratio of not greater than 0.5% as observed on an outer surface of the brazing material layer. The low proof stress metal is preferably oxygen-free copper. A lid produced from the lid material (1) exhibits an excellent bonding property when the lid is brazed to a case mainly composed of a ceramic material for an electronic component package.

Abstract: A MEMS device such as a grating light valve™ light modulator is athermalized such that the force required to deflect the movable portion of the MEMS device remains constant over a range of temperatures. In MEMS embodiments directed to a grating light valve™ light modulator, a ribbon is suspended over a substrate, and the ribbon tension is kept constant over a temperature range by adjusting the aggregate thermal coefficient of expansion of the ribbon to match the aggregate thermal coefficient of expansion of the substrate. Various opposition materials have an opposite thermal coefficient of expansion as the aluminum layer of a grating light valve™ light modulator ribbon, using the thermal coefficient of expansion of the substrate as a zero coefficient reference.

Abstract: Electrically, thermally and mechanically enhanced ball grid array (BGA) packages are described. An IC die is mounted to a first surface of a first stiffener. A peripheral edge portion of a second surface of the first stiffener is attached to a first surface of a second stiffener to cover an opening through the second stiffener that is open at the first surface and a second surface of the second stiffener. The second surface of the second stiffener is attached to a first surface of a substantially planar substrate that has a plurality of contact pads on the first surface of the substrate. The plurality of contact pads are electrically connected through the substrate to a plurality of solder ball pads on a second surface of the substrate.

Abstract: An organic electro-luminescent display device and a method of fabricating the same are disclosed in the present invention. The organic electro-luminescent display device includes a plurality of pixels on a substrate, a thin film transistor coupled to each pixel, an organic electro-luminescent device coupled to the thin film transistor, a packaging layer on the organic electro-luminescent device, wherein the packaging layer comprises first and second inorganic layers having opposite stresses, and a first organic layer between the first and second inorganic layers.

Abstract: A composition including an amount of at least one vinyl terminated polymer; an amount of at least one cross-linker comprising a terminal Si—H unit; an amount of at least one thermally conductive first filler, and at least one thermally conductive second filler, wherein a melting point of the first filler is greater than the melting point of the second filler. An apparatus including a package configured to mate with a printed circuit board; a semiconductor device coupled to the package; a thermal element; and a curable thermal material disposed between the thermal element and the semiconductor device.

Abstract: A method and structure for reducing chip carrier flexing during thermal cycling. A semiconductor chip is coupled to a stiff chip carrier (i.e., a chip carrier having an elastic modulus of at least about 3×105 psi), and there is no stiffener ring on a periphery of the chip carrier. Without the stiffener ring, the chip carrier is able to undergo natural flexing (in contrast with constrained flexing) in response to a temperature change that induces thermal strains due to a mismatch in coefficient of thermal expansion between the chip and the chip carrier. If the temperature at the chip carrier changes from room temperature to a temperature of about −40° C., a maximum thermally induced displacement of a surface of the chip carrier is at least about 25% less if the stiffener ring is absent than if the stiffener ring is present.

Abstract: A semiconductor device able to maintain a bonding state between a bump and an electrode and having high reliability even under thermal stress, wherein a sealing resin is interposed to bond the electrodes and bumps between a wiring board formed with a plurality of electrodes and an IC chip formed with a plurality of bumps, the bumps being formed under the condition that the following formula is satisfied. 100<((&PHgr;A×F)/H)<125 where &PHgr;A represents the top diameter of a bump bonded with an electrode, H the height of a bump projecting from the IC chip and bonded with an electrode, and F the linear thermal expansion coefficient of the sealing resin.

Abstract: A semiconductor device for power control includes a substrate made of aluminum. Lands of copper are formed on the substrate. Semiconductor chips, such as FETs, are mounted on the lands. The semiconductor chips are joined with the lands only through solder layers. A synthetic resin, which includes epoxide, covers the lands, the solder layers and the semiconductor chips on the substrate. Preferably, a coefficient of expansion of the synthetic resin is generally less than a coefficient of expansion of the substrate or a coefficient of expansion of the lands. Each semiconductor chip defines at least two corners positioned generally opposite to each other. Each land defines at least two corners disposed in proximity to the corners of the semiconductor chip. The corners of the land generally confine the corners of the semiconductor chip therein.

Abstract: A composite lid for a semiconductor package, in which the lid includes at least two materials. The first material is disposed over and attached to the back surface of the die with a low-modulus thermal gel and the second material is disposed towards the perimeter of the lid. The second material has a modulus of elasticity greater than the modulus of elasticity of the first material, and preferably, at least twice that of the first material.

Abstract: A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The stress-relaxation layer of a first semiconductor chip is thicker than the stress-relaxation layer of a second semiconductor chip having a distance from a center thereof to an external terminal positioned at an outermost end portion thereof smaller than that of the first semiconductor chip.

Abstract: An electronic packaging structure and method of forming thereof wherein the structure is constituted of a modular arrangement which reduces stresses generated in a chip, underfill, and ball grid array connection with a flexible substrate in the form of an organic material, which stresses may result in potential delamination due to thermally-induced warpage between the components of the modular arrangement.

Abstract: A flip-chip package uses a substrate having bond pad spacing that matches terminal spacing on a chip at an elevated temperature that is an expected operating temperature of the chip. The elevated temperature can be the midpoint of the desired temperature cycle of the chip so that deformations of the electrical connections in one direction balance deformations in the opposite direction during temperature cycling. Matching spacing at an elevated temperature, even a temperature less than the bonding temperature, permits a better alignment at the bonding temperature for formation of stronger bonds.

Abstract: A semiconductor light receiving element having a light receiving layer (1) formed from a GaN group semiconductor, and an electrode (2) formed on one surface of the light receiving layer as a light receiving surface (1a) in such a way that the light (L) can enter the light receiving layer is provided. When the light receiving element is of a Schottky barrier type, the aforementioned electrode (2) contains at least a Schottky electrode, which is formed in such a way that, on the light receiving surface (1a), the total length of the boundary lines between areas covered with the Schottky electrode and exposed areas is longer than the length of the outer periphery of the light receiving surface (1a).

Abstract: An electronic device and method of making same wherein the device includes a substrate (e.g., a printed wiring board or semiconductor chip) having a circuit thereon, a first non-photosensitive layer (e.g., polyimide resin) positioned on the substrate and over the substrate's circuit, a second, photosensitive layer (e.g., epoxy resin) positioned on the first layer, and an electrically conductive layer positioned on the first, non-photosensitive layer and electrically coupled to the circuit through a hole in the first layer.

Abstract: Thermal cycling can lead to damaging stress at the upper surface of a semiconductor device chip (10) encapsulated in synthetic resin material (100), particularly in the case of power devices that include an IC. The invention provides a thick ductile layer pattern (50) of, for example, aluminium over most of the top surface of the insulating over-layer (40) of the chip (10). Electrically-isolated parts (50a, 50b, 50c, 50d etc.) of this ductile covering are individually connected to respective underlying conductive areas so as to reduce charging effects across the insulating over-layer (40). A sufficient spacing Z1 is present between these isolated parts (50a, 50b, 50c, 50d etc.) to avoid short circuits as a result of deformation by shearing and smearing during thermal cycling of the device.

Abstract: A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The stress-relaxation layer of a first semiconductor chip is thicker than the stress-relaxation layer of a second semiconductor chip having a distance from a center thereof to an external terminal positioned at an outermost end portion thereof smaller than that of the first semiconductor chip.

Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a conductive structure that couples a first substrate to a second substrate. The first substrate may include a chip or a module. The second substrate may include a chip carrier or a circuit card. Thus, the present invention encompasses such coupling as chip to chip carrier, chip to circuit card, and module to circuit card. The conductive structure includes a first conductive body and a second conductive body. The first conductive body is attached to the first substrate and the second conductive body is attached to the second substrate. The first conductive body may include a solder bump, while the second conductive body may include a eutectic alloy, such as a eutectic alloy lead and tin. Alternatively, the second conductive body may include a non-eutectic alloy whose melting point is below the melting point of the first conductive body.

Abstract: In order to realize a semiconductor device and a manufacturing method thereof which can keep with a high reliability an electric connection between each of bump pads formed on LSI chips and each of electrode pads formed on an interconnection substrate, within an guaranteed temperature range, a thermal expansion coefficient of an adhesive (3) is in the range of 20 to 60 ppm, and an elastic modulus of a build-up portion (6) is in the range of 5 to 10 GPa. Further, the build-up portion (6) is constituted by a multi-layer build-up substrate in which buid-up portion a peak value (a glass transition temperature) of a loss coefficient exists within a range of 100° C. to 250° C. and does not exist within a range of 0° C. to 100° C.

Abstract: A resistor layer (5) is formed on an isolation insulating film (4) selectively formed in a major surface (1S) of a semiconductor substrate (1). An interlayer insulation film (7) covering the resistor layer (5) has first and second plugs (9, 19) buried therein in the form of buried interconnections. The first and second plugs (9, 19) provide connection not only between an end portion of the resistor layer (5) and first and second interconnection layers (8, 18) but also between the end portion of the resistor layer (5) and the major surface (1S) of the semiconductor substrate (1).

Abstract: A flip chip ball grid array package includes a thin die having a die thickness reduced from a wafer thickness to reduce mismatch of a coefficient of thermal expansion between the thin die and a substrate; a plurality of thin film layers formed on the thin die wherein each of the plurality of thin film layers has a coefficient of thermal expansion that is greater than that of the thin die and is less than that of the substrate; and a plurality of wafer bumps formed on the thin die for making electrical contact between the thin die and the substrate.

Abstract: Novel interconnect structures possessing a relatively low internal stress and dielectric constant for use in semiconductor devices are provided herein. The novel interconnect structures comprise a first layer having a coefficient of thermal expansion greater than about 20 ppm and a first internal stress associated therewith, the first layer having a first set of metallic lines formed therein; a second layer having a coefficient of thermal expansion less than about 20 ppm and a second internal stress associated therewith, the second layer having a second set of metallic lines formed therein; and one or more stress adjustment cap layers formed between the first layer and the second layer, the cap layer(s) having a third internal stress to offset the first stress of the first layer and the second stress of the second layer and inducing a favorable relief of stress on the interconnect structure. Methods for making a semiconductor device having a substantially reduced internal stress are also provided.

Abstract: A method for cooling an MOVPE deposited, As-containing, P-type contact layer includes cooling the contact layer in an arsine environment to preserve the contact layer during the initial stages of the cooling process until a threshold temperature in the range of 560 to 580° C. is attained. During the cooling process, the arsine flow is reduced with respect to the arsine flow used during the MOVPE deposition. After the threshold temperature is attained, the arsine gas is withdrawn and the contact layer is cooled further. Because of the removal of the arsine gas at the threshold temperature, free carrier concentration within the contact layer is enhanced above the atomic concentration of the P-type dopant, and contact resistance is improved to a suitably low level. A semiconductor optoelectronic device is formed to include such a contact layer, the P-type dopant impurity present in an atomic concentration and the contact layer having a free carrier concentration being greater than the atomic concentration.

Abstract: A TRIAC which is one species of chip-type semiconductors includes an element body made of silicon, electrodes provided on one face of the element body, a molybdenum plate provided on one of the electrodes by an alloy plate made of aluminum and silicon, a molybdenum plate provided on the other face of the element body by a similar alloy plate, and nickel layers provided on connection faces of the molybdenum plates to outer electrode plates, so that the electrode and molybdenum plate are firmly connected without conventional high-temperature solder which includes a great amount of lead, and that the alloy plate never melt even when newly developed low-temperature institute is employed, and that the operation of the molybdenum plates is sufficiently realized.

Abstract: A semiconductor device able to maintain a bonding state between a bump and an electrode and having high reliability even under thermal stress, wherein a sealing resin is interposed to bond the electrodes and bumps between a wiring board formed with a plurality of electrodes and an IC chip formed with a plurality of bumps, the bumps being formed under the condition that the following formula is satisfied. 100<((&PHgr;A×F)/H)<125 where &PHgr;A represents the top diameter of a bump bonded with an electrode, H the height of a bump projecting from the IC chip and bonded with an electrode, and F the linear thermal expansion coefficient of the sealing resin.

Abstract: A chip structure comprises a wafer, an insulation layer, some conductive paste, a plurality of ball pads, a solder mask and a plurality of solder balls. The wafer has an active surface. The insulation layer is formed over the active surface of the wafer. The insulation layer has a plurality of open windows. The conductive paste fills the open windows. The ball pads are formed over the insulation layer in electrical connection with the conductive paste. The solder mask formed over the insulation layer. The solder mask exposes the ball pads. A solder ball is mounted to each ball pad.

Abstract: MEMS Device Having A Trilayered Beam And Related Methods. According to one embodiment, a movable, trilayered microcomponent suspended over a substrate is provided and includes a first electrically conductive layer patterned to define a movable electrode. The first metal layer is separated from the substrate by a gap. The microcomponent further includes a dielectric layer formed on the first metal layer and having an end fixed with respect to the substrate. Furthermore, the microcomponent includes a second electrically conductive layer formed on the dielectric layer and patterned to define an electrode interconnect for electrically communicating with the movable electrode.

Abstract: The present invention provides a package for a semiconductor chip that minimizes stresses and strains that arise from differential thermal expansion on chip-to-substrate or chip-to-card interconnections. A collar element of one or more elements is provided. Adhesive material connects the collar element to the electric device and to the substrate that supports it, forming a unitary electrical package.

Abstract: A wiring pattern formation method for forming a wiring pattern on a wafer by using a transcribing operation includes a transcribing step of thermally pressing and adhering a transcribing original substrate 19 that contains a metallic wiring layer 15 to be transcribed and has a linear expansion coefficient in which a dimensional error from a wafer 10 is within a predetermined range in a heated condition, on the wafer 10, and then adhering and transcribing the metallic wiring layer 15.

Abstract: A method for forming copper pad redistribution on a flip chip and structures formed by the method are disclosed. The method is compatible with a copper dual damascene process such that, after a substrate surface is planarized by chemical mechanical polishing, a single photomask can be used to pattern a plurality of redistribution pads, redistribution vias and redistribution lines. After the openings are filled with copper by an electroplating or an electroless plating technique, the top of the structure is again chemical mechanical polished to produce a planarized surface and resulting redistribution pads and redistribution lines. A sealing layer such as silicon nitride may be coated on the final structure as a moisture barrier.

Abstract: A rotating electrical machine control embodying a circuit including semiconductor devices mounted on a conductive pattern formed on a metal substrate without using heat sinks. Performance is improved as is durability by matching the linear expansion coefficient of the resin used to seal the semiconductor chips with that of the conductive pattern formed on the metal substrate.

Abstract: An apparatus and method for flexibly bonding an integrated circuit package to a printed circuit board are provided. The apparatus includes a semiconductor having first and second sides, where the first side defines an inner region and peripheral region. The inner region is surrounded by the peripheral region. An interposer having a substantially similar coefficient of thermal expansion to the semiconductor is included. A dielectric region surrounding the interposer is included. The dielectric region is configured to be partially elastic. A plurality of posts extends transversely through the dielectric region. The post have first and second ends where the first end is configured to be attached to the peripheral region of the semiconductor chip. The second ends of the posts are configured to be attached to an external assembly, wherein the posts are able to absorb stress due to a thermal expansion mismatch between the external assembly and the interposer.

Abstract: A wafer level semiconductor device including a wafer having a plurality of semiconductor elements formed on an upper surface thereof, a sealing resin including a first part for sealing the upper surface of the wafer and a second part for sealing a side surface of wafer, the second part having a lower edge surface flush with a lower surface of the wafer, and a film for covering the lower surface of wafer and the lower edge surface of the second part of the sealing resin and conducting the process using the wafer level semiconductor device in which the film is bonded. This structure prevents warping of the wafer level semiconductor device after the sealing resin is formed on the device and it is then taken out from the mold dies.

Abstract: A contact clip for the aluminum contact of a semiconductor device has a central nickel-iron body, preferably Nilo alloy 42, which is coated on top and bottom by a soft, but high conductivity metal such as gold, silver or copper. The nickel-iron body has a thickness of about 15 mils, and is about the thickness of the silicon die. The conductive layers have a thickness of about 5% to 20% of that of the nickel-iron core.

Abstract: An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate that has a first surface and a second surface is provided. The stiffener has a first surface and a second surface. The second stiffener surface is attached to the first substrate surface. An IC die has a first surface and a second surface. The first IC die surface is mounted to the first stiffener surface. A plurality of solder balls is attached to the second substrate surface. In one aspect, a heat spreader is mounted to the second IC die surface. In another aspect, the stiffener is coupled to ground to act as a ground plane. In another aspect, the substrate has a window opening that exposes a portion of the second stiffener surface. The exposed portion of the second stiffener surface is configured to be coupled to a printed circuit board (PCB). In another aspect, a metal ring is attached to the first stiffener surface.