Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication.

Abstract: A semiconductor device comprises a semiconductor substrate, a first insulation film formed on the semiconductor substrate, a metal film for forming a bonding pad on the first insulation film, and a second insulation film which is formed between the first insulation film and the bonding pad and which is stiffer than the first insulation film.

Abstract: A composite flip chip semiconductor device (10) permits burn-in testing and rework to be performed on the device while also enhancing electrical, thermal, and mechanical device performance. The device includes a semiconductor die (12) having a plurality of bonding pads (14). Also included in the composite device is an interposer (22) having a first surface with a plurality of traces (26). A plurality of vias (24) extend from the first surface of the interposer (22) to a second surface. The semiconductor die (12) is electrically coupled to the plurality of vias of the interposer which in turn is to be coupled to a substrate.

Abstract: A bonded structure is described consisting of a semiconductor wafer, preferably gallium arsenide, soldered to a substrate material. A method for forming the structure is also described. The structure provides mechanical support and thermal conductivity for the wafer, as well as a multitude of connections through the substrate material at predetermined locations on the wafer. The substrate material and the soldering process are selected to minimize the resulting stresses in the wafer. A pattern of pads consisting of a refractory metal covered by a solder material is formed on the substrate to maintain space for excess solder in order to avoid the shorting of the individual connections on the wafer, and to control the size and location of voids in the solder upon solidification.

Abstract: A multiple chip module (MCM) is fabricated by connecting a series of semiconductor chips, in a flip-chip orientation, to a multi-chip substrate with resilient connection pads. The substrate is formed from silicon by placing a layer of SiO2 on the surface. At the locations requiring a resilient connection pad, the SiO2 layer is pierced with a series of closely spaced holes. A cavity is etched out of the silicon below the closely spaced holes. The SiO2 layer is now suspended over the cavity and forms a flexible membrane. A post is formed on top of the flexible membrane. A conductor formed on the substrate has one end supported by the post. One end of the conductor is, therefor, supported by the post and flexible membrane so that a solder bump placed thereon may be used for a demountable connection to a contact pad on a flip-chip.