Abstract: A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby creating a double metal scheme wherein the strapping layer is a second metal layer overlying metal wordlines. In a method of a first embodiment the strapping material is electrically connected to the digit line through a planar landing pad overlying the conductive plug. An insulative material is sloped to the planar landing pad in order to provide a surface conducive to the formation of the strapping material.

Abstract: A liner material and method of use is disclosed. The method includes depositing a silicon layer into a deep void, such as a via or trench, and physical vapor depositing a cobalt seed layer onto the silicon. A supplemental cobalt layer is electroplated over the seed layer. The structure is then annealed, forming cobalt silicide (CoSix). The layer can be made very thin, facilitating further filling the via with highly conductive metals. Advantageously, the layer is devoid of oxygen and nitrogen, and thus allows low temperature metal reflows in filling the via. The liner material has particular utility in a variety of integrated circuit metallization processes, such as damascene and dual damascene processes.

Abstract: A conductive contact having an atomically flat interface. The contact includes, in order, a silicon substrate, a highly disordered silicide layer, and a titanium oxynitride layer. The silicide layer is formed of titanium, silicon, and one of the elements tungsten, tantalum, and molybdenum. The interface between the silicon substrate and the silicide layer is atomically flat. The flat interface prevents diffusion of conductive materials into the underlying silicon substrate. The contact is useful especially for very small devices and shallow junctions, such as are required for ULSI shallow junctions.

Abstract: A polysilicon film, a titanium silicide film and a titanium nitride film are formed in a storage node contact hole of a memory cell region, while a polysilicon film, a titanium silicide film and a titanium nitride film are formed in a bit line contact hole. In a peripheral circuit region, a peripheral circuit contact hole is formed in a silicon oxide film, and another peripheral circuit contact hole is formed in an interlayer insulation film and a silicon oxide film. Thus obtained are a semiconductor device reducing a leakage current, suppressing an electrical short and attaining a high-speed operation while readily forming each contact hole and a method of fabricating the same.

Abstract: This invention relates to a method for manufacturing a semiconductor device having polysilicon lines with micro-roughness on the surface. The micro-rough surface of the polysilicon lines help produce smaller grain size silicide film during the formation phase to reduce the sheet resistance. The micro-rough surface of the polysilicon lines also increases the effective surface area of the silicide contacting polysilicon lines thereby reduces the overall resistance of the final gate structure after metallization.

Abstract: A method of forming a transistor, the method comprises following steps: provides a substrate; covers part of the substrate by a doped amorphous silicon layer and covers part of the substrate by a first dielectric layer; forms a metal silicide layer on the doped amorphous silicon layer; removes the first dielectric layer to form a window; forms a second dielectric layer on both the metal silicide layer and the hole; and forms a conductor layer on the second dielectric layer. Significantly, during formation of the second dielectric layer, not only numerous dopants inside the doped amorphous silicon layer are driven into the substrate but also the doped amorphous silicon layer usually is re-crystallized to form an epi-like silicon layer.

Abstract: A polycide structure for use in an integrated circuit comprises a silicon layer; a barrier layer comprising ZSix where x is greater than two and Z is chosen from the group consisting of tungsten, tantalum and molybdenum; and a metal silicide layer, preferably cobalt silicide. The structure is particularly useful in applications requiring high temperature processing. The structure may be used as a gate stack, especially in memory applications such as DRAM. The structure provides thermal stability, thus avoiding agglomeration problems associated with high temperature processing combined with low resistivity.

Abstract: A capping layer for a semiconductor structure is described. The capping layer is deposited over a silicide-forming metal and has a composition such that nitrogen diffusion therefrom is insufficient to cause formation of an oxynitride from an oxide layer on the underlying silicon. The capping layer may be a metal layer from which no N diffusion occurs, or one or more layers including Ti and/or TiN arranged so that N atoms do not reach the oxide layer. A method is also described for forming the Ti and TiN layers. It is advantageous to deposit non-stoichiometric TiN deficient in N, by sputtering from a Ti target in a nitrogen flow insufficient to cause formation of a nitride on the target.

Abstract: A method is directed to form a semiconductor device with silicide formed by a metal layer associated with a deposited silicon layer by providing a substrate. A field oxide layer is formed on a substrate to define an active region. A gate structure is formed on the active region, where the gate structure has a gate oxide layer, a gate layer, and a cap layer on the gate layer. The field oxide layer has a height substantially equal to the cap layer. A spacer is formed on a sidewall of the gate structure. The cap layer is removed to expose the gate layer, whereby a trench is formed. A silicon layer is deposited over the substrate. A refractory metal layer is deposited on the silicon layer. A silicide layer is formed by performing a thermal process to trigger a reaction between the silicon layer and the metal layer. The silicide layer is polished by CMP process using the field oxide layer as a polishing stop.

Abstract: The present invention mainly provides a method to locally form metal silicide on an integral circuit and to avoid the phenomenon of leakage current which is caused by metal silicide formed between the memory cells on the same word line. The method of the present invention achieves the above objectives by principally using a design rule to adequately arrange elements within a proper distance. In an embodiment, in order to form metal silicide layers on an integral circuit and to avoid metal silicide formed between two neighboring memory cell on the same word line, a dielectric layer is first formed in the spaced region between the two neighboring memory cells to be used as a mask. Thus, in a following selective etching process, a part of the silicon substrate within the above spaced region can be protected and not exposed. Therefore, no metal silicide is formed in the spaced region, and the above objective is achieved.

Abstract: The present invention relates to a semiconductor structure including metal nitride and metal silicide, where a metal silicide layer is formed upon an active area that is part of a junction in order to facilitate further miniaturization that is demanded and dictated by the need for smaller devices. A single PECVD process makes three distinct depositions. First, a metal silicide forms by the reaction: MHal+Si+H2MSix+HHal, where M represents a metal and Hal represents a preferred halogen or the like. Second, a metal nitride forms upon areas not containing Si by the reaction: MHal+N2+H2MN+HHal. Third, a metal nitride forms upon areas of evolving metal silicide due to a diffusion barrier effect that makes formation of the metal silicide self limiting. Ultimately, a metal nitride layer will be uniformly disposed in a substantially uniform composition covering all underlying structures upon a semiconductor substrate.

Abstract: A first silicon oxide film is formed in such a manner as to cover source/drain regions of a transistor. A conductive pad is provided in the first silicon oxide film in such a manner that one end surface thereof is connected to each source/drain region and the other end surface thereof is exposed to the surface of the first silicon oxide film. A second silicon oxide film is formed on the first silicon oxide film and the pad. A conductive layer functioning as a plug is provided in the second silicon oxide film in such a manner that one end surface thereof is in contact with the pad and the other end surface thereof is connected to an interconnection layer. The surface of the first silicon oxide film is smoothly continuous to the other end surface of the pad at the same level. The conductive layer as the plug is formed in such a manner as to be smaller in size than the pad and to be in contact with the central portion of the pad.

Abstract: The present invention provides a semiconductor device having a metal suicide layer and a method for forming the metal silicide layer, the semiconductor device having a metal silicide-semiconductor contact structure, wherein the semiconductor device includes a substrate, an insulation layer with an opening, in which a metal silicide layer is formed using a native metal silicide with a first phase and a second phase, upon which a conductive layer is formed. The second phase has a first stoichiometrical composition ratio different from a second stoichiometrical composition ratio of the first phase. A reaction between the metal silicide layer of the first phase and the silicon results in the metal silicide layer of the second phase having high phase stability and low resistance.

Abstract: A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

Abstract: A triple-poly process forms a static random access memory (SRAM) which has a compact four-transistor SRAM cell layout. The cell layout divides structures among the three layers of polysilicon to reduce the area required for each cell. Additionally, a contact between a pull-up resistor formed in an upper polysilicon layer forms a “strapping” via which cross-couples a gate region and a drain region underlying the strapping via. Pull-up resistors extend across boundaries of cell areas to increase the length and resistance of the pull-up resistors.

Abstract: A method for making interlevel contacts having low contact resistance (Rc) between patterned polycide layers is described. The method and resulting contact structure consists of depositing and conductively doping a first polysilicon layer having a first tungsten silicide (WSi2) layer. The first polysilicon/silicide (first polycide) layer is patterned to form the first polycide inter connecting conducting layer. An insulating layer is deposited over the patterned first polycide layer and contact openings are anisotropically plasma etched in the insulating layer to the underlying polycide layer. The etching is continued to remove completely the first silicide layer in the contact openings, and to etch into the first polysilicon-layer. After a brief hydrofluoric (HF) etch, a second doped polysilicon layer is deposited and patterned to form a second conducting interconnecting level over the contact openings.

Abstract: An imaging device formed as a CMOS semiconductor integrated circuit includes a doped polysilicon contact line between the floating diffusion region and the gate of a source follower output transistor. The doped polysilicon contact line in the CMOS imager decreases leakage from the diffusion region into the substrate which may occur with other techniques for interconnecting the diffusion region with the source follower transistor gate. Additionally, the CMOS imager having a doped polysilicon contact between the floating diffusion region and the source follower transistor gate allows the source follower transistor to be placed closer to the floating diffusion region, thereby allowing a greater photo detection region in the same sized imager circuit.

Abstract: A semiconductor device includes a T-shaped gate on a gate insulation film, wherein the T-shaped gate includes a lower polycrystal layer containing Si and Ge and an upper polycrystal layer of polysilicon.

Abstract: A semiconductor device includes a barrier metal structure which are sandwiched between an electrode provided on a semiconductor chip and a bump. The barrier metal structure has a first through third conductive metal layers, where the third conductive metal layer as an uppermost layer thereof in contact with the bump covers the second conductive metal layer made of a material which is weak in resistance to diffusion and oxidation.

Abstract: A method of manufacturing a semiconductor device in which a cobalt silicide layer is formed on a semiconductor substrate. In the method, the semiconductor substrate is prepared, and cobalt is deposited on the semiconductor substrate by sputtering while heating the semiconductor substrate at a temperature approximately equal to 200 degrees Celsius. Thereafter, cobalt is deposited on the semiconductor substrate by sputtering while heating the semiconductor substrate at a temperature between 300 degrees Celsius and 400 degrees Celsius without exposing the semiconductor substrate to the atmosphere. Preferably, the semiconductor substrate is thereafter rapid thermal annealed at a temperature equal to or higher than 500 degrees Celsius in nitrogen atmosphere for a predetermined time. Further, at least a part of cobalt portion or cobalt oxide portion on the semiconductor substrate is removed by wet etching.

Abstract: A cell plate electrode is shared between storage capacitors of memory cells incorporated in a semiconductor dynamic random access memory device of the type having the storage capacitors over bit lines, and slits are formed in the cell plate electrode in such a manner that the boundaries between channel regions and gate oxide layers are horizontally spaced from the outer periphery of the cell plate electrode and the slits by distances equal to or less than a critical distance determined on the basis of a diffusion length of hydrogen in an inter-level insulating layer, thereby causing the hydrogen to surely reach the boundaries for reducing the density of surface state.

Abstract: A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second precursor with the seed layer by CVD. The titanium layer is used to form contacts to active areas of substrate and for the formation of interlevel vias.

Abstract: In the method for fabricating a metal wiring, an insulation film is formed on a semiconductor substrate. The insulation film has a contact hole exposing the semiconductor substrate. A Ti—Si film is formed over the silicon substrate, and a Ti—Si—N film is formed on the Ti—Si film. The contact hole is then filled by depositing copper on the Ti—Si—N film, and a silicon nitride film is formed over the silicon substrate.

Abstract: Disclosed is a novel contact structure comprising an underlying layer of titanium silicide, an intermediate layer of titanium boride, and an overlying layer of polysilicon. Also disclosed is a method for forming the contact structure which comprises depositing a titanium layer in the bottom of a contact opening having oxide insulation sidewalls, forming an overlying layer of polysilicon above the titanium layer, and annealing the two layers together. The resulting contact structure is formed with fewer steps than contact structures of the prior art and without the need for additional steps to achieve uniform sidewall coverage, due to high adhesion of the overlying layer of polysilicon with oxide insulation sidewalls of the contact opening. The contact structure has low contact resistance, and provides a suitable diffusion barrier due to a high melting point.

Abstract: Methods and apparatus for forming a conductor layer utilize an implanted matrix to form C54-titanium silicide. Word line stacks formed by the methods of the invention are used in sub-0.2 micron line width applications, interconnects, and silicided source/drain regions, among other applications, and have a lower resistivity and improved thermal stability.

Abstract: A silicide layer in direct contact with a gate electrode layer of a MOS transistor is formed only in a contact hole reaching the gate electrode layer, and is located only in the bottom portion of the contact hole. Thereby, increase in gate interconnection resistance is prevented, and thereby decrease in drive power of the transistor can be prevented.

Abstract: A first contact hole for a bit line is formed in an interlayer insulating film, and a polysilicon film is formed on the inner surface of the contact hole and on the interlayer insulating film. Subsequently, the polysilicon film is subjected to isotropic dry etching using a resist as a mask, and the interlayer insulating film is subjected to RIE etching, thereby forming a second contact hole in the interlayer insulating film in a peripheral circuit region. Then, a laminated film is formed on the inner surface of the second contact hole and on the polysilicon film, and the second contact hole is filled with a filling member. The laminated film and the polysilicon film are patterned, thereby forming a bit line in a memory cell region.

Abstract: To provide a conducting path between the metal_0 layer and a metal_1 interconnect layer, two layers with conducting plugs were necessary in the prior art. In the present invention, the conducting regions electrically coupling two regions of the integrated circuit are formed at the same time as the formation of the conducting plugs coupling selected portions of the integrated circuit with the metal_1 interconnect layer. The conducting regions, as with the conducting plugs, extend to surface of the insulating layer upon which the metal_1 interconnect paths are patterned. Using this technique, process steps required in the prior art can be eliminated. This process has the limitation that the metal_1 interconnect layer can not be formed over the conducting regions.

Abstract: A first contact hole for a bit line is formed in an interlayer insulating film, and a polysilicon film is formed on the inner surface of the contact hole and on the interlayer insulating film. Subsequently, the polysiliccon film is subjected to isotropic dry etching using a resist as a mask, and the interlayer insulating film is subjected to RIE etching, thereby forming a second contact hole in the interlayer insulating film in a peripheral circuit region. Then, a laminated film is formed on the inner surface of the second contact hole and on the polysilicon film, and the second contact hole is filled with a filling member. The laminated film and the polysilicon film are patterned, thereby forming a bit line in a memory cell region.

Abstract: A contact interface having a substantially annular silicide ring along sides of a depression formed in an active surface of the semiconductor substrate, wherein the depression is formed by an etching process to form a contact opening through a dielectric layer. The contact interface is formed by depositing a layer of conductive material, such as titanium, with a high bias power IMP deposition. The conductive material is turned to a silicide by an annealing process, thereby forming the contact interface.

Abstract: The present invention is directed to a method and apparatus for detecting edges through one or more opaque, planarized layers of material. Exemplary embodiments can take full advantage of decreased size geometries associated, such as 0.25 micron technologies, without suffering inaccuracies due to wafer misalignment during processing (e.g., during a photolithographic process). The invention is applicable to any process where an edge is to be detected through a planarized layer which is opaque to visible light. In an exemplary embodiment, an edge of an alignment mark can be detected using an energy source having a wavelength and angle of incidence specifically selected with respect to the optical characteristics and thickness of particular material layers being processed.

Abstract: In one aspect, the invention provides a method of forming an integrated circuitry memory device. In one preferred implementation, a conductive layer is formed over both memory array areas and peripheral circuitry areas. A refractory metal layer is formed over the conductive layer to provide conductive structure in both areas. According to a preferred aspect of this implementation, the conductive layer which is formed over the memory array provides an electrical contact for a capacitor container to be formed. According to another preferred aspect of this implementation, the conductive layer formed over the peripheral circuitry area constitutes a conductive line which includes at least some of the silicide. In another preferred implementation, the invention provides a method of forming a capacitor container over a substrate. According to a preferred aspect of this is implementation, a conductive layer is elevationally interposed between an upper insulating layer and a lower conductive layer over the substrate.

Abstract: Form a butted contact in an SRAM memory device by exposing a contact region on the surface of a doped semiconductor substrate and a conductor stack above a field oxide region on the surface of the substrate. Form an interpolysilicon silicon oxide dielectric layer over the device with an opening framing the contact region and the butt end of the conductor stack near the contact region. Form an undoped upper polysilicon layer on the surface of the SRAM device covering the dielectric layer, the contact region, and the butt end of the conductor stack and then patterned into interconnect and load resistance parts. Form a Vcc mask on the surface of the undoped upper polysilicon layer with a window framing the dielectric layer, the contact region, and the butt end of the conductor stack, leaving an exposed region of the undoped upper polysilicon layer.

Abstract: There is provided a semiconductor device comprising a Cu film provided above a main surface of a semiconductor substrate and used as a wiring, an intermediate layer formed at least on the Cu film, and an Al film formed on the intermediate layer and used as a pad, wherein the intermediate layer comprises a refractory metal nitride film and a refractory metal film formed on the refractory metal nitride film.

Abstract: Semiconductor device and method for manufacturing the same prevent the spread of a tungsten film out of an opening portion of a contact hole when the tungsten is grown in the contact hole and avoid inferior wiring shape and inter-wiring shirt-circuit. After a titanium/titanium nitride film is formed along an inner surface of the contact hole, a photo-resist film is applied. Then, the photo-resist film is etched away until a distance from an upper end of the contact hole to the surface of photo-resist film is not smaller than one-half of a width of the contact hole when the titanium/titanium nitride film is formed. After the titanium/titanium nitride film is etched by using the photo-resist as a mask, the photo-resist film is removed and a tungsten layer is selectively grown by using the titanium/titanium nitride film as a seed.

Abstract: Self-aligned contacts to the source and drain regions of a MOS device are formed by selectively removing portions of sidewall spacers from polysilicon source and drain electrodes. Metal silicide layers are then formed in contact with the exposed polysilicon portions and extending over and in contact with respective source and drain regions formed in a semiconductor substrate surface.

Abstract: In one embodiment a substrate 14 is patterned to have high and low conductive areas 110, 112, respectively. Metal lines 104, 108 in dielectric layer 16 pass transversely over the areas 110, 112. The areas 112 interrupt parasitic inductive current induced in the substrate 14.

Abstract: A method for fabricating contact holes in high density integrated circuits and the resulting structure are disclosed. It is shown that by judiciously integrating the process of forming shallow tapered holes with self-alignment techniques, self-aligned holes can be fabricated with reduced number of masking process steps. This is accomplished by first forming shallow tapered holes to a certain depth over certain regions in a substrate by means of isotropic etching and then extending them by anisotropic etching to full depth corresponding to the regions they are allowed to contact. The net result is a whole set of holes which are self-aligned and which are formed by means of a single photoresist mask.

Abstract: An HV transistor integrated in a semiconductor substrate with a first type of conductivity, comprising a gate region included between corresponding drain and source regions, and being of the type wherein at least said drain region is lightly doped with a second type of conductivity. The drain region comprises a contact region with the second type of conductivity but being more heavily doped, from which a contact pad extends.

Abstract: A semiconductor device having a metal interconnection includes an insulating film provided on a semiconductor substrate via a diffusion layer. An interlayer contact hole is formed in the insulating film. A metal silicide layer is provided at the bottom of the interlayer contact hole. A first conductive film comprises a single or a plurality of metal films provided on the insulating film and the interlayer contact hole. A second conductive film is provided in the interlayer contact hole. A third conductive film is provided on the first conductive film and the second conductive film. A fourth conductive film is provided on the third conductive film. This semiconductor device has improved durability with respect to electromigration or stress migration. Even when the interconnection has a multilevel structure, the contact resistance can be reduced by causing the interlayer contact hole portions to contact one another by the same kind of metal.

Abstract: A method for manufacturing a bit line is disclosed. Such a method includes: forming a layer-insulation layer on the surface of a semiconductor substrate; forming a contact hole on a predetermined region of the layer-insulation layer; forming a first conductive layer on the upper surface of the layer-insulation layer and inside the contact hole, the first conductive layer being made of a metal; forming a second conductive layer on the upper surface of the first conductive layer, the second conductive layer being made of a metal; and patterning the first and the second conductive layers together. The bit line made of a metal is manufactured to be integrated with a plug. The first conductive layer is formed by sputtering while the second conductive layer is formed by chemical vapor deposition, thereby shortening the process and improving the characteristics of the bit line.

Abstract: The present invention provides a structure for a semiconductor device, capable of eliminating the generation of defective products due to poor connection. In the present semiconductor device, an n-type high concentration diffusion layer 2 is selectively formed on the P-type silicon substrate 1, and on the diffusion layer 2, a silicon oxide film 3 is formed as a first interlayer insulating film 3. A silicon plug 4 is disposed on the n-type high concentration diffusion layer 2. On the top end surface of the polysilicon plug 4, a silicide pad 5 is formed in a self-aligning manner such that the width of the silicide pad 5 is larger than that of the polysilicon plug 4. A second interlayer insulating film is formed so as to cover the first interlayer insulating film 3 and the silicide pad 5, and a tungsten plug 7 is disposed on the silicide pad 5. On the second interlayer insulating film, wiring 8, made of an aluminum-copper alloy and connected to the tungsten plug, is formed.

Abstract: A semiconductor device includes a polysilicon film formed directly or indirectly on a semiconductor substrate, and a refractory metal silicide film formed on the polysilicon film. The refractory metal silicide film comprises grains of refractory metal silicide. At least a portion of the grains has a maximum grain diameter equal to or larger than at least one of a film thickness of the refractory metal silicide film and a film width of the refractory metal silicide film.

Abstract: A dual damascene process and structure for fabricating semiconductor devices are disclosed. In one embodiment of the invention, a protection layer is deposited on top of a metal layer to protect the metal layer during subsequent etching of an oxide layer to form the via and damascene trench. Because the selectivity between the oxide layer and the protection layer is high, the number and complexity of processing steps are thereby reduced. Other embodiments of the present invention use a metal sealant layer and/or anti-reflective coating in conjunction with the protection layer in a dual-damascene process.

Abstract: Methods and apparatus for forming a conductor layer utilize an implanted matrix to form C54-titanium silicide. Word line stacks formed by the methods of the invention are used in sub-0.25 micron line width applications, interconnects, and silicided source/drain regions, among other applications, and have a lower resistivity and improved thermal stability.

Abstract: A packaging and interconnection for connecting a contact structure to an outer peripheral component with a short signal pass length to achieve a high frequency operation.

Abstract: Interlevel contacts in semiconductor integrated circuits are fabricated by formation of a contact opening through an insulating layer. A layer of refractory metal, or refractory metal alloy, is deposited over the surface of the integrated circuit chip. An aluminum layer is then deposited at a significantly elevated temperature, so that an aluminum/refractory metal alloy is formed at the interface between the aluminum layer and the refractory metal layer. Formation of such an alloy causes an expansion of the metal within the contact opening, thereby filling the contact opening and providing a smooth upper contour to the deposited aluminum layer.

Abstract: An integrated circuit having at least one electrical interconnect for connecting at least two components and a process for forming the same are disclosed. The integrated circuit comprises: a substrate, a plurality of adjacent conductive strips, a layer of dielectric material, and a conductive material. The substrate has a surface and the plurality of adjacent conductive strips is disposed on the substrate surface with each adjacent conductive strip having a length. The layer of dielectric material is deposited over the substrate surface and over and around the plurality of adjacent conductive strips to form at least two opposing, contoured, merging dielectric surfaces, each of which overhangs the substrate surface located between at least two of the plurality of adjacent conductive strips. The at least two opposing, contoured, merging dielectric surfaces define at least one elongated passageway which has at least one opening and is substantially encased therein and which extends along the length.

Abstract: The MOS transistor has field plates and a subarea of the gate formed from the same polysilicon layer. A gate oxide lying underneath them is produced at the beginning of the fabrication process and it therefore exhibits particularly high quality. The polysilicon in the active area is raised to the same level as the adjoining field oxide areas, resulting in a planar topology.

Abstract: A semiconductor device adopting an interlayer contact structure between upper and lower conductive layers and a method of manufacturing the semiconductor device adopting the structure are provided. The lower conductive layer includes a first conductive layer and a first silicide layer stacked together. The upper conductive layer includes a second conductive layer doped with impurities and a second silicide layer stacked together. In the interlayer contact structure, the first and second conductive layers are in direct contact with each other. This decreases the contact resistance between the two conductive layers and improves the electrical properties of the device.