At Least One Layer Of Molybdenum, Titanium, Or Tungsten Patents (Class 257/763)
  • Patent number: 10367089
    Abstract: According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: July 30, 2019
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Stephen Daley Arthur, Joseph Darryl Michael, Tammy Lynn Johnson, David Alan Lilienfeld, Kevin Sean Matocha, Jody Alan Fronheiser, William Gregg Hawkins
  • Patent number: 10354871
    Abstract: A method for sputtering an aluminum layer on a surface of a semiconductor device is presented. The method includes three sputtering steps for depositing the aluminum layer, where each sputtering step includes at least one sputtering parameter that is different from a corresponding sputtering parameter of another sputtering step. The surface of the semiconductor device includes a dielectric layer having a plurality of openings formed through the dielectric layer.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: July 16, 2019
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Stacey Joy Kennerly, Victor Torres, David Lilienfeld, Robert Dwayne Gossman, Gregory Keith Dudoff
  • Patent number: 10297562
    Abstract: Provided is a semiconductor device that is resistant to the corrosion of titanium nitride forming an anti-reflection film. The semiconductor device includes: a wiring layer which includes a wiring film made of aluminum or an aluminum alloy and formed on a substrate and a titanium nitride film formed on the wiring film; a protection layer which covers a top surface and a side surface of the wiring layer; and a pad portion which penetrates the protection layer and the titanium nitride film, and which exposes the wiring film, the protection layer including a first silicon nitride film, an oxide film, and a second silicon nitride film which are layered in the stated order from the side of the wiring layer.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: May 21, 2019
    Assignee: ABLIC INC.
    Inventors: Kaku Igarashi, Shinjiro Kato, Hisashi Hasegawa, Masaru Akino, Yukihiro Imura
  • Patent number: 10227696
    Abstract: A method includes heating, using a heat source, a reactor vessel including a substrate in a radially central core region of the reactor vessel and introducing, using at least one reactor inlet in an outer wall of the reactor vessel, a precursor gas to the reactor vessel. The at least one reactor inlet is configured to swirling flow of the precursor gas around the radially central core region of the reactor vessel. The material deposits on the substrate from the precursor gas. The method includes removing, using at least one reactor outlet, an exhaust gas from the reactor vessel.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: March 12, 2019
    Assignees: Rolls-Royce Corporation, Rolls-Royce High Temperature Composites, Inc.
    Inventors: Chong M. Cha, David Liliedahl, Richard Kidd, Ross Galligher, Nicholas Doan
  • Patent number: 10217664
    Abstract: A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches. The depositing and the reflowing steps are repeated until the trenches are aggregately filled with the reflow material. The reflow material is planarized to form conductive structures in the trenches.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Su Chen Fan, Huai Huang, Koichi Motoyama, Wei Wang, Chih-Chao Yang
  • Patent number: 10186592
    Abstract: An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: January 22, 2019
    Assignee: Acorn Technologies, Inc.
    Inventors: Daniel E. Grupp, Daniel J. Connelly
  • Patent number: 10163758
    Abstract: Present disclosure provides a semiconductor structure, including a semiconductor substrate having an active side, an interconnect layer over the active side of the semiconductor substrate, and a through substrate via (TSV) extending from the semiconductor substrate to the first metal layer. The interconnect layer includes a first metal layer closest to the active side of the semiconductor substrate, a thickness of the first metal layer is lower than 1 micrometer, and a dimension of a continuous metal feature of the first metal layer is less than 2 micrometer from a top view perspective. The continuous metal feature is cut off by a first dielectric feature. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Ching-Chun Wang, Kuan-Chieh Huang, Hsing-Chih Lin, Yi-Shin Chu
  • Patent number: 10128188
    Abstract: A low resistance middle-of-line interconnect structure is formed without liner layers. A contact metal layer is deposited on source/drain regions of field-effect transistors and directly on the surfaces of trenches within a dielectric layer using plasma enhancement. Contact metal fill is subsequently provided by thermal chemical vapor deposition. The use of low-resistivity metal contact materials such as ruthenium is facilitated by the process. The process further facilitates the formation of metal silicide regions on the source/drain regions.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: November 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
  • Patent number: 10109610
    Abstract: A wire bond system. Implementations may include: a bond wire including copper (Cu), a bond pad including aluminum (Al) and a sacrificial anode electrically coupled with the bond pad, where the sacrificial anode includes one or more elements having a standard electrode potential below a standard electrode potential of Al.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: October 23, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Wentao Qin, Gordon M. Grivna, Harold Anderson, Thomas Anderson, George Chang
  • Patent number: 10056536
    Abstract: Provided is a thermoelectric conversion material including a plurality of kinds of phases including a first phase and a second phase which have elemental compositions different from each other. The first phase and the second phase have a skutterudite structure.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: August 21, 2018
    Assignee: FURUKAWA CO., LTD.
    Inventors: Ge Nie, Atsuro Sumiyoshi, Taketoshi Tomida, Takahiro Ochi, Shogo Suzuki, Masaaki Kikuchi, Junqing Guo
  • Patent number: 10008450
    Abstract: An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: June 26, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey A. West, Kezhakkedath R. Udayakumar, Eric H. Warninghoff, Alan G. Merriam, Rick A. Faust
  • Patent number: 9991202
    Abstract: A method of forming a semiconductor structure includes forming a first insulating layer containing a first metal layer embedded therein and on a surface of a semiconductor substrate. The method further includes forming an inter-layer dielectric (ILD) layer on the first insulating layer, and forming at least one via trench structure including a first metallization trench and a via in the ILD layer. In addition, the method also includes depositing a metal material to form a first metallization layer in the first metallization trench, a via contact in the via, and a second metal layer on top of at least a portion of the first metal layer in the opening of the first insulating layer. The first metal layer and the second metal layer constitute a multilayer metal contact located in the opening of the first insulating layer.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: June 5, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jim S. Liang, Justin C. Long, Atsushi Ogino
  • Patent number: 9978700
    Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first insulating layer is formed over a first surface of the encapsulant and an active surface of the semiconductor die. A second insulating layer is formed over a second surface of the encapsulant opposite the first surface. A conductive layer is formed over the first insulating layer. The conductive layer includes a line-pitch or line-spacing of less than 5 ?m. The active surface of the semiconductor die is recessed within the encapsulant. A third insulating layer is formed over the semiconductor die including a surface of the third insulating layer coplanar with a surface of the encapsulant. The second insulating layer is formed prior to forming the conductive layer. A trench is formed in the first insulating layer. The conductive layer is formed within the trench.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: May 22, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Yaojian Lin
  • Patent number: 9960135
    Abstract: A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads includes a metal bond pad area. A cobalt including connection layer is deposited directly on the metal bond pad area. The cobalt including connection layer is patterned to provide a cobalt bond pad surface for the plurality of bond pads, and a solder material is formed on the cobalt bond pad surface.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: May 1, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Helmut Rinck, Gernot Bauer, Robert Zrile, Kai-Alexander Schachtschneider, Michael Otte, Harald Wiesner
  • Patent number: 9956396
    Abstract: A thin film for a lead for brain applications includes at least one section comprising a high conductive metal and a low conductive metal, whereby the low conductive metal is a biocompatible metal and has a lower electrical conductivity than the high conductive metal and whereby the high conductive metal is at least partially encapsulated by the low conductive metal. Furthermore, the present invention relates to a method of manufacturing a thin film for a lead for brain applications and a deep brain stimulation system.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: May 1, 2018
    Assignee: Medtronic Bakken Research Center B.V.
    Inventors: Edward Willem Albert Young, Hoa Thi Mai Pham, Martinus Lambertus Wilhelmus Vorstenbosch, Ke Wang
  • Patent number: 9955590
    Abstract: The present disclosure relates to redistribution layer structures useful in semiconductor substrate packages, semiconductor package structures, and chip structures. In an embodiment, a redistribution layer structure includes a dielectric layer, an anti-plating layer, and a conductive material. The dielectric layer defines one or more trenches. The conductive material is disposed in the trench(es), and the anti-plating layer is disposed on a surface of the dielectric layer.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: April 24, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chao-Fu Weng
  • Patent number: 9922876
    Abstract: An interconnect structure including a substrate, a dielectric layer, a first conductive pattern, and a second conductive pattern is provided. The dielectric layer is disposed on the substrate and has an opening. The first conductive pattern is disposed in the opening. The second conductive pattern is disposed on the first conductive pattern and exposes an exposed portion of the first conductive pattern. The exposed portion of the first conductive pattern has a notch.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: March 20, 2018
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Hong-Ji Lee, Min-Hsuan Huang
  • Patent number: 9780053
    Abstract: Various embodiments provide a method of forming a bondpad, wherein the method comprises providing a raw bondpad, and forming a recess structure at a contact surface of the raw bondpad, wherein the recess structure comprises sidewalls being inclined with respect to the contact surface.
    Type: Grant
    Filed: November 15, 2015
    Date of Patent: October 3, 2017
    Assignee: Infineon Technologies AG
    Inventors: Magdalena Hoier, Peter Scherl, Manfred Schneegans
  • Patent number: 9768135
    Abstract: The present disclosure discloses a semiconductor device having conductive bumps formed on a conductive redistribution layer and associated method for manufacturing. The semiconductor device may further include a first type shallow trench formed on a passivation layer overlying a semiconductor substrate. The conductive redistribution layer is formed in the first type shallow trench. A polyimide layer may be formed between neighboring conductive redistribution layers should a plurality of the conductive redistribution layers are formed with or without the first type shallow trench formed for each of the plurality of conductive redistribution layers.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: September 19, 2017
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Ze-Qiang Yao, Fayou Yin, Xiaodan Shang
  • Patent number: 9735119
    Abstract: In some embodiments, the present disclosure provides a conductive pads forming method. The conductive pads forming method may include providing a contact pad or a test pad electrically connected to a semiconductor component; and forming the conductive pads electrically connected to the contact pad or the test pad through the conductive routes, respectively.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: August 15, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Tzung-Han Lee
  • Patent number: 9728503
    Abstract: In some embodiments, the present disclosure relates to a conductive interconnect layer. The conductive interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: August 8, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Hsien Peng, Chi-Liang Kuo, Ming-Han Lee, Hsiang-Huan Lee, Shau-Lin Shue
  • Patent number: 9723716
    Abstract: According to various embodiments, a contact pad structure may be provided, the contact pad structure may include: a dielectric layer structure; at least one contact pad being in physical contact with the dielectric layer structure; the at least one contact pad including a metal structure and a liner structure, wherein the liner structure is disposed between the metal structure of the at least one contact pad and the dielectric layer structure, and wherein a surface of the at least one contact pad is at least partially free from the liner structure, and a contact structure including an electrically conductive material; the contact structure completely covering at least the surface being at least partially free from the liner structure of the at least one contact pad, wherein the liner structure and the contact structure form a diffusion barrier for a material of the metal structure of the at least one contact pad.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: August 1, 2017
    Assignee: Infineon Technologies AG
    Inventor: Dirk Meinhold
  • Patent number: 9633900
    Abstract: A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Wen-Chih Chiou, Fang Wen Tsai, Chen-Yu Tsai
  • Patent number: 9553050
    Abstract: A semiconductor device includes a semiconductor substrate, an interlayer insulating film on the semiconductor substrate and having a first hole extending therethrough, and a contact portion in the first hole of the interlayer insulating film. The contact portion includes a first silicon film along an inner surface of the first hole of the interlayer insulating film.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: January 24, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ming Hu, Akira Yotsumoto
  • Patent number: 9472454
    Abstract: In a tungsten film forming method, a substrate having a recess is provided in a processing chamber, and a first tungsten film is formed on the substrate to fill the recess with a tungsten by simultaneously or alternately supplying WCl6 gas as a tungsten source and a reducing gas under a depressurized atmosphere of the processing chamber, and by reacting the WCl6 gas with the reducing gas while heating the substrate. Then, an opening is formed in the tungsten filled in the recess by supplying WCl6 gas into the processing chamber and etching an upper portion of the tungsten. Thereafter, a second tungsten film is formed on the substrate having the opening by simultaneously or alternately supplying the WCl6 gas and the reducing gas into the processing chamber, and by reacting the WCl6 gas with the reducing gas while heating the substrate.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: October 18, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takanobu Hotta, Yasushi Aiba
  • Patent number: 9385081
    Abstract: A connective structure for bonding semiconductor devices and methods for forming the same are provided. The bonding structure includes an alpad structure, i.e., a thick aluminum-containing connective pad, and a substructure beneath the aluminum-containing pad that includes at least a pre-metal layer and a barrier layer. The pre-metal layer is a dense material layer and includes a density greater than the barrier layer and is a low surface roughness film. The high density pre-metal layer prevents plasma damage from producing charges in underlying dielectric materials or destroying subjacent semiconductor devices.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: July 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Chih Wang, Yao-Hsiang Liang
  • Patent number: 9385085
    Abstract: A metallization layer including a fully clad interconnect and a method of forming a fully clad interconnect. An opening is formed in a dielectric layer, wherein the dielectric layer has a surface and the opening includes walls and a bottom. A diffusion barrier layer and an adhesion layer are deposited on the dielectric layer. An interconnect material is deposited on the dielectric layer and reflowed into the opening forming an interconnect. An adhesion capping layer and diffusion barrier capping layer are deposited over the interconnect. The interconnect is surrounded by the adhesion layer and the adhesion capping layer and the adhesion layer and the adhesion capping layer are surrounded by the diffusion barrier layer and the diffusion capping layer.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: July 5, 2016
    Assignee: Intel Corporation
    Inventors: Manish Chandhok, Hui Jae Yoo, Christopher J. Jezewski, Ramanan V. Chebiam, Colin T. Carver
  • Patent number: 9368474
    Abstract: A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thickn
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: June 14, 2016
    Assignee: J-DEVICES CORPORATION
    Inventors: Hiroaki Matsubara, Tomoshige Chikai, Kiminori Ishido, Takashi Nakamura, Hirokazu Honda, Hiroshi Demachi, Yoshikazu Kumagaya, Shotaro Sakumoto, Shinji Watanabe, Sumikazu Hosoyamada, Shingo Nakamura, Takeshi Miyakoshi, Toshihiro Iwasaki, Michiaki Tamakawa
  • Patent number: 9343408
    Abstract: Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and H2SO4 can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: May 17, 2016
    Assignees: Intermolecular, Inc., GLOBALFOUNDRIES, Inc.
    Inventors: Anh Duong, Errol Todd Ryan
  • Patent number: 9287228
    Abstract: A method of etching a semiconductor structure, comprises contacting an under bump metallization (UBM) with an etching composition. The UBM includes an underlying layer comprising titanium and an overlying layer comprising a second metal. The etching composition is a liquid comprising at least 0.1 wt % hydrofluoric acid and at least 0.1 wt % phosphoric acid.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: March 15, 2016
    Assignee: LAM RESEARCH AG
    Inventors: Harald Kraus, Hebert Schier
  • Patent number: 9257392
    Abstract: The invention provides a semiconductor package with a through silicon via (TSV) interconnect. An exemplary embodiment of the semiconductor package with a TSV interconnect includes a semiconductor substrate, having a front side and a back side. A contact array is disposed on the front side of the semiconductor substrate. An isolation structure is disposed in the semiconductor substrate, underlying the contact array. The TSV interconnect is formed through the semiconductor substrate, overlapping with the contact array and the isolation structure.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: February 9, 2016
    Assignee: MEDIATEK INC.
    Inventors: Ming-Tzong Yang, Yu-Hua Huang, Wei-Che Huang
  • Patent number: 9209426
    Abstract: A light-emitting element with improved heat resistance is provided without losing its advantages such as thinness, lightness, and low power consumption. A light-emitting element is provided which includes a first electrode, a second electrode, and an EL layer between the first electrode and the second electrode, in which the EL layer includes a layer containing a condensed aromatic compound or a condensed heteroaromatic compound, and a layer containing 2,9-bis(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviation: NBPhen) in contact with the layer containing the condensed aromatic compound or the condensed heteroaromatic compound.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: December 8, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tsunenori Suzuki, Toshiki Sasaki, Riho Kataishi, Satoshi Seo
  • Patent number: 9153536
    Abstract: Provided is an Al alloy film for semiconductor devices, which has excellent heat resistance and is suppressed in the generation of hillocks even in cases where the Al alloy film is exposed to high temperatures, and which has low electrical resistivity as a film. The present invention relates to an Al alloy film for semiconductor devices, which is characterized by satisfying all of the features (a)-(c) described below after being subjected to a heat treatment wherein the Al alloy film is held at 500° C. for 30 minutes and by having a film thickness from 500 nm to 5 ?m. (a) The maximum grain diameter of the Al matrix is 800 nm or less. (b) The hillock density is less than 1×109 pieces/m2. (c) The electrical resistivity is 10 ??cm or less.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: October 6, 2015
    Assignee: Kobe Steel, Ltd.
    Inventors: Hiroyuki Okuno, Toshihiro Kugimiya, Yoshihiro Yokota, Takeaki Maeda
  • Patent number: 9105730
    Abstract: A thin film transistor and a fabrication method thereof are provided. A metal patterning layer is formed on the metal oxide semiconductor layer of a thin film transistor to shield the metal oxide semiconductor layer from the water, oxygen and light in the environment.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: August 11, 2015
    Assignee: E Ink Holdings Inc.
    Inventors: Wei-Tsung Chen, Ted-Hong Shinn, Chuang-Chuang Tsai, Chih-Hsiang Yang, Chia-Chun Yeh, Wen-Chung Tang
  • Patent number: 9093385
    Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: July 28, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Anja Gissibl, Hermann Wendt, Thomas Fischer, Bernhard Weidgans, Gudrun Stranzl, Tobias Schmidt, Dietrich Bonart
  • Publication number: 20150137259
    Abstract: A semiconductor device includes a substrate including a conductive region, an insulating layer disposed on the substrate and including an opening exposing the conductive region, and a conductive layer buried within the opening and including a first region disposed on inner side walls of the opening and a second region disposed within the first region. The first region includes a plurality of first crystal grains and the second region includes a plurality of second crystal grains. The pluralities of first and second crystal grains are separated from each other at a boundary formed between the first and second regions.
    Type: Application
    Filed: August 7, 2014
    Publication date: May 21, 2015
    Inventors: Hauk HAN, Yu Min KIM, Ki Hyun YOON, Myoung Bum LEE, Chang Won LEE, Joo Yeon HA
  • Patent number: 9030018
    Abstract: Provided are test vehicles for evaluating various semiconductor materials. These materials may be used for various integrated circuit components, such as embedded resistors of resistive random access memory cells. Also provided are methods of fabricating and operating these test vehicles. A test vehicle may include two stacks protruding through an insulating body. Bottom ends of these stacks may include n-doped poly-silicon and may be interconnected by a connector. Each stack may include a titanium nitride layer provided over the poly-silicon end, followed by a titanium layer over the titanium nitride layer and a noble metal layer over the titanium layer. The noble metal layer extends to the top surface of the insulating body and forms a contact surface. The titanium layer may be formed in-situ with the noble metal layer to minimize oxidation of the titanium layer, which is used as an adhesion and oxygen getter.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: May 12, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Mihir Tendulkar, David Chi
  • Publication number: 20150123279
    Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate and forming a dielectric layer over the semiconductor substrate. An opening is formed in the dielectric layer. A conductive line is formed in the opening, wherein the conductive line has an open void formed therein. A sealing metal layer is formed overlying the conductive line, the dielectric layer, and the open void, wherein the sealing metal layer substantially fills the open void. The sealing metal layer is planarized so that a top surface thereof is substantially level with a top surface of the conductive line. An interconnect feature is formed above the semiconductor substrate, wherein the interconnect feature is electrically coupled with the conductive line and the sealing metal layer-filled open void.
    Type: Application
    Filed: January 9, 2015
    Publication date: May 7, 2015
    Inventors: Chih-Chien Chi, Huang-Yi Huang, Szu-Ping Tung, Ching-Hua Hsieh
  • Patent number: 9018750
    Abstract: Disclosed is a package that includes a wafer substrate and a metal stack seed layer. The metal stack seed layer includes a titanium thin film outer layer. A resist layer is provided in contact with the titanium thin film outer layer of the metal stack seed layer, the resist layer forming circuitry. A method for manufacturing a package is further disclosed. A metal stack seed layer having a titanium thin film outer layer is formed. A resist layer is formed so as to be in contact with the titanium thin film outer layer of the metal stack seed layer, and circuitry is formed from the resist layer.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: April 28, 2015
    Assignee: Flipchip International, LLC
    Inventors: Robert Forcier, Douglas Scott
  • Patent number: 9006900
    Abstract: A connective structure for bonding semiconductor devices and methods for forming the same are provided. The bonding structure includes an alpad structure, i.e., a thick aluminum-containing connective pad, and a substructure beneath the aluminum-containing pad that includes at least a pre-metal layer and a barrier layer. The pre-metal layer is a dense material layer and includes a density greater than the barrier layer and is a low surface roughness film. The high density pre-metal layer prevents plasma damage from producing charges in underlying dielectric materials or destroying subjacent semiconductor devices.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Chih Wang, Yao-Hsiang Liang
  • Patent number: 9006899
    Abstract: In one embodiment method, a first Ti based layer is deposited on the substrate. An intermediate Al based layer is deposited on the first layer, a second NiV based layer is deposited on the intermediate layer, and a third Ag based layer is deposited on the second layer. The layer stack is tempered in such a way that at least one inter-metallic phase is formed between at least two metals of the group containing Ti, Al, Ni and V.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: April 14, 2015
    Assignee: Infineon Technologies AG
    Inventors: Paul Ganitzer, Kurt Matoy, Martin Sporn, Mark Harrison
  • Patent number: 9000596
    Abstract: A MOS transistor having a gate insulator including a dielectric of high permittivity and a conductive layer including a TiN layer, wherein the nitrogen composition in the TiN layer is sub-stoichiometric in its lower portion and progressively increases to a stoichiometric composition in its upper portion.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pierre Caubet, Sylvain Baudot
  • Patent number: 8975670
    Abstract: A semiconductor device, including: a semiconductor substrate with a first layer including first transistors; a shield layer overlaying the first layer; a second layer overlaying the shield layer, the second layer including second transistors; wherein the shield layer is a mostly continuous layer with a plurality of regions for connections between the first transistors and the second transistors, and where the second transistors include monocrystalline regions.
    Type: Grant
    Filed: July 22, 2012
    Date of Patent: March 10, 2015
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Publication number: 20150061138
    Abstract: A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.
    Type: Application
    Filed: November 6, 2014
    Publication date: March 5, 2015
    Inventors: John Moore, Joseph F. Brooks
  • Patent number: 8970043
    Abstract: A wafer structure includes a first wafer stack and a first bonding layer disposed on the first wafer stack. The wafer structure further includes a second wafer stack that includes a first surface and a second surface opposing the first surface. A second bonding layer is disposed on the second surface and is in contact with the first bonding layer. The second wafer stack comprises through-silicon-vias (TSVs) that extend from the first surface to the second bonding layer. A seed layer is disposed on the first surface and is in contact with the TSVs.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: March 3, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Quanbo Zou, Uppili Sridhar, Amit S. Kelkar, Xuejun Ying
  • Publication number: 20150048511
    Abstract: Methods of forming conductive structures and the conductive structures are disclosed. A method includes forming an opening in a dielectric layer over a substrate, performing a cleaning process on the dielectric layer with the opening, forming a nucleation layer in the opening, etching the nucleation layer in the opening, and forming a conductive material in the opening and on the nucleation layer after the etching. An upper portion of the opening is distal from the substrate, and a lower portion of the opening is proximate the substrate. After the etching, a thickness of an upper portion of the nucleation layer in the upper portion of the opening is less than a thickness of a lower portion of the nucleation layer in the lower portion of the opening.
    Type: Application
    Filed: August 19, 2013
    Publication date: February 19, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-I Tsai, Chi-Yuan Chen, Wei-Jung Lin, Chia-Han Lai
  • Publication number: 20150048510
    Abstract: A semiconductor device includes a semiconductor substrate and a metal film formed on the semiconductor substrate. The metal film includes a Ni base and a material having condensation energy higher than that of Ni. In a method of manufacturing a semiconductor device, a semiconductor substrate and a target, which is formed by melting P in Ni, are prepared, and sputtering is performed with the target while a portion of the semiconductor substrate where the metal film is to be formed is heated to a temperature of from 280° C. inclusive to 870° C. inclusive.
    Type: Application
    Filed: April 22, 2013
    Publication date: February 19, 2015
    Inventors: Manabu Tomisaka, Yoshifumi Okabe, Mikimasa Suzuki
  • Patent number: 8952543
    Abstract: A semiconductor device including a lower layer, an insulating layer on a first side of the lower layer, an interconnection structure in the insulating layer, a via structure in the lower layer. The via structure protrudes into the insulating layer and the interconnection structure.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jin Lee, Pil-Kyu Kang, Kyu-Ha Lee, Byung-Lyul Park, Hyun-Soo Chung, Gil-Heyun Choi
  • Patent number: 8952506
    Abstract: A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Wen-Chih Chiou, Fang Wen Tsai, Chen-Yu Tsai
  • Patent number: 8946074
    Abstract: A method of forming a semiconductor device, comprising: providing a Si-containing layer; forming a barrier layer over said Si-containing layer, said barrier layer comprising a compound including a metallic element; forming a metallic nucleation_seed layer over said barrier layer, said nucleation_seed layer including said metallic element; and forming a metallic interconnect layer over said nucleation_seed layer, wherein said barrier layer and said nucleation_seed layer are formed without exposing said semiconductor device to the ambient atmosphere.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: February 3, 2015
    Assignee: Infineon Technologies AG
    Inventor: Heinrich Koerner