Abstract: A method for fabricating a semiconductor device includes the steps of first forming an aluminum (Al) pad on a substrate, forming a passivation layer on the substrate and an opening exposing the Al pad, forming a cobalt (Co) layer in the opening and on the Al pad, bonding a wire onto the Co layer, and then performing a thermal treatment process to form a Co—Pd alloy on the Al pad.

Abstract: Methods and architectures for forming metal line plugs that define separations between two metal line ends, and for forming vias that interconnect the metal lines to an underlying contact. The line plugs are present in-plane with the metal lines while vias connecting the lines are in an underlying plane. One lithographic plate or reticle that prints lines at a given pitch (P) may be employed multiple times, for example each time with a pitch halving (P/2), or pitch quartering (P/4) patterning technique, to define both metal line ends and metal line vias. A one-dimensional (1D) grating mask may be employed in conjunction with cross-grating (orthogonal) masking structures that are likewise amenable to pitch splitting techniques.

Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a top spacer trench adjacent to an upper region of the channel fin. An oxygen-blocking layer is deposited within the top spacer trench and over the upper region of the channel fin. A top spacer is formed within the top spacer trench and over a portion of the oxygen-blocking layer that is within the top spacer trench. The oxygen-blocking layer includes an oxygen gettering material.

Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.

Abstract: A thermoelectric module including at least a first and a second thermoelectric element comprising a thermoelectric semiconductor; an electrode connecting the first and second thermoelectric elements; and at least a first and a second joining layer, the first joining layer positioned between the first thermoelectric element and the electrode, and the second joining layer positioned between the second thermoelectric element and the electrode; and at least a first and a second barrier layer including an alloy including Cu, Mo and Ti, the first barrier layer positioned between the first thermoelectric element and the first joining layer, and the second barrier layer positioned between the second thermoelectric element and the second joining layer.

Abstract: A capacitor having a substrate, a first electrode layer, a dielectric layer, a second electrode layer, and first and second outer electrodes. The substrate has a first main surface and a second main surface opposite to the first main surface. The first electrode layer is on the first main surface of the substrate. The dielectric layer is on at least part of the first electrode layer. The second electrode layer is on at least part of the dielectric layer. The first outer electrode is electrically connected to the first electrode layer and the second outer electrode is electrically connected to the second electrode layer. At least one of the first electrode layer and the first outer electrode and the second electrode layer and the second outer electrode are in contact with each other at a first contact surface. The first contact surface includes a first uneven surface portion.

Abstract: There is provided a semiconductor device including: a first wiring; a second wiring; a dielectric layer configured to insulate the first wiring and the second wiring from each other; and an impedance adjustment layer formed between the first wiring and the second wiring, and configured to adjust an impedance between the first wiring and the second wiring.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The electrically conductive layers include aluminum and silicon and provide low resistance electrically conductive paths as word lines of the three-dimensional memory device. The aluminum-based electrically conductive layers can provide low resistivity, low mechanical stress, and thermal stability for use as high performance word lines.

Abstract: A conductive pattern for a display device includes a first layer including aluminum or an aluminum alloy disposed on a substrate and forming a first taper angle with the substrate, and a second layer disposed on the first layer forming a second taper angle with the first layer, in which the second taper angle is smaller than the first taper angle.

Abstract: An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

Abstract: A multi-layer circuit board is formed multiple layers of a catalytic layer, each catalytic layer having an exclusion depth below a surface, where the cataltic particles are of sufficient density to provide electroless deposition in channels formed in the surface. A first catalytic layer has channels formed which are plated with electroless copper. Each subsequent catalytic layer is bonded or laminated to an underlying catalytic layer, a channel is formed which extends through the catalytic layer to an underlying electroless copper trace, and electroless copper is deposited into the channel to electrically connect with the underlying electroless copper trace. In this manner, traces may be formed which have a thickness greater than the thickness of a single catalytic layer.

Abstract: An integrated circuit structure includes a substrate, a metal pad, a first passivation layer, a second passivation layer, and a conductive bump. The metal pad is over the substrate. The metal pad includes a probing portion and a bumping portion laterally connected to the probing region. The first passivation layer is over the metal pad. The second passivation layer is over the first passivation layer and has an opening. The bumping portion is in the opening. The conductive bump is in the opening of the second passivation layer and contacts the probing portion. The probing portion and the conductive bump are separated by the first passivation layer.

Abstract: A perovskite solar cell and a tandem solar cell are provided. The perovskite solar cell includes a perovskite light-absorbing layer, a first electrode and a second electrode. The first electrode is disposed on a first surface of the perovskite light-absorbing layer. The second electrode is disposed on a second surface of the perovskite light-absorbing layer. The first electrode includes a transparent electrode made of metal-doped molybdenum oxide, and the doped metal is niobium (Nb) or manganese (Mn).

Abstract: Methods for forming a transition metal nitride film on a substrate by atomic layer deposition and related semiconductor device structures are provided. In some embodiments, methods may include contacting a substrate with a first vapor phase reactant comprising a transition metal precursor and contacting the substrate with a second vapor phase reactant comprising an alkyl-hydrazine precursor. In some embodiments, related semiconductor device structures may include a PMOS transistor gate structure, the PMOS transistor gate structure including a transition metal nitride film and a gate dielectric between the transition nitride film and a semiconductor body. The transition metal nitride film includes a predominant (200) crystallographic orientation.

Abstract: A method of forming a semiconductor structure includes the steps: providing a substrate; forming a dielectric over the substrate; forming an opening recessed under a top surface of the dielectric; forming a barrier layer on a sidewall of the opening; performing a physical vapor deposition (PVD) to form a copper layer over the barrier layer, a corner of the opening intersecting with the top surface and the top surface with a predetermined resputter ratio so that the ratio of the thickness of the copper layer on the barrier layer and the thickness of the copper layer over the top surface is substantially greater than 1.

Abstract: An interconnect for a semiconductor device includes an insulator layer having a trench. A barrier layer is formed on a surface of the insulator layer in the trench. An elemental cobalt conductor is formed on the barrier layer.

Abstract: According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.

Abstract: A method for sputtering an aluminum layer on a surface of a semiconductor device is presented. The method includes three sputtering steps for depositing the aluminum layer, where each sputtering step includes at least one sputtering parameter that is different from a corresponding sputtering parameter of another sputtering step. The surface of the semiconductor device includes a dielectric layer having a plurality of openings formed through the dielectric layer.

Abstract: Provided is a semiconductor device that is resistant to the corrosion of titanium nitride forming an anti-reflection film. The semiconductor device includes: a wiring layer which includes a wiring film made of aluminum or an aluminum alloy and formed on a substrate and a titanium nitride film formed on the wiring film; a protection layer which covers a top surface and a side surface of the wiring layer; and a pad portion which penetrates the protection layer and the titanium nitride film, and which exposes the wiring film, the protection layer including a first silicon nitride film, an oxide film, and a second silicon nitride film which are layered in the stated order from the side of the wiring layer.

Abstract: A method includes heating, using a heat source, a reactor vessel including a substrate in a radially central core region of the reactor vessel and introducing, using at least one reactor inlet in an outer wall of the reactor vessel, a precursor gas to the reactor vessel. The at least one reactor inlet is configured to swirling flow of the precursor gas around the radially central core region of the reactor vessel. The material deposits on the substrate from the precursor gas. The method includes removing, using at least one reactor outlet, an exhaust gas from the reactor vessel.

Abstract: A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches. The depositing and the reflowing steps are repeated until the trenches are aggregately filled with the reflow material. The reflow material is planarized to form conductive structures in the trenches.

Abstract: An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

Abstract: Present disclosure provides a semiconductor structure, including a semiconductor substrate having an active side, an interconnect layer over the active side of the semiconductor substrate, and a through substrate via (TSV) extending from the semiconductor substrate to the first metal layer. The interconnect layer includes a first metal layer closest to the active side of the semiconductor substrate, a thickness of the first metal layer is lower than 1 micrometer, and a dimension of a continuous metal feature of the first metal layer is less than 2 micrometer from a top view perspective. The continuous metal feature is cut off by a first dielectric feature. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.

Abstract: A low resistance middle-of-line interconnect structure is formed without liner layers. A contact metal layer is deposited on source/drain regions of field-effect transistors and directly on the surfaces of trenches within a dielectric layer using plasma enhancement. Contact metal fill is subsequently provided by thermal chemical vapor deposition. The use of low-resistivity metal contact materials such as ruthenium is facilitated by the process. The process further facilitates the formation of metal silicide regions on the source/drain regions.

Abstract: A wire bond system. Implementations may include: a bond wire including copper (Cu), a bond pad including aluminum (Al) and a sacrificial anode electrically coupled with the bond pad, where the sacrificial anode includes one or more elements having a standard electrode potential below a standard electrode potential of Al.

Abstract: Provided is a thermoelectric conversion material including a plurality of kinds of phases including a first phase and a second phase which have elemental compositions different from each other. The first phase and the second phase have a skutterudite structure.

Abstract: An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.

Abstract: A method of forming a semiconductor structure includes forming a first insulating layer containing a first metal layer embedded therein and on a surface of a semiconductor substrate. The method further includes forming an inter-layer dielectric (ILD) layer on the first insulating layer, and forming at least one via trench structure including a first metallization trench and a via in the ILD layer. In addition, the method also includes depositing a metal material to form a first metallization layer in the first metallization trench, a via contact in the via, and a second metal layer on top of at least a portion of the first metal layer in the opening of the first insulating layer. The first metal layer and the second metal layer constitute a multilayer metal contact located in the opening of the first insulating layer.

Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first insulating layer is formed over a first surface of the encapsulant and an active surface of the semiconductor die. A second insulating layer is formed over a second surface of the encapsulant opposite the first surface. A conductive layer is formed over the first insulating layer. The conductive layer includes a line-pitch or line-spacing of less than 5 ?m. The active surface of the semiconductor die is recessed within the encapsulant. A third insulating layer is formed over the semiconductor die including a surface of the third insulating layer coplanar with a surface of the encapsulant. The second insulating layer is formed prior to forming the conductive layer. A trench is formed in the first insulating layer. The conductive layer is formed within the trench.

Abstract: A thin film for a lead for brain applications includes at least one section comprising a high conductive metal and a low conductive metal, whereby the low conductive metal is a biocompatible metal and has a lower electrical conductivity than the high conductive metal and whereby the high conductive metal is at least partially encapsulated by the low conductive metal. Furthermore, the present invention relates to a method of manufacturing a thin film for a lead for brain applications and a deep brain stimulation system.

Abstract: A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads includes a metal bond pad area. A cobalt including connection layer is deposited directly on the metal bond pad area. The cobalt including connection layer is patterned to provide a cobalt bond pad surface for the plurality of bond pads, and a solder material is formed on the cobalt bond pad surface.

Abstract: The present disclosure relates to redistribution layer structures useful in semiconductor substrate packages, semiconductor package structures, and chip structures. In an embodiment, a redistribution layer structure includes a dielectric layer, an anti-plating layer, and a conductive material. The dielectric layer defines one or more trenches. The conductive material is disposed in the trench(es), and the anti-plating layer is disposed on a surface of the dielectric layer.

Abstract: An interconnect structure including a substrate, a dielectric layer, a first conductive pattern, and a second conductive pattern is provided. The dielectric layer is disposed on the substrate and has an opening. The first conductive pattern is disposed in the opening. The second conductive pattern is disposed on the first conductive pattern and exposes an exposed portion of the first conductive pattern. The exposed portion of the first conductive pattern has a notch.

Abstract: Various embodiments provide a method of forming a bondpad, wherein the method comprises providing a raw bondpad, and forming a recess structure at a contact surface of the raw bondpad, wherein the recess structure comprises sidewalls being inclined with respect to the contact surface.

Abstract: The present disclosure discloses a semiconductor device having conductive bumps formed on a conductive redistribution layer and associated method for manufacturing. The semiconductor device may further include a first type shallow trench formed on a passivation layer overlying a semiconductor substrate. The conductive redistribution layer is formed in the first type shallow trench. A polyimide layer may be formed between neighboring conductive redistribution layers should a plurality of the conductive redistribution layers are formed with or without the first type shallow trench formed for each of the plurality of conductive redistribution layers.

Abstract: In some embodiments, the present disclosure provides a conductive pads forming method. The conductive pads forming method may include providing a contact pad or a test pad electrically connected to a semiconductor component; and forming the conductive pads electrically connected to the contact pad or the test pad through the conductive routes, respectively.

Abstract: In some embodiments, the present disclosure relates to a conductive interconnect layer. The conductive interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.

Abstract: According to various embodiments, a contact pad structure may be provided, the contact pad structure may include: a dielectric layer structure; at least one contact pad being in physical contact with the dielectric layer structure; the at least one contact pad including a metal structure and a liner structure, wherein the liner structure is disposed between the metal structure of the at least one contact pad and the dielectric layer structure, and wherein a surface of the at least one contact pad is at least partially free from the liner structure, and a contact structure including an electrically conductive material; the contact structure completely covering at least the surface being at least partially free from the liner structure of the at least one contact pad, wherein the liner structure and the contact structure form a diffusion barrier for a material of the metal structure of the at least one contact pad.

Abstract: A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via.

Abstract: A semiconductor device includes a semiconductor substrate, an interlayer insulating film on the semiconductor substrate and having a first hole extending therethrough, and a contact portion in the first hole of the interlayer insulating film. The contact portion includes a first silicon film along an inner surface of the first hole of the interlayer insulating film.

Abstract: In a tungsten film forming method, a substrate having a recess is provided in a processing chamber, and a first tungsten film is formed on the substrate to fill the recess with a tungsten by simultaneously or alternately supplying WCl6 gas as a tungsten source and a reducing gas under a depressurized atmosphere of the processing chamber, and by reacting the WCl6 gas with the reducing gas while heating the substrate. Then, an opening is formed in the tungsten filled in the recess by supplying WCl6 gas into the processing chamber and etching an upper portion of the tungsten. Thereafter, a second tungsten film is formed on the substrate having the opening by simultaneously or alternately supplying the WCl6 gas and the reducing gas into the processing chamber, and by reacting the WCl6 gas with the reducing gas while heating the substrate.

Abstract: A connective structure for bonding semiconductor devices and methods for forming the same are provided. The bonding structure includes an alpad structure, i.e., a thick aluminum-containing connective pad, and a substructure beneath the aluminum-containing pad that includes at least a pre-metal layer and a barrier layer. The pre-metal layer is a dense material layer and includes a density greater than the barrier layer and is a low surface roughness film. The high density pre-metal layer prevents plasma damage from producing charges in underlying dielectric materials or destroying subjacent semiconductor devices.

Abstract: A metallization layer including a fully clad interconnect and a method of forming a fully clad interconnect. An opening is formed in a dielectric layer, wherein the dielectric layer has a surface and the opening includes walls and a bottom. A diffusion barrier layer and an adhesion layer are deposited on the dielectric layer. An interconnect material is deposited on the dielectric layer and reflowed into the opening forming an interconnect. An adhesion capping layer and diffusion barrier capping layer are deposited over the interconnect. The interconnect is surrounded by the adhesion layer and the adhesion capping layer and the adhesion layer and the adhesion capping layer are surrounded by the diffusion barrier layer and the diffusion capping layer.

Abstract: A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thickn

Abstract: Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and H2SO4 can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.

Abstract: A method of etching a semiconductor structure, comprises contacting an under bump metallization (UBM) with an etching composition. The UBM includes an underlying layer comprising titanium and an overlying layer comprising a second metal. The etching composition is a liquid comprising at least 0.1 wt % hydrofluoric acid and at least 0.1 wt % phosphoric acid.

Abstract: The invention provides a semiconductor package with a through silicon via (TSV) interconnect. An exemplary embodiment of the semiconductor package with a TSV interconnect includes a semiconductor substrate, having a front side and a back side. A contact array is disposed on the front side of the semiconductor substrate. An isolation structure is disposed in the semiconductor substrate, underlying the contact array. The TSV interconnect is formed through the semiconductor substrate, overlapping with the contact array and the isolation structure.

Abstract: A light-emitting element with improved heat resistance is provided without losing its advantages such as thinness, lightness, and low power consumption. A light-emitting element is provided which includes a first electrode, a second electrode, and an EL layer between the first electrode and the second electrode, in which the EL layer includes a layer containing a condensed aromatic compound or a condensed heteroaromatic compound, and a layer containing 2,9-bis(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviation: NBPhen) in contact with the layer containing the condensed aromatic compound or the condensed heteroaromatic compound.

Abstract: Provided is an Al alloy film for semiconductor devices, which has excellent heat resistance and is suppressed in the generation of hillocks even in cases where the Al alloy film is exposed to high temperatures, and which has low electrical resistivity as a film. The present invention relates to an Al alloy film for semiconductor devices, which is characterized by satisfying all of the features (a)-(c) described below after being subjected to a heat treatment wherein the Al alloy film is held at 500° C. for 30 minutes and by having a film thickness from 500 nm to 5 ?m. (a) The maximum grain diameter of the Al matrix is 800 nm or less. (b) The hillock density is less than 1×109 pieces/m2. (c) The electrical resistivity is 10 ??cm or less.

Abstract: A thin film transistor and a fabrication method thereof are provided. A metal patterning layer is formed on the metal oxide semiconductor layer of a thin film transistor to shield the metal oxide semiconductor layer from the water, oxygen and light in the environment.