Abstract: A method of fabricating a semiconductor device includes forming a first film having a first film stress type and a first film stress intensity over a substrate and forming a second film having a second film stress type and a second film stress intensity over the first film. The second film stress type is different than the first film stress type. The second film stress intensity is about same as the first film stress intensity. The second film compensates stress induced effect of non-flatness of the substrate by the first film.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a semiconductor substrate, a plurality of first conductive elements separately positioned above the semiconductor substrate, a plurality of first supporting pillars respectively correspondingly positioned between an adjacent pairs of the plurality of first set conductive elements, and a plurality of spaces respectively correspondingly positioned adjacent to the plurality of first set supporting pillars.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a dual airgap structure and methods of manufacture. The structure includes: a lower metal line; a plurality of upper metal lines; and a first airgap between the lower metal line and at least one upper metal line of the plurality of upper metal lines.

Abstract: A method of manufacturing a semiconductor device includes assigning a plurality of chip regions on an epitaxial-growth layer of a semiconductor substrate where the epitaxial-growth layer is grown on a bulk layer and forming a plurality of device structures on the plurality of chip regions, respectively, thinning the semiconductor substrate from a bottom-surface side of the bulk layer, bonding a supporting-substrate on a bottom surface of the thinned semiconductor substrate, selectively removing the supporting-substrate so that the bottom surface of the semiconductor substrate is exposed, at locations corresponding to positions of each of main current paths in the plurality of device structures, respectively, dicing the semiconductor substrate together with the supporting-substrate along dicing lanes between the plurality of the chip regions so as to form a plurality of chips.

Abstract: A method for integrating epitaxial, metallic transition metal nitride (TMN) layers within a compound semiconductor device structure. The TMN layers have a similar crystal structure to relevant semiconductors of interest such as silicon carbide (SiC) and the Group III-Nitrides (III-Ns) such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and their various alloys. Additionally, the TMN layers have excellent thermal stability and can be deposited in situ with other semiconductor materials, allowing the TMN layers to be buried within the semiconductor device structure to create semiconductor/metal/semiconductor heterostructures and superlattices.

Abstract: A structure of an under bump metallization and a method of forming the same are provided. The under bump metallization has a redistribution via hole, viewed from the top, in a round shape or a polygon shape having an angle between adjacent edges greater than 90°. Therefore, the step coverage of the later formed metal layer can be improved.

Abstract: An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a dielectric layer to create a high density layer. The treatment may include, for example, creating a high density monolayer using hexamethyldisilazane (HMDS), trimethylsilydiethylamine (TMSDEA) or trimethylsilylacetate (OTMSA). After treating, the dielectric layer may be patterned to create openings, which are subsequently filled with a conductive material. Excess conductive material may be removed using, for example, a chemical mechanical polishing.

Abstract: A device comprises a first rounded metal line in a metallization layer over a substrate, a second rounded metal line in the metallization layer, a first air gap between sidewalls of the first rounded metal line and the second metal line, a first metal line in the metallization layer, wherein a top surface of the first metal line is higher than a top surface of the second rounded metal line and a bottom surface of the first metal line is substantially level with a bottom surface of the second rounded metal line and a second air gap between sidewalls of the second rounded metal line and the first metal line.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. A semiconductor device includes a contact hole formed over a semiconductor substrate so as to open an active region, a contact plug coupled to the active region in the contact hole and having a height lower than that of the contact hole, and a bit line that is coupled to the contact plug and has the same width as the contact plug. When forming a bit line of a cell region, a barrier metal layer is formed between a bit line contact plug and a bit line conductive layer, such that interfacial resistance is reduced, a thickness of the bit line conductive layer is increased, conductivity is improved, and the height of overall bit line is reduced, resulting in reduction in parasitic capacitance.

Abstract: An electrical connection structure with a via hole, an array substrate and a display device are provided, and the electrical connection structure with the via hole includes: a first insulating layer disposed on a first electrical conductor and under a second electrical conductor and provided with a first via hole which overlaps the first electrical conductor and the second electrical conductor; and a conductive connection portion which passes through the first via hole, electrically connects the first electrical conductor to the second electrical conductor, and is electrically connected with at least one lateral surface of the first electrical conductor. The electrical connection structure with the via hole can solve the problem of a poor contact between the first electrical conductor and the conductive connection portion which is formed in the via hole.

Abstract: A structure includes a substrate, and a first metal line and a second metal line over the substrate, with a space therebetween. A first air gap is on a sidewall of the first metal line and in the space, wherein an edge of the first metal line is exposed to the first air gap. A second air gap is on a sidewall of the second metal line and in the space, wherein an edge of the second metal line is exposed to the second air gap. A dielectric material is disposed in the space and between the first and the second air gaps.

Abstract: A method for manufacturing a semiconductor device that includes steps of: (1) adhering a support substrate to a first surface of a wafer using an adhesive, the wafer including first and second scribe lines extending along first and second directions, respectively, (2) thinning the wafer, (3) forming a groove in a first scribe line excluding a region located in an outer peripheral portion of the wafer, the groove piercing the wafer from the first surface to a second surface opposite to the first surface to expose the adhesive, the first scribe line and the second scribe line demarcating chip regions; and (4) removing the adhesive by immersing the wafer adhered to the support substrate in a solvent such that the solvent permeates into the groove.

Abstract: Fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines and depositing a protective cap on at least some of the one or more conductive lines. Alternatively, fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines, wherein the conductive lines have sub-eighty nanometer pitches, and depositing a protective cap on at least some of the conductive lines, wherein the protective cap has a thickness between approximately five and fifteen nanometers. Alternatively, fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines, wherein the conductive lines have sub-eighty nanometer line widths, and depositing a protective cap on at least some of the conductive lines, wherein the protective cap has a thickness between approximately five and fifteen nanometers.

Abstract: An integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal. Alternatively, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices and having sub-eighty nanometer pitches, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal, wherein the protective cap has a thickness between approximately five and fifteen nanometers.

Abstract: According to an embodiment, a non-volatile memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction orthogonal to the first direction. The device includes third wirings, and a first and a second memory. The third wirings extend in a third direction crossing the first direction and orthogonal to the second direction, and aligned in the second direction on both sides of the second wiring. The first memory is provided between one of third wiring pair and the second wiring, the pair of third wirings facing each other across the second wiring. The second memory is provided between another one of the third wiring pair and the second wiring. The second wiring has a block portion between a first portion in contact with the first memory and a second portion in contact with the second memory.

Abstract: A method for manufacturing a contact plug is provided. The method includes providing a silicon substrate having at least one opening. A titanium layer is conformably formed in the opening. A first barrier layer is conformably formed on the titanium layer in the opening. A rapid thermal process is performed on the titanium layer and the first barrier layer. After performing the rapid thermal process, a second barrier layer is conformably formed on the first barrier layer in the opening.

Abstract: A method includes forming a first metal liner conformally along a sidewall and a bottom of a contact opening. A second metal liner is formed above and in direct contact with the first metal liner, a grain size of the first metal liner is larger than a grain size of the second metal liner. A barrier layer is formed above and in direct contact with the second metal liner and the contact opening is filled with a conductive material to form a middle-of-the-line contact.

Abstract: A method of making a semiconductor device is disclosed. A device is fabricated on a semiconductor body. A gate electrode is disposed over the semiconductor body with a gate dielectric between the gate electrode and the semiconductor body, wherein the gate dielectric has a length greater than the gate electrode. A first source/drain region is disposed within the semiconductor body adjacent to the first edge of the gate with the gate dielectric at least partially overlapping the first source/drain region, and a second source/drain region is disposed within the semiconductor body adjacent to the first edge of the gate with the gate dielectric at least partially overlapping the second source/drain region.

Abstract: In one embodiment method, a first Ti based layer is deposited on the substrate. An intermediate Al based layer is deposited on the first layer, a second NiV based layer is deposited on the intermediate layer, and a third Ag based layer is deposited on the second layer. The layer stack is tempered in such a way that at least one inter-metallic phase is formed between at least two metals of the group containing Ti, Al, Ni and V.

Abstract: A semiconductor device and method are disclosed. The semiconductor device includes a substrate having a first region and a second region and an insulating layer arranged on the substrate. A first conductive layer is arranged in or on insulating layer in the first region and a second conductive layer is arranged in or on the insulating layer in the second region. The first conductive layer comprises a first conductive material and the second conductive layer comprises a second conductive material wherein the first conductive material is different than the second conductive material. A metal layer is arranged on the first conductive layer.

Abstract: A connective structure for bonding semiconductor devices and methods for forming the same are provided. The bonding structure includes an alpad structure, i.e., a thick aluminum-containing connective pad, and a substructure beneath the aluminum-containing pad that includes at least a pre-metal layer and a barrier layer. The pre-metal layer is a dense material layer and includes a density greater than the barrier layer and is a low surface roughness film. The high density pre-metal layer prevents plasma damage from producing charges in underlying dielectric materials or destroying subjacent semiconductor devices.

Abstract: A MOS transistor having a gate insulator including a dielectric of high permittivity and a conductive layer including a TiN layer, wherein the nitrogen composition in the TiN layer is sub-stoichiometric in its lower portion and progressively increases to a stoichiometric composition in its upper portion.

Abstract: A semiconductor device, including: a semiconductor substrate with a first layer including first transistors; a shield layer overlaying the first layer; a second layer overlaying the shield layer, the second layer including second transistors; wherein the shield layer is a mostly continuous layer with a plurality of regions for connections between the first transistors and the second transistors, and where the second transistors include monocrystalline regions.

Abstract: A method of manufacturing a semiconductor device provided with an interlayer insulating film formed on a semiconductor substrate, and a plurality of wiring layers formed on the interlayer insulating film. The method includes forming of a first wiring layer closest to the semiconductor substrate among the plurality of wiring layers, and forming of an alloy of a titanium layer and a metal layer by heating treatment. The forming of the first wiring layer includes: forming of a titanium layer on an interlayer insulating film; forming of a metal layer containing a metal capable of forming an alloy with titanium in the titanium layer; forming of an orientation layer on the metal layer; and forming of an aluminum layer on the orientation layer.

Abstract: A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.

Abstract: A method for fabricating packaged semiconductor devices; attaching a batch-sized metallic grid with openings onto an adhesive tape having an insulating clear core covered by a layer of UV-releasable adhesive, the openings sized larger than a semiconductor chip; attaching a semiconductor chip onto the tape of each window, the chip terminals facing the adhesive surface; laminating insulating material of low coefficient of thermal expansion to fill gaps between each chip and respective grid; turning over assembly to place a carrier under backside of chips and lamination and to remove the tape; plasma-cleaning the assembly front side and sputtering uniform at least one metal layer across the assembly; optionally plating metal layers; and patterning the metal layers to form rerouting traces and extended contact pads for assembly.

Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.

Abstract: Structures and methods of forming the same are disclosed herein. In one embodiment, a structure can comprise a region having first and second oppositely facing surfaces. A barrier region can overlie the region. An alloy region can overlie the barrier region. The alloy region can include a first metal and one or more elements selected from the group consisting of silicon (Si), germanium (Ge), indium (Id), boron (B), arsenic (As), antimony (Sb), tellurium (Te), or cadmium (Cd).

Abstract: One or more embodiments relate to a method of forming a semiconductor device, comprising: forming a structure, the structure including at least a first element and a second element; and forming a passivation layer over the structure, the passivation layer including at least the first element and the second element, the first element and the second element of the passivation layer coming from the structure.

Abstract: A hybridization method comprises providing a first IC, depositing a first metal layer over electrical contacts on the IC, depositing an insulating layer over the first metal layer and contacts, providing recesses in the insulating layer above each contact, and depositing metal such that the sidewalls of the recesses provide electrical continuity between the top of each recess and the electrical contact it is above. The recesses are backfilled with a sacrificial planarization material and planarized, and a second metal layer is deposited, patterned and etched over each backfilled recess to form openings over each recess and to separate the pixels. The sacrificial planarization material is removed to form compliant structures overhanging the recesses and thereby creating micro-sockets capable of receiving corresponding conductive pins associated with a mating IC. Electrical contact between the first and mating ICs is accomplished through shear between the pins and the micro-sockets.

Abstract: Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer.

Abstract: According to one embodiment, a semiconductor device includes a metal interconnect and a graphene interconnect which are stacked to one another.

Abstract: Electrodes, which contain molybdenum dioxide (MoO2) can be used in electronic components, such as memory or logic devices. The molybdenum-dioxide containing electrodes can also have little or no molybdenum element, together with a portion of molybdenum oxide, e.g., MoOx with x between 2 and 3. The molybdenum oxide can be present as molybdenum trioxide MoO3, or in Magneli phases, such as Mo4O11, MO8O23, or Mo9O26. The molybdenum-dioxide containing electrodes can be formed by annealing a multilayer including a layer of molybdenum and a layer of molybdenum oxide. The oxygen content of the multilayer can be configured to completely, or substantially completely, react with molybdenum to form molybdenum dioxide, together with leaving a small excess amount of molybdenum oxide MoOx with x>2.

Abstract: A graphene and metal interconnect structure and methods of making the same are disclosed. The graphene is a multiple layer graphene structure that is grown using a graphene catalyst. The graphene forms an electrical connection between two or more VIAs or components, or a combination of VIAs and components. A VIA includes a fill metal, with at least a portion of the fill metal being surrounded by a barrier metal. A component may be a routing track, a clock signal source, a power source, an electromagnetic signal source, a ground terminal, a transistor, a macrocell, or a combination thereof. The graphene is grown, using a graphene catalyst, from both solid and liquid carbon sources using chemical vapor deposition (CVD) at a temperature between 300° C.-400° C. The graphene catalyst can be an elemental form of, or alloy including, nickel, palladium, ruthenium, iridium or copper.

Abstract: Methods for forming structures to use in atomic force probing of a conductive feature embedded in a dielectric layer and structures for use in atomic force probing. An insulator layer is formed on the dielectric layer such that the conductive feature is covered. A contact hole penetrates from a top surface of the insulator layer through the insulator layer to the conductive feature. The contact hole is at least partially filled with a conductive stud that is in electrical contact with the conductive feature and exposed at the top surface of the insulator layer so as to define a structure. A probe tip of an atomic force probe tool is landed on a portion of the structure and used to electrically characterize a device structure connected with the conductive feature.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes: forming a silicon oxide film on a semiconductor substrate; forming a via in the silicon oxide film; forming a contact layer inside the via; forming a silicon layer on the contact layer; and forming a tungsten film embedded in the via by making a tungsten-containing gas react with the silicon layer.

Abstract: To provide: a technique capable of suppressing a titanium nitride film that is exposed at the side surface of an opening from turning into a titanium oxide film even when water permeates the opening over a pad from outside a semiconductor device and thus improving the reliability of the semiconductor device; and a technique capable of suppressing a crack from occurring in a surface protective film of a pad and improving the reliability of a semiconductor device. An opening is formed so that the diameter of the opening is smaller than the diameter of another opening and the opening is included in the other opening. Due to this, it is possible to cover the side surface of an antireflection film that is exposed at the side surface of the other opening with a surface protective film in which the opening is formed. As a result of this, it is possible to form a pad without exposing the side surface of the antireflection film.

Abstract: A manufacturing method of a MOS device with memory function is provided, which includes: providing a semiconductor substrate, a surface of the semiconductor substrate being covered by a first dielectric layer, a metal interconnect structure being formed in the first dielectric layer; forming a second dielectric layer overlying a surface of the first dielectric layer and the metal interconnect structure; forming an opening in the second dielectric layer, a bottom of the opening revealing the metal interconnect structure; forming an alloy layer at the bottom of the opening, material of the alloy layer containing copper and other metal; and performing a thermal treatment to the alloy layer and the metal interconnect structure to form, on the surface of the metal interconnect structure, a compound layer containing oxygen element. The compound layer containing oxygen element and the MOS device formed in the semiconductor substrate constitute a MOS device with memory function.

Abstract: An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by minimizing oxygen intrusion into a seed layer and an electroplated copper layer of the interconnect structure, are disclosed. At least one opening in a dielectric layer is formed. A sacrificial oxidation layer disposed on the dielectric layer is formed. The sacrificial oxidation layer minimizes oxygen intrusion into the seed layer and the electroplated copper layer of the interconnect structure. A barrier metal layer disposed on the sacrificial oxidation layer is formed. A seed layer disposed on the barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the sacrificial oxidation layer, the barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.

Abstract: A manufacturing method of a semiconductor device including an electrode having low contact resistivity to a nitride semiconductor is provided. The manufacturing method includes a carbon containing layer forming step of forming a carbon containing layer containing carbon on a nitride semiconductor layer, and a titanium containing layer forming step of forming a titanium containing layer containing titanium on the carbon containing layer. A complete solid solution Ti (C, N) layer of TiN and TiC is formed between the titanium containing layer and the nitride semiconductor layer. As a result, the titanium containing layer comes to be in ohmic contact with the nitride semiconductor layer throughout the border therebetween.

Abstract: A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first interconnect pattern formed therein. During the formation of the self-aligned tungsten nitride passivation layer, a nitrogen enriched dielectric surface also forms within exposed surface of the MOL dielectric material. A second interconnect pattern is then formed adjacent to, but not connect with, the first interconnect pattern. Because of the presence of the self-aligned tungsten nitride passivation layer on the tungsten region, no damaging and/or contamination of the tungsten region can occur.

Abstract: A semiconductor component including a first layer (10) of a semiconductor material as a substrate, a second layer (12) running on said first layer (10), and at least two intermediate layers (14, 16) made of the materials of the first and second layers running between the first and second layer, where the first intermediate layer (16) facing the second layer (12) may contain a eutectic mixture (18) made of the materials of the first and second layers. The invention is also directed to an electroconductive contact (15, 15a, 15b) forming an electroconductive connection to the first layer and originating at or running through the second layer, as well as to a method for producing the metal-semiconductor contact.

Abstract: A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first interconnect pattern formed therein. During the formation of the self-aligned tungsten nitride passivation layer, a nitrogen enriched dielectric surface also forms within exposed surface of the MOL dielectric material. A second interconnect pattern is then formed adjacent to, but not connect with, the first interconnect pattern. Because of the presence of the self-aligned tungsten nitride passivation layer on the tungsten region, no damaging and/or contamination of the tungsten region can occur.

Abstract: A CVD showerhead that includes a circular inner showerhead and at least one outer ring showerhead. At least two process gas delivery tubes are coupled to each showerhead. Also, a dual showerhead that includes a circular inner showerhead and at least one outer ring showerhead where each showerhead is coupled to oxygen plus a gas mixture of lead, zirconium, and titanium organometallics. A method of depositing a CVD thin film on a wafer. Also, a method of depositing a PZT thin film on a wafer.

Abstract: A CVD showerhead that includes a circular inner showerhead and at least one outer ring showerhead. At least two process gas delivery tubes are coupled to each showerhead. Also, a dual showerhead that includes a circular inner showerhead and at least one outer ring showerhead where each showerhead is coupled to oxygen plus a gas mixture of lead, zirconium, and titanium organometallics. A method of depositing a CVD thin film on a wafer. Also, a method of depositing a PZT thin film on a wafer.

Abstract: An IC device comprises a stack of contact levels, each including conductive layer and an insulation layer. A dielectric liner surrounds an interlevel conductor within an opening in the stack of contact levels. The opening passes through a portion of the stack of contact levels. The interlevel conductor is electrically insulated from the conductive layers of each of the contact levels through the dielectric liner. A portion of the conductive layer at the opening is recessed relative to adjacent insulation layers. The dielectric liner may have portions extending between adjacent insulation layers.

Abstract: A semiconductor device with overlapping contacts is provided. In one aspect, the semiconductor device includes a dielectric layer; a first contact located in the dielectric layer; and a second contact located in the dielectric layer adjacent to the first contact, wherein a portion of the second contact overlaps a top surface of the first contact.

Abstract: A wafer with a eutectic bonding carrier and a method of manufacturing the same are disclosed, wherein the wafer comprises a thinned wafer, a eutectic bonding layer formed on the backside of said thinned wafer, a eutectic bonding carrier attached on said eutectic bonding layer, and a plurality of openings formed at the active side of said thinned wafer and exposing said eutectic bonding layer on the backside of said thinned wafer.

Abstract: An improved alignment structure for photolithographic pattern alignment is disclosed. A topographical alignment mark in an IC under a low reflectivity layer may be difficult to register. A reflective layer is formed on top of the low reflectivity layer so that the topography of the alignment mark is replicated in the reflective layer, enabling registration of the alignment mark using common photolithographic scanners and steppers. The reflective layer may be one or more layers, and may be metallic, dielectric or both. The reflective layer may be global over the entire IC or may be local to the alignment mark area. The reflective layer may be removed during subsequent processing, possibly with assist from an added etch stop layer, or may remain in the completed IC. The disclosed alignment mark structure is applicable to an IC with a stack of ferroelectric capacitor materials.

Abstract: A semiconductor structure includes a first metal-containing layer, a dielectric capping layer, a second metal-containing layer, and a conductive pad. The first metal-containing layer includes a set of metal structures, a dielectric filler disposed to occupy a portion of the first metal-containing layer, and an air-gap region defined by at least the set of metal structures and the dielectric filler and abutting at least a portion of the set of metal structures. The second metal-containing layer includes at least a via plug electrically connected to a portion of the set of metal structures. The conductive pad and the via plug do not overlap the air-gap region.