Abstract: According to the method for manufacturing a semiconductor device, a surface of a lower insulating film (55) is planarized by CMP or the like, and an upper insulating film (56) and a protective metal film (59) are formed on the lower insulating film (55). Accordingly, the upper insulating film (56) and the protective metal film (59) are formed in such a manner they have an excellent coverage and the water/hydrogen blocking capability of the upper insulating film (56) and the protective metal film (59) is maximized.

Abstract: A method and system for improving planarization and uniformity of dielectric layers for providing improved optical efficiency in CCD and CMOS image sensor devices. In various embodiments, a dielectric planarization method for achieving better optical efficiency includes first depositing a first dielectric having an optically transparent property on and around a metal pattern. Optical sensors are formed in or on the substrate in areas between metal features. The metal pattern protects a sensor situated therebetween and thereunder from electromagnetic radiation. After the first dielectric layer is polished using CMP, a slanted or inclined surface is produced but this non-uniformity is eliminated using further planarization processes that produce a uniform total dielectric thickness for the proper functioning of the sensor.

Abstract: A semiconductor device includes a semiconductor layer, an electrode pad that is composed of Au and is provided on the semiconductor layer, a silicon nitride film provided on the semiconductor layer and the electrode pad so that an end portion of the silicon nitride film is located, and a metal layer that contacts a part of a surface of the electrode pad and the end portion of the silicon nitride film and is provided so that another part of the surface of the electrode pad is exposed, the metal layer including any of Ti, Ta and Pt.

Abstract: An integrated circuit system comprised by forming a first region, a second region and a third region within a dielectric over a substrate. The first region includes tungsten plugs. The second region is formed adjacent at least a portion of the perimeter of the first region and the third region is formed between the first region and the second region. An opening is formed in the third region and a material is deposited within the opening for preventing erosion of the first region.

Abstract: Contacts having use in an integrated circuit and exemplary methods of forming the contacts are disclosed. The methods involve forming a conductive cap over a metal plug. The invention can mitigate keyholes in the contacts by capping and encapsulating the conductive material used to form the contact. The exemplary cap may be made of a nitride material.

Abstract: An oxide or nitride semiconductor layer is formed over a substrate. A first conductive layer including a first element and a second element, and a second conductive layer including the second element are formed over the semiconductor layer. The first element is oxidized or nitrogenized near an interface region between the first conductive layer and the oxide or nitride semiconductor layer by heat treatment or laser irradiation. The Gibbs free energy of oxide formation of the first element is lower than those of the second element or any element in the oxide or nitride semiconductor layer.

Abstract: A method and device of nanostructured titania that is crack free. A method in accordance with the present invention comprises depositing a Ti film on a surface, depositing a masking layer on the Ti film, etching said masking layer to expose a limited region of the Ti film, the limited region being of an area less than a threshold area, oxidizing the exposed limited region of the Th.ucsbi film, and annealing the exposed limited region of the Ti film.

Abstract: Provided is a metal interconnection structure of a semiconductor device, including a first metal film pattern disposed on an upper part of an insulation film of a semiconductor substrate; an intermetallic dielectric film having a metal contact plug in which a barrier layer, a metal film for contact plug and a second metal film are sequentially disposed, on the first metal film pattern; and a second metal film pattern disposed on the metal contact plug and intermetallic dielectric film and connected to the metal contact plug.

Abstract: A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained.

Abstract: A transparent, electrically conductive composite includes a layer of molybdenum oxide or nickel oxide deposited on a layer of zinc oxide layer. The molybdenum component exists in a mixed valence state in the molybdenum oxide. The nickel component exists in a mixed valence state in the nickel oxide. The composite may be utilized in various electronic devices, including optoelectronic devices. In particular, the composite may be utilized as a transparent conductive electrode. As compared to conventional transparent conduct oxides such as indium tin oxide, the composite exhibits superior properties, including a higher work function.

Abstract: A method for fabricating a semiconductor device is provided. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a first insulating layer, a first conductive layer and a chemical mechanical polishing (CMP) stop layer over the semiconductor substrate in sequence; forming openings in the chemical mechanical polishing (CMP) stop layer and the underlying first conductive layer to expose the first insulating layer, thereby leaving a patterned chemical mechanical polishing (CMP) stop layer and a patterned first conductive layer; forming a second insulating layer on the patterned chemical mechanical polishing (CMP) stop layer, filling in the openings; performing a planarization process to remove a portion of the second insulating layer until the patterned chemical mechanical polishing (CMP) stop layer is exposed, thereby leaving a remaining second insulating layer in the openings; removing the patterned chemical mechanical polishing (CMP) stop layer.

Abstract: A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of metal. The layer of metal silicide is patterned to define the boundaries of the local interconnect. The metal silicide is reacted with the layer of metal to form a composite structure. The composite structure includes the metal silicide, another metal silicide formed as silicon from the metal silicide reacts with the underlying layer of metal and an intermetallic compound of the metal from the layer of metal and metal from the layer of metal silicide. The unreacted layer of metal is removed with the composite structure remaining as the local interconnect.

Abstract: A functional perovskite cell formed on a silicon substrate layer and including a functional layer of bismuth ferrite (BiFeO3 or BFO) sandwiched between two electrode layers. An optional intermediate template layer, for example, of strontium titanate allows the bismuth ferrite layer to be crystallographically aligned with the silicon substrate layer. Other barrier layers of platinum or an intermetallic alloy produce a polycrystalline BFO layer. The cell may be configured as a non-volatile memory cell or a MEMS structure respectively depending upon the ferroelectric and piezoelectric character of BFO. Lanthanum substitution in the BFO increases ferroelectric performance. The films may be grown by MOCVD using a heated vaporizer.

Abstract: Semiconductor interconnect structures including a surface-repair material, e.g., a noble metal or noble metal alloy, that fills hollow-metal related defects located within a conductive material are provided. The filling of the hollow-metal related defects with the surface repair material improves the electromigration (EM) reliability of the structure as well as decreasing in-line defect related yield loss.

Abstract: An interconnect structure including a noble metal-containing cap that is present at least on some portion of an upper surface of at least one conductive material that is embedded within an interconnect dielectric material is provided. In one embodiment, the noble metal-containing cap is discontinuous, e.g., exists as nuclei or islands on the surface of the at least one conductive material. In another embodiment, the noble metal-containing cap has a non-uniform thickness across the surface of the at least one conductive material.

Abstract: A metal/metal nitride barrier layer for semiconductor device applications. The barrier layer is particularly useful in contact vias where high conductivity of the via is important, and a lower resistivity barrier layer provides improved overall via conductivity.

Abstract: A method for forming a silicon alloy based barrier layer comprises providing a substrate having a dielectric layer including a trench, placing the substrate in a reactor, and carrying out a process cycle, wherein the process cycle comprises introducing a silicon containing precursor into the reactor, introducing a metal containing precursor into the reactor, and introducing a co-reactant into the reactor, wherein the silicon, metal, and co-reactant react to form a silicon alloy layer that is conformally deposited on a bottom and a sidewall of the trench.

Abstract: Semiconductor device structures and related fabrication methods are provided herein. One fabrication method relates to the formation of conductive contact plugs for a semiconductor device. The method begins by providing a semiconductor device structure having a conductive contact region, a layer of insulating material overlying the conductive contact region, and a via formed in the layer of insulating material and terminating at the conductive contact region. The fabrication process then deposits a first electrically conductive material on the semiconductor device structure such that the first electrically conductive material at least partially fills the via. Then, the process anisotropically etches a portion of the first electrically conductive material located in the filled via, resulting in a lined via. Thereafter, the process deposits a second electrically conductive material on the semiconductor device structure such that the second electrically conductive material at least partially fills the lined via.

Abstract: A metal interconnection including a substrate, a first conductive structure, a second conductive structure, a complex plug and a plug is provided. The substrate includes a first region and a second region. The first conductive structure is disposed on the first region. The second conductive structure is disposed on the second region. The complex plug is disposed on the first conductive structure and includes a tungsten layer and a plurality of insulator columns, wherein an extended direction of each of the insulator columns is perpendicular to a surface of the substrate and the tungsten layer is electrically connected with the first conductive structure. The plug is disposed on the second conductive structure and electrically connected with the second conductive structure.

Abstract: A structure applied to a photolithographic process is provided. The structure includes at least a film layer, an optical isolation layer, an anti-reflection coating and a photoresist layer sequentially formed over a substrate. In the photolithographic process, the optical isolation layer stops light from penetrating down to the film layer. Since the optical isolation layer is set up underneath the photoresist layer, light emitted from a light source during photo-exposure is prevented from reflecting from the substrate surface after passing through the film layer. Thus, the critical dimensions of the photolithographic process are unaffected by any change in the thickness of the film layer.

Abstract: An LED array chip (2), which is one type of a semiconductor light emitting device, includes an array of LEDs (6), a base substrate (4) supporting the array of the LEDs (6), and a phosphor film (48). The array of LEDs (6) is formed by dividing a multilayer epitaxial structure including a light emitting layer into a plurality of portions. The phosphor film (48) covers an upper surface of the array of the LEDs (6) and a part of every side surface of the array of LEDs (6). Here, the part extends from the upper surface to the light emitting layer.

Abstract: A semiconductor device includes a first wiring extending in a first direction and a second wiring extending in a second direction which crosses the first direction and being disposed with a space interposed between the first wiring and the second wiring, and including a tantalum layer, a tantalum nitride layer formed over the tantalum layer, and a metal layer formed over the tantalum nitride layer.

Abstract: There is provided a semiconductor device and method of fabricating the same that employs an insulation film of a borazine-based compound to provided enhanced contact between a material for insulation and that for interconnection, increased mechanical strength, and other improved characteristics. The semiconductor device includes a first insulation layer having a recess with a first conductor layer buried therein, an etching stopper layer formed on the first insulation layer, a second insulation layer formed on the etching stopper layer, a third insulation layer formed on the second insulation layer, and a second conductor layer buried in a recess of the second and third insulation layers. The second and third insulation layers are grown by chemical vapor deposition with a carbon-containing borazine compound used as a source material and the third insulation layer is smaller in carbon content than the second insulation layer.

Abstract: Back-end-of-line (BEOL) wiring structures that include a passive element, such as a thin film resistor or a metal-insulator-metal capacitor, and multiple-height vias in a metallization level, as well as design structures for a radiofrequency integrated circuit. The wiring structures generally include a first metal-filled via in a dielectric layer having sidewalls that intersect the passive element and a second metal-filled via in the dielectric layer with sidewalls that do not intersect the passive element. The bottom of the first via includes a conductive layer that operates as an etch stop to prevent deepening of the sidewalls of the first via into a portion of the passive element when the second via is fully etched through the dielectric layer. A liner is applied to the layer of conductive material and the sidewalls of the first via, and the remaining space is filled with another conductive layer.

Abstract: The methods described herein relate to deposition of low resistivity, highly conformal tungsten nucleation layers. These layers serve as a seed layers for the deposition of a tungsten bulk layer. The methods are particularly useful for tungsten plug fill in which tungsten is deposited in high aspect ratio features. The methods involve depositing a nucleation layer by a combined PNL and CVD process. The substrate is first exposed to one or more cycles of sequential pulses of a reducing agent and a tungsten precursor in a PNL process. The nucleation layer is then completed by simultaneous exposure of the substrate to a reducing agent and tungsten precursor in a chemical vapor deposition process. In certain embodiments, the process is performed without the use of a borane as a reducing agent.

Abstract: A semiconductor device including at least one conductive structure is provided. The conductive structure includes a silicon-containing conductive layer, a refractory metal salicide layer and a protection layer. The refractory metal salicide layer is disposed over the silicon-containing conductive layer. The protection layer is disposed over the refractory metal salicide layer. Another semiconductor device including at least one conductive structure is also provided. The conductive structure includes a silicon-containing conductive layer, a refractory metal alloy salicide layer and a protection layer. The refractory metal alloy salicide layer is disposed over the silicon-containing conductive layer. The refractory metal alloy salicide layer is formed from a reaction of silicon of the silicon-containing conductive layer and a refractory metal alloy layer which includes a first refractory metal and a second refractory metal. The protection layer is disposed over the refractory metal alloy salicide layer.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IID disposed on a top surface of a metal gate disposed on the substrate.

Abstract: The present disclosure provide an integrated circuit. The integrated circuit includes a through-silicon-via (TSV) trench configured in a semiconductor substrate; a conductive pad formed on the semiconductor substrate, the conductive pad being adjacent the TSV trench; a silicon nitride layer disposed over the conductive pad and in the TSV trench; a titanium layer disposed on the silicon nitride layer; a titanium nitride layer disposed on the titanium layer; and a copper layer disposed on the titanium nitride layer.

Abstract: A semiconductor device includes a first interlayer insulating film, and a plurality of first interconnects formed in the first interlayer insulating film. A void is selectively formed between adjacent ones of the plurality of first interconnects in the first interlayer insulating film, and a cap insulating film is formed in a region located over the void and between the interconnects. Respective widths of a lower end and an upper end of the void are substantially the same as a gap between the interconnects located adjacent to the void, and the lower end of the void is located lower than lower ends of the first interconnects located adjacent to the void.

Abstract: Disclosed is a method for forming a capacitor of a semiconductor device. In such a method, a mold insulating layer is formed on an insulating interlayer provided with a storage node plug, and the mold insulating layer is etched to form a hole through which the storage node plug is exposed. Next, a metal storage electrode with an interposed WN layer is formed on a hole surface including the exposed storage node plug and the mold insulating layer is removed. Finally, a dielectric layer and a plate electrode are formed in order on the metal storage electrode.

Abstract: A substrate for device bonding is provided, which enables bonding of a device with high bond strength to an Au electrode formed on a substrate such as aluminum nitride by soldering the device at a low temperature using a soft solder metal having a low melting point such as an Au—Sn-based solder having an Au content of 10% by weight. The substrate for device bonding comprises a substrate having an Au electrode layer formed on its surface and in which (i) a layer composed of a platinum group element, (ii) a layer composed of at least one transition metal element selected from the group consisting of Ti, V, Cr and Co, (iii) a barrier metal layer composed of at least one metal selected from the group consisting of Ag, Cu and Ni and (iv) a solder layer composed of a solder containing Sn or In as a main component are laminated in this order on the Au electrode layer.

Abstract: In a light emitting device using a light emitting element, the invention provides a sealing structure capable of preventing ingress of moisture from the outside and obtaining adequate reliability. The light emitting device has a light emitting element comprising a light emitting layer formed between a first electrode and a second electrode and a pixel portion comprising the light emitting element. The entire surface of the pixel portion is covered with the second electrode. An impermeable insulating film is formed in contact with the first electrode of the light emitting element. The edge of the first electrode and the impermeable insulating film are covered with a partition wall. An opening is formed along the circumference of the pixel portion in the partition wall. The opening passes through the partition wall in the thickness direction, and the side wall and the bottom face thereof are covered with the second electrode.

Abstract: A method of optimally filling a through via within a through wafer via structure with a conductive metal such as, for example, W is provided. The inventive method includes providing a structure including a substrate having at least one aperture at least partially formed through the substrate. The at least one aperture of the structure has an aspect ratio of at least 20:1 or greater. Next, a refractory metal-containing liner such as, for example, Ti/TiN, is formed on bare sidewalls of the substrate within the at least one aperture. A conductive metal seed layer is then formed on the refractory metal-containing liner. In the invention, the conductive metal seed layer formed is enriched with silicon and has a grain size of about 5 nm or less. Next, a conductive metal nucleation layer is formed on the conductive metal seed layer. The conductive metal nucleation layer is also enriched with silicon and has a grain size of about 20 nm or greater.

Abstract: Since VF and IR characteristics of a Schottky barrier diode are in a trade-off relationship, there has heretofore been a problem that an increase in a leak current is unavoidable in order to realize a low VF. Moreover, there has been a known structure which suppresses the leak current in such a manner that a depletion layer is spread by providing P+ regions and a pinch-off effect is utilized. However, in reality, it is difficult to completely pinch off the depletion layer. P+ type regions are provided, and a low VF Schottky metal layer is allowed to come into contact with the P+ type regions and depletion regions therearound. A low IR Schottky metal layer is allowed to come into contact with a surface of a N type substrate between the depletion regions. When a forward bias is applied, a current flows through the metal layer of low VF characteristic. When a reverse bias is applied, a current path narrowed by the depletion regions is formed only in the metal layer portion of low IR characteristic.

Abstract: A TFT includes a gate electrode, an active layer, a source electrode, a drain electrode, and a buffer layer. The gate electrode is formed on the substrate; the active layer is formed on the gate electrode. The source and drain electrodes, formed on the active layer, are separated by a predetermined distance. The buffer layer is formed between the active layer and the source and drain electrodes. The buffer layer has a substantially continuously varying content ratio corresponding to a buffer layer thickness. The buffer layer is formed to suppress oxidation of the active layer, and reduce contact resistance.

Abstract: A semiconductor device is provided. An amorphous silicon layer that acts as a UV blocking layer replaces a conventional silicon-rich oxide (SRO) layer or the super silicon-rich oxide (SSRO) layer. By doing this, the process window is increased. In addition, silicon nitride sidewall spacer is formed inside the contact hole to prevent charge loss.

Abstract: A fusible link between metallization layers of a semiconductor device comprises a tungsten plug deposited in a via interconnecting two aluminum metallization layers.

Abstract: A power semiconductor package that includes a power semiconductor device having a threshold voltage that does not vary when subjected to an autoclave test.

Abstract: A semiconductor device has a porous low-dielectric-constant film formed on a substrate and having an opening and a fine particle film composed of a plurality of aggregately deposited fine particles each having a diameter of not less than 1 nm and not more than 2 nm and formed on a surface of the portion of the porous low-dielectric-constant film which is formed with the opening. The fine particles are filled in voids exposed at the surface of the portion of the porous low-dielectric-constant film which is formed with the opening.

Abstract: A semiconductor device, comprises: a wiring formed on a first insulating film, a second insulating film formed on the first insulating film and on the wiring, a contact hole formed in the second insulating film and located on the wiring, a coating that covers a sidewall of the contact hole and is formed by sputtering the wiring at the bottom of the contact hole, a barrier film formed on the coating and at the bottom of the contact hole, and an electrical conductor deposited in the contact hole.

Abstract: A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.

Abstract: Tungsten nitride films were deposited on heated substrates by the reaction of vapors of tungsten bis(alkylimide)bis(dialkylamide) and a Lewis base or a hydrogen plasma. For example, vapors of tungsten bis(tert-butylimide)bis(dimethylamide) and ammonia gas supplied in alternate doses to surfaces heated to 300° C. produced coatings of tungsten nitride having very uniform thickness and excellent step coverage in holes with aspect ratios up to at least 40:1. The films are metallic and good electrical conductors. Suitable applications in microelectronics include barriers to the diffusion of copper and electrodes for capacitors. Similar processes deposit molybdenum nitride, which is suitable for layers alternating with silicon in X-ray mirrors.

Abstract: A semiconductor device formed by the steps of forming a contact hole in an insulation film so as to extend therethrough and so as to expose a conductor body at a bottom part of the contact hole, forming a barrier metal film of tungsten nitride on the bottom part and a sidewall surface of the contact hole with a conformal shape to the bottom part and the sidewall surface of the contact hole, forming a tungsten layer so as to fill the contact hole via the barrier metal film, and forming a tungsten plug in the contact hole by the tungsten layer by polishing away a part of the tungsten film on the insulation film until a surface of the insulation film is exposed, wherein there is conducted a step of cleaning a surface of the conductor body prior to the forming step of the barrier metal film.

Abstract: A light-emitting device, which has a structure that improves an opening ratio and light extraction efficiency, can solve a problem of an etching residue occurred during forming the device itself, and reduce deterioration due to poor coverage and short-circuiting to improve greatly the reliability, and a method for manufacturing the light-emitting device. In the light-emitting device having a structure that improves light extraction efficiency, a material used for forming a first electrode is Ti/TiN/Al (or Al—Ti)/Ti (or TiN).

Abstract: Provided are a semiconductor chip, a method of fabricating a semiconductor chip, and a semiconductor chip stack package. The semiconductor chip includes a semiconductor substrate and a semiconductor device on the semiconductor substrate. A dielectric covers the semiconductor device. A top metal is on the dielectric and electrically connected to the semiconductor device. A deep via penetrates the semiconductor substrate and the dielectric. An interconnection connects the deep via and the top metal electrically. A bump is in contact with the top metal and the interconnection.

Abstract: The present disclosure provide an integrated circuit. The integrated circuit includes a through-silicon-via (TSV) trench configured in a semiconductor substrate; a conductive pad formed on the semiconductor substrate, the conductive pad being adjacent the TSV trench; a silicon nitride layer disposed over the conductive pad and in the TSV trench; a titanium layer disposed on the silicon nitride layer; a titanium nitride layer disposed on the titanium layer; and a copper layer disposed on the titanium nitride layer.

Abstract: Methods of forming dual-damascene metal wiring patterns include forming a first metal wiring pattern (e.g., copper wiring pattern) on an integrated circuit substrate and forming an etch-stop layer on the first metal wiring pattern. These steps are followed by the steps of forming an electrically insulating layer on the etch-stop layer and forming an inter-metal dielectric layer on the electrically insulating layer. The inter-metal dielectric layer and the electrically insulating layer are selectively etched in sequence to define an opening therein that exposes a first portion of the etch-stop layer. This opening may include a trench and a via hole extending downward from a bottom of the trench. A first barrier metal layer is formed on a sidewall of the opening and directly on the first portion of the etch-stop layer. A portion of the first barrier metal layer is selectively removed from the first portion of the etch-stop layer.

Abstract: A process is described that forms a low resistivity connection between a tungsten layer and a silicon surface with high adherence of the tungsten to the silicon. The silicon surface is plasma-cleaned to remove native oxide. A very thin layer (one or more monolayers) of Si-NH2 is formed on the silicon surface, serving as an adhesion layer. A WNx layer is formed over the Si-NH2 layer, using an atomic layer deposition (ALD) process, to serve as a barrier layer. A thick tungsten layer is formed over the WNx layer by CVD. An additional metal layer (e.g., aluminum) may be formed over the tungsten layer.

Abstract: A thin-film transistor substrate in which an aluminum alloy film composing a source/drain wiring is directly connected with a transparent electrode. The thin-film transistor substrate includes a gate wiring, and source wiring and drain wiring, the gate wiring and the source and drain wiring being arranged orthogonally to each other. The single-layer aluminum alloy film composing the gate wiring and the single-layer aluminum alloy film composing the source wiring and the drain wiring are the same in composition. Furthermore, display devices can be mounted with the above thin-film transistor substrates.

Abstract: Embodiments relate to a semiconductor device. In embodiments, the semiconductor device may include a semiconductor substrate having a first metal line; a pre-metal dielectric (PMD) layer over the first metal line on the semiconductor substrate; a first metal layer formed in a first contact hole in the PMD layer; a second metal layer formed in a second contact hole in the PMD layer; and a second metal line electrically connected to the first and second metal layers, respectively, over the PMD layer, wherein the first and second metal layers are located at prescribed positions and configured to be electrically connected to the first metal line.