Abstract: A capacitor, electrode, or wiring structure having an alpha ray emitting source (in particular, a Pt electrode), and an alpha ray shielding layer 18, having at least one type selected from the group of simple metals of nickel, cobalt, copper, and tungsten, their compounds or alloys made of at least two types of these simple metals, and compounds and alloys made of these simple metals and silicon is provided. It is possible to shield off the alpha ray effectively, to suppress generation of soft errors, to enable the use of Pt and other new materials in making the electrodes and wiring, and to reduce the cost of the mold resin.

Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.

Abstract: A solderable lead frame is disclosed which includes a copper base lead frame containing a one layer or plated tin or tin alloy and another layer of plated palladium. The tin plating covers only external portions of the leads, whereas the palladium covers the external regions including the tin plating, and extends into internal portions of the lead frame. A diffusion barrier, of cobalt or nickel, is provided on the base lead frame beneath the tin plating.

Abstract: On a rear surface of a semiconductor (10), a contact layer (11), a diffusion preventing layer (12) and a solder joint layer (13) are formed, and this solder joint layer (13) is connected to a mount base (15) by a Pb-Sn solder layer (14). The contact layer (11) is formed of a rare earth metal, its silicide or a composite thereof, the diffusion preventing layer (12) is formed of a ferrous metal, and the solder joint layer (13) is formed of a Ni-Au alloy. By forming the diffusion preventing layer (12) using the ferrous metal, a diffusion of tin in a solder is prevented and by the solder joint layer (13) of the Ni-Au alloy, an excellent solder joint property can be maintained to reduce the number of laminated layers. Further, as a surface treated layer of at least one joint member, the Ni-Au alloy is used and by heating the semiconductor substrate via a solder foil in a reducing atmosphere a high airtightness is obtained.

Abstract: A metallization layer is formed on a substrate with improved adhesion thereto by performing the deposition at an elevated temperature which favors the formation of chemical bonds of the metal to the substrate as well as clusters of metal embedded within the substrate and contiguous with the metallization layer. In polymer substrates the chemical bond is made to carbonyl functional groups such as ketones or aldehydes. The adhesion is enhanced by the removal of moisture from the surface of the substrate at the elevated temperatures employed. A high degree of adhesion is also obtained through the deposition of a mixture of metals including chromium and copper which initially has a high chromium to copper ratio which is decreased during the deposition process. Completion of the process is determined by the reaching of a final desired chromium to copper ratio as observed by optical emission spectroscopy. The process can be carried out on a continuous basis by the use of a multi-chamber vacuum sputtering system.

Abstract: A structure for an improved solder terminal is disclosed. The improved solder terminal is made of a bottom metallic adhesion layer, a CrCu intermediate layer on top of the adhesion layer, a solder bonding layer above the CrCu layer and a solder top layer. The adhesion layer is either TiW or TiN. A process for fabricating an improved terminal metal consists of depositing an adhesive metallic layer, a layer of CrCu over the adhesive layer and a layer of solder bonding material, over which a solder layer is formed in selective regions and the underlying layers are etched using solder regions as a mask.

Abstract: An aluminum-nickel-chromium (Al-Ni-Cr) layer used as an interconnect within a semiconductor device is disclosed. The Al-Ni-Cr layer has about 0.1-0.5 weight percent nickel and about 0.02-0.1 weight percent chromium. Usually, the nickel or chromium concentrations are no greater than 0.5 weight percent. The layer is resistant to electromigration and corrosion. The low nickel and chromium concentrations allow the layer to be deposited and patterned similar to most aluminum-based layers.

Abstract: In a conventional overmolded leadframe package, having a multiplicity of leadframe fingers and encasing one or more electronic devices, a window is formed. The window exposes at least three selected ones of the leadframe fingers at localized sites. At these (exposed) sites of these selected ones of the leadframe fingers, these fingers are coated with a contact material such as gold, whereby localized contact sites are formed. Electrical conductors emanating from one or more external devices--such as electronic devices, electro-optic devices, or opto-electronic devices--can then be bonded to these localized contact sites. The remaining (non-selected) leadframe fingers are typically bonded to a wiring board.

Abstract: An multiple lead semiconductor integrated circuit package incorporating a silicon die wire bonded to a lead frame plated by high purity copper. The die and the lead frame are encapsulated in an epoxy compound with lead fingers from the lead frame extending outside of the encapsulated compound. The high copper plating on the lead frame, which lead frame is not composed of high purity copper, increases the conductivity thereof so as to improve the signal speed for the lead frame. A thinner copper plating on the lead frame can be used without a decrease in signal speed as frequency of the signal is increased.

Abstract: A semiconductor device, including a nickel layer formed on a semiconductor substrate and a solder layer formed on the nickel layer, and a method of manufacturing such a device are disclosed. The percent ratio of an X-ray diffraction peak intensity of the (200) plane of the nickel layer to that of the (111) plane of the nickel layer is not less than 10%. The nickel layer is sputtered in a condition which a pressure of an argon discharge gas is at least 15 mTorr. The solder layer includes at least tin and lead, and the amount of tin is not more than 30% by weight. The adhesive strength of the resultant semiconductor device is strong.

Abstract: A semiconductor device has a contact structure between two conductive layers capable of effectively preventing growth of an oxide film and diffusion of impurities between an impurity diffused region in a first one of the conductive layers and a polycrystalline silicon film (the second conductive layer) formed to be in contact with the impurity diffused region. The contact structure between the two conductive layers includes an n-type impurity diffused region 3 formed on a silicon substrate 1, an nitrided oxide film 4 formed to be in contact with the n-type impurity diffused region 3, and a polycrystalline silicon film 5a formed on the nitrided oxide film 4 and doped with impurities. Accordingly, growth of an oxide film and diffusion of impurities between the n-type impurity diffused region 3 and the polycrystalline silicon film 5a are also effectively prevented in a case where heat treatment at a high temperature is subsequently carried out in an oxygen atmosphere.

Abstract: A II-VI group compound semiconductor device having a p-type Zn.sub.x Mg.sub.1-x S.sub.y Se.sub.1-y (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1) semiconductor layer, on which an electrode layer is formed with at least metallic nitride layer lying between the semiconductor layer and the electrode layer.

Abstract: An outer lead having a plurality of external leads 1 for electrically connecting the semiconductor IC of a semiconductor IC package to external devices comprises a base plate 11, a plated base structure formed over the surface of the base plate 11 and consisting of a plurality of plated base layers 12, 13 and 14 of Ni or a Ni alloy, and a surface layer 15 of Au or an Au alloy formed over the uppermost plated base layer 14 of the plated base structure. The number of the plated base layers is at least three. Each plated base layer 12, 13 and 14 of the plated base structure is subjected to crystal-growth annealing after being formed by plating to crystal-grow the grains thereof. A method of fabricating such an outer lead is provided.

Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.

Abstract: There is disclosed a leadframe for electrically interconnecting a semiconductor device to external circuitry. The leadframe has an electrically conductive substrate that is coated with an oxidation resistant external layer. An intervening layer is disposed between a portion of the substrate and the external layer. The intervening layer is absent from the outer lead ends of the leadframe. Subsequent removal of the external layer from the outer lead ends enables a solder to directly contact the leadframe substrate.

Abstract: A flange interface for wrap-around contact regions formed in fabricating semiconductor devices provides for a durable and reliable electrical bond. A first layer having a first material is formed over the first side of a wafer. A trench is formed from the second side of the wafer such that a portion of the first layer becomes exposed in the trench. A second layer having a second material is formed over the second side of the wafer such that a portion of the second layer contacts the portion of the first layer exposed in the trench. The wafer is separated through the trench. The trench may be formed by sawing the second side of the wafer in an area where the trench is to be formed. The wafer may then be etched such that the trench is formed.

Abstract: The present invention relates generally to a new structure and method for capped copper electrical interconnects. More particularly, the invention encompasses a novel structure in which one or more of the copper electrical interconnects within a semiconductor substrate are capped to obtain a robust electrical interconnect structure. A method for obtaining such capped copper electrical interconnect structure is also disclosed. These capped interconnects can be a single layer or multi-layer structures. Similarly, the interconnect structure that is being capped can itself be composed of single or multi-layered material.

Abstract: There is disclosed a process for the assembly of an electronic package in which the outer lead ends of a leadframe are solderable to external circuitry without the necessity of a tin or solder coat. An oxidation resistant layer is deposited on the leadframe prior to package assembly. The oxidation resistant layer is removed prior to outer lead soldering providing a clean, oxide free metallic surface for soldering.

Abstract: A feature in a thin-film structure such as an AMLCD array has an edge with a tapered sidewall profile, reducing step coverage problems. The feature can be produced by producing a layer in which local etch rates vary in the thickness direction of the layer. The layer can then be etched to produce the feature with the tapered sidewall profile. The layer can be produced by physical vapor deposition. The layer can, for example, includes sublayers with different etch rates, either due to different atomic proportions of constituents or due to different etchants. Or local etch rates can vary continuously as a result of changing deposition conditions. Differences in etch rates or differences in etchant mixtures can be used to obtain a desired angle of elevation.

Abstract: An ohmic electrode for a p-type III-V compound semiconductor is disclosed. The ohmic electrode formed on a p-type III-V compound semiconductor layer includes nickel (Ni), titanium (Ti), and platinum (Pt) as main components in an interface between the ohmic electrode and the p-type III-V compound semiconductor layer.

Abstract: A semiconductor device includes a semiconductor chip, a die-pad on which the semiconductor chip is mounted, a package encapsulating the die pad and the semiconductor chip, and a plurality of leads electrically connected to the semiconductor chip and projecting from the package, wherein each of the leads has a lead body made of pure nickel (Ni) having a purity equal to or greater than 99% and a first film formed thereon, the first film being made of palladium (Pd).

Abstract: In a ceramic base and metallic member assembly, a metallic member such as an input/output terminal is joined by solder to a ceramic base substrate by way of a stress relief layer. The ceramic base substrate has a metallized layer on which the stress relief layer is formed by plating. The stress relief layer is made of soft metal such as copper and has the thickness equal to or larger than 25 .mu.m. In one embodiment, a barrier made of glass or an organic insulating material for preventing outflow of solder is formed on a peripheral portion of a joining surface of the stress relief layer.

Abstract: An N-InP buffer layer is deposited on an N.sup.+ -InP substrate, an InGaAs light-absorbing layer is deposited on the buffer layer, an N.sup.- -InP cap layer is deposited on the light-absorbing layer, and a P-type impurity region is formed in the light-absorbing layer and the cap layer. Next, a masking film is formed on the cap layer, and with this masking film serving as a mask, the cap layer, the light-absorbing layer, the buffer layer are etched, thus forming a P-type electrode forming region and an N-type electrode forming region. Next, an insulating film is provided for the periphery portion of the P-type impurity region of the cap layer. Electrode pads having a laminated structure is formed respectively on the P-type and N-type electrode forming regions, and a non-metal member is formed on the insulating film and on the surface, the periphery and the side surface of the electrode pad of the P-type electrode.

Abstract: A method of forming an insulated gate semiconductor device (10). A field effect transistor and a bipolar transistor are formed in a portion of a monocrystalline semiconductor substrate (11) that is bounded by a first major surface (12). A control electrode (19) is isolated from the first major surface by a dielectric layer (18). A first current conducting electrode (23) contacts a portion of the first major surface (12). A second current conducting electrode (24) contacts another portion of the monocrystalline semiconductor substrate (11) and is capable of injecting minority carriers into the monocrystalline semiconductor substrate (11). In one embodiment, the second current conducting electrode contacts a second major surface (13) of the monocrystalline semiconductor substrate (11).

Abstract: Lead frames completely surface-plated with palladium have a nickel-phosphorus or copper-tin layer between the base element, made for example of copper, and the palladium layer. Such lead frames exhibit good bondability and good solderability without tinning.

Abstract: A semiconductor device including a conductive pad and a semiconductor chip soldered to the conductive pad, the semiconductor chip including a substrate having opposite front and rear surfaces, a first electrode disposed on the front surface, a dome-shaped via-hole having an opening at the rear surface of the substrate and a bottom in contact with the first electrode, and a second electrode covering the rear surface of the substrate and the internal surface of the via-hole. The semiconductor chip is soldered to the conductive pad so that a space is formed between the internal surface of the via-hole and the solder. The space has a distance d from the bottom of the via-hole in a direction perpendicular to the front surface of the substrate represented by ##EQU1## where x is the via-hole depth, y is rupture stress of the semi-conductor substrate, E.sub.1 is Young's modulus of a semi-conductor substrate, E.sub.2 is Young's modulus of the solder, .alpha..sub.

Abstract: A lower electrode, a first inorganic insulating film of SiN, and an organic insulating film of polyimide are formed on a GaAs substrate serving as an underlie, in this order. The organic insulating film is selectively etched to form a capacitor opening. A second norganic insulating film covering the surface of the organic insulating film and the bottom and side wall of the capacitor opening, and an upper electrode are formed. As the selective etching of the organic insulating film, wet etching may be used for simplifying manufacturing processes. Alternatively, dry etching may be used for improving etching accuracy. The organic insulating film 4 may be formed by a multi-layer film so that a circuit can be formed across multi-layers, improving the degree of integration.

Abstract: A metallization composite comprises a refractory metal, nickel, and copper. The refractory metal is preferably titanium (Ti), but other suitable refractory metals such as zirconium and hafnium can also be utilized. An additional optional layer of gold can overlie the copper. The metallization composite is used to connect a solder contact to a semiconductor substrate.

Abstract: A plastic leaded semiconductor package (20) has a semiconductor device (614) encapsulated in the package and mounted to a lead frame (612). The lead frame has a plurality of leads (622) that extend beyond the body (610) of the encapsulated package. Each of the plurality of leads is made from a metal having a predetermined coefficient of thermal expansion. A second metal (627) with a different coefficient of thermal expansion is disposed on at least one portion of each of the leads.

Abstract: A method for electrically connecting integrated circuit copper-gold ball bond that connect a bond wire (18) with a bond pad (14) forms a palladium layer (16) in the electrical connection between the bond wire (18) and the bond pad (14). The connection avoids excessive stresses that arise from intermetallic formations between the bond wire (18) and the bond pad (14).

Abstract: The invention provides a multilayer laminar interconnect package comprising a plurality of conductor circuit layers adhering to and sandwiched between a plurality of dielectric polyimide polymer layers where the conductor circuit layers are a circuit pattern of lines of conductive metal. The conductive metal, e.g. copper, is coated with a capping layer of a metal, e.g. cobalt, which capping layer is further characterized as having a thin layer of the capping metal oxide adhered to the surface thereof. The conductive layer is in contact with an overcoated polyimide dielectric layer such that the surface oxidized capping layer forms an adherent barrier layer at the interface of the polyimide and conductive line layers. The invention also provides a process for producing such interconnect packages.

Abstract: A multilayer composite interconnection for use in circuits including thin film elements and electrical interconnections includes a copper barrier layer interposed between a nickel layer and a gold layer of the interconnection. The copper layer is in a thickness sufficient to bar or at least to restrict diffusion of nickel through the gold layer under processing and operating conditions. The interconnection multilayer composite interconnection includes in an ascending order, titanium, palladium or palladium-titanium alloy, copper, nickel, copper barrier and gold layers.

Abstract: There is provided a lead frame with enhanced adhesion to a polymer resin. The lead frame is coated with a thin layer of containing chromium, zinc or a mixture of chromium and zinc. A mixture of chromium and zinc with the zinc-to-chromium ratio in excess of about 4:1 is most preferred. The coated lead frames exhibit improved adhesion to a polymeric resin.

Abstract: This invention relates generally to structure and method for corrosion- and stress-resistant interconnecting metallurgy, and more specifically to new structures and methods for corrosion- and stress-resistant interconnecting multilayer metallurgical pad comprising sequentially deposited layers of chromium, nickel and noble or relatively noble metal as the interconnecting metallurgy, or multilayer metallurgical pad comprising sequentially deposited layers of chromium, soluble noble metal, nickel and noble or relatively noble metal as the interconnecting metallurgy. This invention also relates to an improved multilayer metallurgical pad or metallurgical structure for mating at least a portion of a pin or a connector or a wire to a substrate.

Abstract: The line material is of a laminated structure consisting of: a Ta containing N alloy layer (lower layer) which is a first metal layer made of at least an alloy selected from the group consisting of a TaN alloy, a Ta--Mo--N alloy, a Ta--Nb--N alloy and a Ta--W--N alloy; a second metal layer (upper layer) formed integrally with the first metal layer and made of at least an alloy selected from the group consisting of Ta, a Ta--Mo alloy, a Ta--Nb alloy, a Ta--W alloy, a TaN alloy, a Ta--Mo--N alloy, a Ta--Nb--N alloy and a Ta--W--N alloy; and/or a pin hole-free oxide film. The line material of the laminated structure is to be applied to the formation of signal lines and electrodes of, e.g., a liquid crystal display. The line material has a low resistance and the insulating film formed by anodization and the like exhibits excellent insulation and thermal stability. Therefore, when the line material is applied to signal lines of various devices, it exhibits excellent characteristics.

Abstract: An n.sup.- -type InP buffer layer is formed on an n-type InP substrate. An n.sup.- -type InGaAs light absorbing layer is formed on the n.sup.- -type InP buffer layer. An n.sup.- -type InP cap layer is formed on the n.sup.- -type InGaAs light absorbing layer. A p-type InP region is formed in the InP cap layer. A layered electrode having a contact with the p-type InP region comprises a first layer made of an Au layer, a second layer made of a Ti layer or the like, a third layer made of a Pt layer or the like, and a fourth layer made of an Au layer. The first layer made of Au has a thickness of 1 to 500 nm. This structure improves an ohmic ability and a peel strength at a contact portion where an electrode is connected, and simplifies manufacturing steps.

Abstract: A light-emitting diode of GaN compound semiconductor emits a blue light from a plane rather than dots for improved luminous intensity. This diode includes a first electrode associated with a high-carrier density n.sup.+ layer and a second electrode associated with a high-impurity density i.sub.H -layer. These electrodes are made up of a first Ni layer (110 .ANG. thick), a second Ni layer (1000 .ANG. thick), an Al layer (1500 .ANG. thick), a Ti layer (1000 .ANG. thick), and a third Ni layer (2500 .ANG. thick). The Ni layers of dual structure permit a buffer layer to be formed between them. This buffer layer prevents the Ni layer from peeling. The direct contact of the Ni layer with GaN lowers a drive voltage for light emission and increases luminous intensity.

Abstract: Desirably, a Schottky barrier semiconductor diode has low forward direction rising voltage and high inverse direction yield voltage. A semiconductor device is provided with a first metal producing a low Schottky barrier and a second metal producing a high Schottky barrier. The forward direction rising voltage is reduced on account of the first metal. The inverse direction yield voltage, which is decreased due to the lowered forward rising voltage, is compensated for upon linking of depletion regions generated by forming the PN junction under the first metal layer and not under the second metal layer. As a result, a high inverse yield voltage is realized.

Abstract: A light-emitting device comprises an n-type layer made of an n-type gallium nitride-based compound of the formula Al.sub.x Ga.sub.1-x N, wherein 0.ltoreq.X<1, and an i-type layer formed on the n-type layer and made of a semi-insulating i-type gallium nitride-based compound semiconductor and doped with a p-type impurity for junction with the n-type layer. A first electrode is formed on the surface of the i-type layer and made of a transparent conductive film and a second electrode is formed to connect to the n-type layer through the i-type layer. The device is so arranged that light is emitted from the side of the i-type layer to the outside. When an electric current is supplied to the first electrode from a wire contacted thereto, the first electrode is held entirely at a uniform potential. Light is emitted from the entire interface beneath the first electrode and can thus be picked up from the first electrode which is optically transparent.

Abstract: A packaged device with a lead frame, a lead frame and an article of manufacture comprising a base metal, a layer of nickel on the base metal, and a protective composite of metal layers on the nickel. The composite includes, in succession from the nickel layer, a layer of palladium or soft gold strike, a layer of palladium-nickel alloy, a layer of palladium and a layer of gold. The palladium or soft gold strike layer acts primarily as a bonding (an adhesive) layer between the Ni and Pd-Ni alloy layers and as a layer that enhances reduction in porosity of subsequent layers, Pd-Ni alloy layer acts as a trap for base metal ions, Pd layer acts as a trap for Ni ions from the Pd-Ni alloy layer, and the outer gold layer synergistically enhances the quality to the Pd layer. The various layers are in thickness sufficient to effectively accomplish each of their designated roles, depending on the processing and use conditions.

Abstract: There is provided a lead frame with enhanced adhesion to a polymer resin. The lead frame is coated with a thin layer of containing a mixture of chromium and zinc. A mixture of chromium and zinc with the zinc-to-chromium ratio in excess of about 4:1 is most preferred. The coated lead frames exhibit improved adhesion to a polymeric resin.

Abstract: An IC package and LSI package having a lead frame of a copper alloy that contains 0.1 to 1% by weight of chromium, 0.01 to 0.5% by weight of zirconium and that has partial discolored regions caused by unbalanced precipitation of the zirconium distributed thereon at a rate of 2 grains/100 cm.sup.2 or less is disclosed. The lead frame is, for example, obtained from an alloy that contains 0,005% by weight of sulfur or less. The lead frame has high reliability, can be produced in high yield and has high electrical conductivity.

Abstract: A ferroelectric thin film element constructed by forming a first electrode composed of an alloy thin film of a Ni-Cr-Al system or Ni-Al system on a substrate and forming a ferroelectric thin film composed of a ferroelectric material having a composition having a spontaneous axis in the direction (111) and having a crystal orientation in the direction (111) on the first electrode composed of a thin film.

Abstract: This invention describes a low resistance contact structure to n-type GaAs and a method for making such a contact structure. The contact structure is formed by depositing successive layers of Ni, Au, Ge, and Ni. A fifth layer is then deposited on the first four layers. The fifth layer is a metallic tungsten oxide. The metallic tungsten oxide is formed by sputtering tungsten onto the 4 layer stack in a low pressure argon plus oxygen atmosphere. The resulting 5 layer stack is then annealed in a rapid thermal anneal (RTA) process. The RTA process heats the stack for 5 seconds at 600 degrees. The resulting structure consists of an intermetallic NiGe compound having a small amount of a AuGa compound dispersed within it and being covered by a metallic tungsten oxide film. The oxygen from the metallic tungsten oxide film acts as a gettering mechanism to create gallium vacancies in the GaAs lattice structure during the RTA process.

Abstract: Annealed copper foil (12) is coated with chromium film (16), followed by coating with an appropriate thickness of gold film (14) and is thermocompression bonded to an aluminum metallized substrate (18) on a silicon chip (30) to provide solderable, high current contacts to the chip. The foil is formed into appropriate electrical network-contact patterns (40) and is bonded to the silicon chip only where aluminum metallization exists on the chip. Leaf (wing) portions (46) of the foil extend beyond the boundaries of the silicon chip for subsequent retroflexing over the foil to provide electrical contact at predesignated locations (49). External contacts to the foil are made by penetrating through a ceramic lid positioned directly above the foil area. Thus, direct thermocompression bonding of a principally copper foil to aluminum semiconductor pads can replace current gold detent/bump connections by securing a copper conductor to a silicon chip through an intermetallic AuAl.sub.2 link and an aluminum stratum.

Abstract: There is disclosed a semiconductor device having an electrode for wire bonding, comprising a first aluminum layer, a nickel-aluminum alloy layer, and a second aluminum layer. The electrode is suitable for bonding with copper wire, since the electrode withstands a wide range of bonding conditions--mechanical pressure, ultrasonic wave power and such, and permits a reliable electrical connection to be maintained.

Abstract: In an ohmic contact electrode for the p-type semiconductor diamond, the electrode is formed of metals or metallic compounds containing boron on a p-type semiconductor diamond, so as to obtain a decreased contact resistance.

Abstract: Minimum line spacing is reduced and line spacing uniformity is increased in thin film transistors by employing source/drain metallization having a first relatively thin layer of a first conductor and a second relatively thick layer of a second conductor. The second conductor is selected to be one which may be preferentially etched in the presence of the first conductor whereby the first conductor acts as an etch stop for the etchant used to pattern the second conductor portion of the source/drain metallization. This etching is preferably done using dry etching. Dry etching typically provides substantially better control of line width than wet etching. The etching of the second conductor can be done with a dry etch process which etches the photoresist at substantially the same rate as the second conductor whereby the second conductor is provided with a sidewall slope of substantially 45.degree. which improves the quality of passivation provided by subsequent deposition of a conformal passivating layer.

Abstract: A bonded structure is described consisting of a semiconductor wafer, preferably gallium arsenide, soldered to a substrate material. A method for forming the structure is also described. The structure provides mechanical support and thermal conductivity for the wafer, as well as a multitude of connections through the substrate material at predetermined locations on the wafer. The substrate material and the soldering process are selected to minimize the resulting stresses in the wafer. A pattern of pads consisting of a refractory metal covered by a solder material is formed on the substrate to maintain space for excess solder in order to avoid the shorting of the individual connections on the wafer, and to control the size and location of voids in the solder upon solidification.

Abstract: On the surface of n-type layer of Ga.sub.1-x Al.sub.x As (0.ltoreq.x.ltoreq.1) having n-type layer, Au layer is formed as a first layer, and alloying treatment is performed after Ge layer, Ni layer and Au layer are sequentially formed. The first Au layer, the second Ge layer, the third Ni layer and the fourth Au layer have the following thickness:______________________________________ 1st layer Au 10-100 .ANG. 2nd layer Ge 50-200 .ANG. 3rd layer Ni 50-200 .ANG. 4th layer Au 200-1000 .ANG. ______________________________________Thus, it is possible to form an ohmic electrode, which has low contact resistance and does not develop ball-up phenomenon.