Abstract: A light-emitting device and method for fabricating the same are revealed. The light-emitting device includes an epitaxial structure, a P-type ohmic contact electrode and an N-type ohmic contact electrode. The epitaxial structure includes a plurality of epitaxial layers capable of emitting light and P-type contact layer. The P-type ohmic contact electrode includes a first nickel layer deposited on the epitaxial structure, a first platinum layer deposited on the first nickel layer, and a first gold layer deposited on the first platinum layer. According to the fabricating method of the light-emitting device, an epitaxial structure is first formed on the surface of a substrate, a P-type ohmic contact electrode is then formed on the epitaxial structure, and an N-type ohmic contact electrode is formed on the other surface of the substrate. Finally, an annealing process is performed at a temperature between 220° C. and 330° C.

Abstract: A method for forming a nickel cap layer over copper metalized bond pad is disclosed in which the phosphorous content of the nickel cap, and particularly the surface of the nickel cap, may be controlled. The phosphorous content of the surface of the nickel cap is suitably determined such that oxidation is inhibited. The resulting nickel cap may be wire-bonded directly, without the deposition of a gold cap layer.

Abstract: A method and apparatus for plating facilitates the plating of a small contact feature of a wafer die while providing a relatively stable plating bath. The method utilizes a supplemental plating structure that is larger than a die contact that is to be plated. The supplemental plating structure may be located on the wafer, and is conductively connected to the die contact. Conductive connection between the die contact and the supplemental plating structure facilitates the plating of the die contact. The supplemental plating structure also can be used to probe test the die prior to singulation.

Abstract: A semiconductor device of the present invention comprises a semiconductor chip, metal layers formed on a first main surface of the semiconductor chip, a first conductive layer layered on a second main surface of the semiconductor chip, consisting of a plurality of conductive films, a second conductive layer layered on the metal layer, having a layered structure consisting of a plurality of conductive films formed in the same order as in the first conductive layer as viewed from the semiconductor chip and a third conductive layer layered on the metal layer, having a layered structure consisting of a plurality of conductive films formed in the same order as in the first conductive layer as viewed from the semiconductor chip. The plurality of conductive films comprise a nickel film and a low contact resistance conductive film having contact resistance with the semiconductor chip which is lower than that of the nickel film.

Abstract: A semiconductor device includes an active element structure that is formed on a semiconductor substrate and has a connection region formed in the surface of the semiconductor substrate. A contact hole extends from a surface of a first insulating film formed on the semiconductor substrate to the connection region. A contact plug is provided in the contact hole. A clearance formed in the contact plug is formed with a buried conductive film consisting of a material different from the contact plug. The buried conductive film has a continuous surface without forming a step with the surface of the contact plug.

Abstract: It is an object of the present invention to achieve a semiconductor device capable of preventing circuit malfunctions caused by noise without decreasing an integration degree of the circuit by making a space between signal interconnections wider and inserting a shield or a shield layer between the signal interconnections. The semiconductor device has a multilayer interconnection structure wherein three or more interconnection layers are stacked on a silicon semiconductor substrate, and comprises: a first signal line which is formed with a (N?1)-th interconnection layer and comprises a latch circuit; a second signal line which is formed with a (N+1)-th interconnection layer and is arranged so as to cross the first signal line or partially overlap thereover; and a power supply interconnection serving as a shield interconnection which is formed with an N-th interconnection layer in a portion directly beneath the first signal line and the second signal line.

Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.

Abstract: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.

Abstract: A method of creating a multi-layered barrier for use in an interconnect, a barrier for an interconnect, and an interconnect including the barrier are disclosed. The method includes creating the multi-layered barrier in a recess of the device terminal by use of a single electroplating chemistry to enhance protection against voiding and de-lamination due to the diffusion of copper, whether by self-diffusion or electro-migration. The barrier includes at least a first layer of nickel-rich material and a second layer of copper-rich material. The barrier enables use of higher current densities for advanced complementary metal-oxide semiconductors (CMOS) designs, and extends the reliability of current CMOS designs regardless of solder selection. Moreover, this technology is easily adapted to current methods of fabricating electroplated interconnects such as C4s.

Abstract: A high performance, highly reflective ohmic contact, in the visible spectrum (400 nm–750 nm), has the following multi-layer metal profile. A uniform and thin ohmic contact material is deposited and optionally alloyed to the semiconductor surface. A thick reflector layer selected from a group that includes Al, Cu, Au, Rh, Pd, Ag and any multi-layer combinations is deposited over the ohmic contact material.

Abstract: A flip chip package, apparatus and technique in which a ball grid array composed of a doped eutectic Pb/Sn solder composition is used. The dopant in the Pb/Sn solder forms a compound or complex with the phosphorous residue from the electroless nickel plating process that is mixable with the Pb/Sn solder. The phosphorous containing compound or complex prevents degradation of the solder/under bump metallization bond associated with phosphorus residue. The interfacial solder/under bump metallization bond is thereby strengthened. This results in fewer fractured solder bonds and greater package reliability.

Abstract: In a wiring structure of a semiconductor device, dielectric tolerance of the wiring is improved by preventing diffusion of the wiring material. The wiring structure of the semiconductor device includes a first insulating film having plural grooves, plural wiring films formed protrusively above tops of the first insulating film among the grooves, plural barrier films formed on bottoms of the wiring films and up to a higher position than the tops on sides of the wiring films, first cap films including metal films formed on tops of the wiring films, and a second cap film formed on at least respective sides of the first cap films and the barrier films.

Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.

Abstract: The present invention discloses a laminated chip electronic device and a method of manufacturing the same. In the laminated chip electronic device and the method of manufacturing the same according to the present invention, a body is made of a non-linear resistance coefficient material and has a plurality of conductive layers formed therein; an insulating layer is formed on the top, bottom, front and back surfaces of the body; and two electrodes are formed at the two ends of the body and electrically connected to the terminals of the conductive layers, respectively. Furthermore, in the present invention, two soldered interface layers are formed on the two electrodes, respectively.

Abstract: The semiconductor device of the present invention includes: a substrate; a first conductor film supported by the substrate; an insulating film formed on the substrate to cover the first conductor film, an opening being formed in the insulating film; and a second conductor film, which is formed within the opening of the insulating film and is in electrical contact with the first conductor film. The second conductor film includes: a silicon-containing titanium nitride layer formed within the opening of the insulating film; and a metal layer formed over the silicon-containing titanium nitride layer. The metal layer is mainly composed of copper.

Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.

Abstract: A method for fabricating a surface-emission semiconductor laser on a p-type substrate includes the step of interposing an Au film between an AuGeNi film or AuGe film of an n-side electrode and a compound semiconductor layer of an n-type DBR, followed by annealing to form an Au alloy in the n-side electrode. The presence of the Au alloy film improves the adherence between the n-side electrode and the compound semiconductor layer to improve an injection current vs. applied voltage characteristic.

Abstract: An active matrix substrate comprises a matrix array of TFTs. A double-layered film includes an under-layer of aluminum-neodymium (Al—Nd) alloy and an over-layer of high melting point metal. The double-layered film forms first interconnection lines for connection to the TFTs. A triple-layered film includes an under-layer of said high melting point metal, a middle-layer of said Al—Nd alloy and an over-layer of the high melting point metal. The triple-layered film forms second interconnection lines for connection to the TFTs.

Abstract: An under-bump-metallurgy layer is provided. The under-bump-metallurgy layer is formed over the contact pad of a chip and a welding lump is formed over the under-ball-metallurgy layer. The under-bump-metallurgy layer comprises an adhesion layer, a barrier layer and a wettable layer. The adhesion layer is directly formed over the contact pad. The barrier layer made from a material such as nickel-vanadium alloy is formed over the adhesion layer. The wettable layer made from a material such as copper is formed over the barrier layer. The wettable layer has an overall thickness that ranges from about 3 ?m to about 8 ?m.

Abstract: A method for manufacturing a semiconductor device can simply form a silicide film for reducing ohmic contact between a metal line and a substrate and a ternary phase thin film as an amorphous diffusion prevention film between a metal line and the silicide film. The method for manufacturing a semiconductor device includes the steps of sequentially forming a first refractory metal and a second refractory metal on a semiconductor substrate, forming a silicide film on an interface between the semiconductor substrate and the first refractory metal, and reacting the semiconductor substrate with the first and second refractory metals on the silicide film to form a ternary phase thin film.

Abstract: A method and structure for forming a refractory metal liner, includes depositing a layer of refractory metal on a first conductive layer, at least half of the depositing being carried out in the presence of an amount of passivating agent that is sufficient to impede subsequent reaction of at least a top half of the layer of refractory metal with the first conductive layer and is less than an amount of passivating agent necessary to form a stoichiometric refractory metal with the passivating agent, and annealing the refractory metal and the first conductive layer in a first element ambient, thereby forming a stoichiometric refractory metal with the first element in at least a portion of the top half of the layer of refractory metal.

Abstract: Nickel silicide formation with significantly reduced interface roughness is achieved by forming a diffusion modulating layer between the underlying silicon and nickel silicide layers. Embodiments include ion implanting nitrogen into the substrate and gate electrode, depositing a thin layer of titanium or tantalum, depositing a layer of nickel, and then heating to form a diffusion modulating layer containing nitrogen at the interface between the underlying silicon and nickel silicide layers.

Abstract: A semiconductor device is provided which includes a semiconductor substrate, metal conductors formed on a side of a main face of the substrate, which metal conductors contain aluminum as a main constituent thereof, and copper as an additive element, the metal conductors being made to contain such an element as to suppress the precipitation of copper or being made to have such a film adjacent to the metal conductor as to suppress the precipitation of copper or being made to have such a film adjacent to the metal conductor as to suppress the precipitation of copper.

Abstract: The present invention discloses a substrate within a Ni/Au structure electroplated on electrical contact pads and a method for fabricating the same. The method comprises: providing a substrate with a circuit layout pattern and forming a conducting film on the surface of the substrate; depositing a first photoresist layer within an opening on said electrical conducting film surface to expose a portion of said circuit layout pattern to be electrical contact pads; removing the exposed conducting film uncovered by the first photoresist layer; depositing a second photoresist layer, covering the conducting film exposed in the openings of the first photoresist layer; electroplating Ni/Au covering the surface of the electrical contact pads; removing the first and second photoresists, and the conducting film covered by the photoresists; depositing solder mask on the substrate within an opening to expose said electrical contact pads.

Abstract: An object of the invention is to prevent the color on a surface of a plated metal layer from changing. The invention is a wiring substrate obtained by forming a wiring conductor made of a metal having a high melting point on an insulator, and coating a surface of the wiring conductor with an electroless plated metal layer, wherein the electroless plated metal layer contains an element of Group 1B and is free from lead.

Abstract: An under bump metallurgy structure is applicable to be disposed above the wafer and on the bonding pads of the wafer. The wafer comprises a passivation layer and an under bump metallurgy structure. The passivation layer exposes the bonding pads, and the under bump metallurgy structure including an adhesive layer, a first barrier layer, a wetting layer and a second barrier layer are sequentially formed on the bonding pads. Specifically, the material of the second barrier mainly includes tin-nickel alloy.

Abstract: An under bump metallurgy structure is applicable to be disposed above the wafer and on the bonding pads of the wafer. The wafer comprises a passivation layer and an under bump metallurgy structure. The passivation layer exposes the bonding pads, and the under bump metallurgy structure including an adhesive layer, a first barrier layer, a wetting layer and a second barrier layer are sequentially formed on the bonding pads. Specifically, the material of the second barrier mainly includes tin-copper alloy.

Abstract: A silicide method for integrated circuit and semiconductor device fabrication wherein a layer of nickel is formed over at least one silicon region of a substrate and a layer of cobalt is formed over the nickel layer. The cobalt/nickel bi-layer is then annealed to transform the bi-layer to a bi-silicide film having a cobalt-rich silicide portion and a nickel-rich silicide portion.

Abstract: For fabricating an interconnect structure formed within an interconnect opening surrounded by dielectric material, the interconnect opening is filled with a conductive fill material comprised of a bulk conductive fill material doped with a first dopant element and a second dopant element that is different from the first dopant element. The dielectric material is comprised of a first dielectric reactant element and a second dielectric reactant element. A diffusion barrier material is formed from a reaction of the first dielectric reactant element and the first dopant element that diffuses from the conductive fill material to the walls to the interconnect opening. In addition, a boundary material is formed from a reaction of the second dielectric reactant element and the second dopant element that diffused from the conductive fill material to the walls of the interconnect opening.

Abstract: A leadframe for use in the assembly of integrated circuit (IC) chips, which has first and second surfaces and a base metal structure (606) with an adherent layer (607) of nickel having a rough, non-reflecting surface covering the base metal. This rough nickel enhances adhesion to molding compounds. An adherent layer (608) of smooth, reflective nickel selectively covers the first surface of the leadframe in areas intended for attachment of bonding wires and the IC chip. This smooth nickel facilitates the use of vision systems. A first adherent metal layer (609) is deposited in selected areas of the first leadframe surface for wire bond attachment, and a second adherent metal layer (610) is deposited to provide attachment to external parts.

Abstract: A method for forming a nickel cap layer over copper metalized bond pad is disclosed in which the phosphorous content of the nickel cap, and particularly the surface of the nickel cap, may be controlled. The phosphorous content of the surface of the nickel cap is suitably determined such that oxidation is inhibited. The resulting nickel cap may be wire-bonded directly, without the deposition of a gold cap layer.

Abstract: An under-ball-metallurgy layer between a bonding pad on a chip and a solder bump made with tin-based material is provided. The under-ball-metallurgy layer at least includes an adhesion layer over the bonding pad, a nickel-vanadium layer over the adhesion layer, a wettable layer over the nickel-vanadium layer and a barrier layer over the wettable layer. The barrier layer prevents the penetration of nickel atoms from the nickel-vanadium layer and reacts with tin within the solder bump to form inter-metallic compound. This invention also provides an alternative under-ball-metallurgy layer that at least includes an adhesion layer over the bonding pad, a wettable layer over the adhesion layer and a nickel-vanadium layer over the wettable layer. The nickel within the nickel-vanadium layer may react with tin within the solder bump to form an inter-metallic compound.

Abstract: The present invention provides an electrically conductive layer comprising a copper alloy which includes at least one of Ag, As, Bi, P, Sb, Si, and Ti in the range of not less than 0.1 percent by weight to not more than a maximum solubility limit to copper, so that the copper alloy is in a solid solution and/or which includes at least one of Mo, Ta and W in a range of not less than 0.1 percent by weight to not more than 1 percent by weight.

Abstract: An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the dielectric layer to expose a portion of the surface of the first layer. A binding layer is formed on the dielectric layer and on the exposed portion of the surface of the first layer and a second layer of conductive material is formed on the conductive binding layer. The binding layer can be an oxide and the second layer a conductive material that is diffusible into an oxide. The electrode structure can be annealed to cause conductive material from the second layer to be chemisorbed into the binding layer to improve adhesion between the first and second layers. A programmable cell can be formed by forming a doped glass layer in the electrode structure.

Abstract: A monolithic semiconducting ceramic electronic component includes barium titanate-based semiconducting ceramic layers and internal electrode layers alternately deposited, and external electrodes electrically connected to the internal electrode layers. The semiconducting ceramic layers contain ceramic particles having an average particle size of about 1 &mgr;m or less and the average number of ceramic particles per layer in the direction perpendicular to the semiconductor layers is about 10 or more. The internal electrode layers are preferably composed of a nickel-based metal.

Abstract: A structure in which a phosphorus-nickel layer, a rich phosphorus nickel layer that contains phosphorus or boron higher than this phosphorus-nickel layer, a nickel-tin ally layer, a tin-rich tin alloy layer, and a tin alloy solder layer are formed in sequence on an electrode. Accordingly, adhesiveness between a metal pattern used as the electrode, the wiring, or the pad and the solder can be improved.

Abstract: A packaging substrate for electronic elements comprises a first area for receiving an electronic element through flip chip bonding and a second area for receiving an electronic element through wire bonding. The first area has a bonding pad having applied on a surface thereof a coating of a solder material. The packaging substrate is used in the production of an electronic device having mounted thereon electronic elements such as semiconductor chips.

Abstract: An organic electro-luminescence device that is adapted to improve its characteristic by using materials being different from each other and corresponding to each function for a formation of data lines, gate lines and supply voltage lines. The organic electro-luminescence device includes a plurality of gate lines for receiving scanning signal; a plurality of data lines for receiving data signal; and a plurality of supply voltage lines arranged alternatively with the data lines, wherein at least one of the gate line, the data line and the supply voltage line is a wiring formed from a metal material having a high melting point. The organic electro-luminescence device allows metal materials of high melting points for forming the gate line, the data line and the supply voltage line to be different from each other. Accordingly, the organic electro-luminescence device reduces defects that can be generated at the wiring formation. As a result, the organic electro-luminescence device can be highly productive.

Abstract: By a solder bump, a CSP is bonded to a first electrode of the module substrate of a multi-chip module. For this solder bump, a solder added with an alkaline earth metal such as Ba, Be, Ca or Mg is used. Accordingly, upon solder reflow, phosphorous (P) reacts with the alkaline earth metal, thereby forming a P compound. Owing to dispersion of this P compound inside of the solder bump, no P concentrated layer is formed on the Ni film, making it possible to prevent peeling of the solder bump from the first electrode upon solder reflow. Thus, the present invention makes it possible to improve the solder bonding property.

Abstract: A solder terminal and a fabrication method thereof are provided. According to one embodiment of the present invention, a solder terminal structure includes an adhesion metal layer formed on an electrode pad of a semiconductor device, a thermal diffusion barrier, a solder bonding layer, and a solder bump formed on upper portion of the solder bonding layer. With the thermal diffusion layer, the characteristic deterioration caused by the probe mark generated on the electrode pad can be prevented during a semiconductor reliability test, and at the same time, material movement between the layers of the electrode pad, the solder bonding layer and the adhesion metal layer can be reduced. Also, by having the thermal diffusion barrier act as a solder dam (a layer to confine the melted solder area to prevent the solder from being wetted), an additional deposition or etching process can be omitted.

Abstract: The semiconductor device of the present invention includes: a gallium nitride (GaN) compound semiconductor layer; and a Schottky electrode formed on the GaN compound semiconductor layer, wherein the Schottky electrode contains silicon.

Abstract: There is provided is a metal line structure in which no defect of blistering occurs on a surface of a Cu/Ni film or a Cu/Au/Ni film even if an Ni plating thickness is reduced. According to this metal line 1, in a Cu/Au/Ni film structure in which an Au film 13 and a Cu film 15 are successively laminated by electroless plating on an Ni film 12 formed by electroless plating, the Ni film 12 has a phosphorus content x of 10 wt %≦x≦15 wt %. It was discovered through experiments that the so-called high phosphorus content type Ni film 12 having a phosphorus content x of 10 to 15 percent by weight became a fine smooth film under a condition of a film thickness of 0.1 &mgr;m or greater.

Abstract: A layer of gold (405) is disposed on upper surfaces (225) of copper pillars (210) on a bumped wafer (205). Coating material (410) is then applied to a level which is less than the height of the copper pillars (210), and etchant is disposed to remove coating material on the layer of gold (405) and to remove coating material (410) adhering to side surfaces of the copper pillars (210). Solder deposits are then disposed on the gold layer and reflowed to form balls (405) on the ends of the copper pillars (210), with the copper pillars (210) protruding into the solder balls (405).

Abstract: A composite Pt/Ti/WSi/Ni Ohmic contact has been fabricated by a physical deposition process which uses electron beam evaporation and dc-sputter deposition. The Ni based composite Ohmic contact on n-SiC is rapid thermally annealed (RTA) at 950° C. to 1000° C. for 30s to provide excellent current-voltage characteristics, an abrupt, void free contact-SiC interface, retention of the as-deposited contact layer width, smooth surface morphology and an absence of residual carbon within the contact layer and/or at the Ohmic contact-SiC interface. The annealed produced Ni2Si interfacial phase is responsible for the superior electrical integrity of the Ohmic contact to n-SiC. The effects of contact delamination due to stress associated with interfacial voiding has been eliminated. Wire bonding failure, non-uniform current flow and SiC polytype alteration due to extreme surface roughness have also been abolished.

Abstract: A method is described for filling of high aspect ratio contact vias provided over silicon containing areas. A via is formed in an insulating layer over the silicon containing area and a silicide forming material is deposited in the via. A silicide region is formed over the silicon containing area, the silicide forming material is removed from the via leaving the silicide region. The via is then filled with a conductor using an electroless plating process.

Abstract: There is provided a electronic parts packaging structure that includes a mounted body on which an electronic parts is mounted, the electronic parts having a connection pad, which has an etching stopper film (a copper film, a gold film, a silver film, or a conductive past film) as an uppermost film, and mounted on the mounted body to direct the connection pad upward, an interlayer insulating film for covering the electronic parts, a via hole formed in the insulating film on the connection pad of the electronic parts, and a wiring pattern connected to the connection pad via the via hole.

Abstract: A leadframe for use with integrated circuit chips comprising a leadframe base made of aluminum or aluminum alloy having a surface layer of zinc; a first layer of nickel on said zinc layer, said first nickel layer deposited to be compatible with aluminum and zinc; a layer of an alloy of nickel and a noble metal on said first nickel layer; a second layer of nickel on said alloy layer, said second nickel layer deposited to be suitable for lead bending and solder attachment; and an outermost layer of noble metal, whereby said leadframe is suitable for solder attachment to other parts, for wire bonding, and for corrosion protection.

Abstract: A defect-free film is formed on a surface of a protrusive electrode. An immersion Au film is formed on the surface of the protrusive electrode, after a gap which an immersion Au plating liquid can enter evenly is formed between a protrusive electrode made of Ni or a Ni alloy on an electrode pad made of Al or mainly made of Al and a protective coat by etching.

Abstract: A member having a metal layer is disclosed. The member is a silicon substrate or quartz substrate, for example, which is mainly composed of silicon or silicon oxide. A plurality of overhanging depressions are created on the surface of the member, and an anchor layer is formed thereon by filling the depressions. On the anchor layer is formed a metal film. The depressions are created by physical grinding followed by chemical etching. The anchor layer is NiP or NiB, for example. The metal layer is Au or AuSn, for instance.

Abstract: In a process of fabricating flip chip interconnection, a UBM layer is deposited on an I/O pad of a chip. The UBM layer includes a nickel layer. On the UBM layer is formed a tin-containing solder material. The chip is mounted on a carrier substrate by alignment of the bonding pad with a contact pad of the carrier substrate. A reflow process is performed to respectively turn the tin-containing solder material to a tin-containing solder bump and form a composite intermetallic compound on the nickel layer of the UBM to prevent its spalling.