Abstract: A first thin film resistor formed by direct etch or lift off on a first dielectric layer that covers an integrated circuit in a substrate. A second thin film resistor comprised of a different material than the first resistor, formed by direct etch or lift off on the first dielectric layer or on a second dielectric layer over the first dielectric layer. The first and second thin film resistors are interconnected with another electronic device such as other resistors or the integrated circuit.

Abstract: A pinning process including the steps of gold-plating through-holes in a laminate carrier and crimping old or gold-plated pin located in the through-holes to form a pin head on the top and a pin bulge on the bottom of the laminate carrier to produce a plastic pin grid array. A variety of mechanical forming processes may be employed to form the pin heads and pin bulges and cause the pin to at least partially, and preferably substantially, fill and contact the gold-plated through-hole including swage pinning, impact pinning, and double-die pinning operations. By combining the steps of gold-plating through-holes of a laminate carrier and using a mechanical pinning process to crimp a gold or gold-plated pin in the through-holes, a reliable mechanical and electrical connection may be established between the pin and the metal lines both inside and on the surface of the laminate carrier without the need for lead-containing solders and pastes.

Abstract: This circuit board contains electronic components having electrical contacts. At least one of the electrical contacts is initially glued to the circuit board using a conductive adhesive and at least one of the electrical contacts is connected to the circuit board by soldering. The circuit board is suitable for fast mechanical mass production. Further a method for the manufacture of the connection between the circuit board and the electronic components is disclosed, in which a solder is applied to soldering points and a conductive adhesive is applied to adhesive points. The circuit board with the components is then placed in a furnace to connect the components to the circuit board.

Abstract: An electronic device includes a first conductive polymer layer sandwiched between a first external metal foil electrode and a first internal metal foil electrode, a second conductive polymer layer sandwiched between a second internal metal foil electrode and a second external metal foil electrode, a layer of fiber-reinforced epoxy resin bonding the first and second internal electrodes together, a first terminal providing electrical contact between the first internal electrode and the second external electrode, and a second terminal providing electrical contact between the second internal electrode and the first external electrode. In a preferred embodiment, the polymer layers exhibit PTC behavior, and the terminals are formed by a solder layer applied over a plated layer of conductive metal. Insulative layers are preferably provided on the external electrodes, and located so as to insulate the first and second terminals from each other.

Abstract: A pad metal film used to fit a conductor for external connection composed of a bump-like or wire-like conductor can be formed by reduced numbers of processes. A semiconductor device is so configured that a trench for interconnect with its diameter of about 50 &mgr;m and its depth of about 2 &mgr;m is formed on a protective insulating film, formed on a semiconductor substrate, with a thickness of 3 to 4 &mgr;m, and in the trench for interconnect is imbedded an uppermost-layered copper wiring through a first barrier metal film composed of a titanium nitride with a thickness of about 50 nm. Furthermore, approximately in the center region of the upper-layered copper wiring is imbedded a copper pad film through a second barrier metal film with a thickness of about 70 nm.

Abstract: The substrate according to the present invention is comprised of a silver/gold/grain element alloy layer, wherein the alloy forms an outside layer of the product. The grain element is selected from a group consisting of selenium, antimony, bismuth, nickel, cobalt, indium and combination thereof. The present invention has a particular application in forming the outside layer of various items, including a lead frame, a ball grid array, a header, a printed circuit board, a reed switch and a connector.

Abstract: A semiconductor device having bonding pad electrode or electrodes of a multi-layer structure. The bonding pad electrode comprises a lower electrode layer formed on a semiconductor substrate, and a cover insulating film formed on the lower electrode layer. The cover insulating film has an opening for exposing at least a portion of the lower electrode layer. A step portion is provided at a side wall of the opening of the cover insulating film. The size of the opening at the upside portion of a step surface of the step portion is larger than the size of the opening at the downside portion of the step surface. The bonding pad electrode further comprises an upper electrode layer formed on the portion of the lower electrode layer exposed via the opening. The upper electrode layer is made of material having corrosion resistance against the substance which is corrosive to the lower electrode layer, and the upper electrode layer overlaps the step surface of the step portion.

Abstract: Low resistance contacts are formed on source/drain regions and gate electrodes by selectively depositing a reaction barrier layer and selectively depositing a metal layer on the reaction barrier layer. Embodiments include selectively depositing an alloy of cobalt and tungsten which functions as a reaction barrier layer preventing silicidation of a layer of nickel or cobalt selectively deposited thereon. Embodiments also include tailoring the composition of the cobalt tungsten alloy so that a thin silicide layer is formed thereunder for reduced contact resistance.

Abstract: To realize an ohmic electrode having practically satisfactory characteristics relative to GaAs semiconductors, first formed on an n+-type GaAs substrate are a Ni thin film with a thickness between 8 nm and 30 nm, an In thin film with a thickness between 2 nm and 6 nm and a Ge thin film with a thickness between 10 nm and 50 nm, sequentially. After that, the n+-type GaAs substrate having formed the Ni thin film, In thin film and Ge thin film is annealed at a temperature between 300 to 600° C. for a few seconds to minutes. As a result, the ohmic electrode has a multi-layered structure including an n++-type re-grown GaAs layer re-grown from the n+-type GaAs substrate, InGaAs layer and NiGe thin film. Alternatively, before the annealing, a thin film of a refractory metal or its compound, such as Nb thin film, with or without another thin film of a wiring metal, such as Au thin film, may be further formed on the Ge thin film.

Abstract: There is provided an I/O pin by which an MCM is positively prevented from being damaged by solder flowing from the fore end to the base of the I/O pin when the I/O pin is soldered in the case of mounting the MCM. An I/O pin used for an electrical connection is provided, one end of which is perpendicularly fixed to an MCM and the other end of which is soldered to a predetermined position on the mother board in the case of mounting the MCM on the mother board. In an intermediate portion of the I/O pin, there is formed a solder dam composed of a plated layer of Ni of low solder wettability, a layer of highly heat-resistant resin or a layer of high-temperature solder.

Abstract: An electrically resistive structure comprising a substrate (11) which is provided on at least one side with a first resistive film (13) and a second resistive film (17), the materials of these first and second films (13, 17) being mutually different, whereby an anti-diffusion film (15) is disposed between the first and second films (13, 17). The presence of such an anti-diffusion film (15) allows annealing of the resistive structure without significant degradation of its resistive properties. Suitable alloy materials for use in such an anti-diffusion film (15) include WTi, and particularly WTiN. Appropriate exemplary materials for the first resistive film (13) and second resistive film (17) include SiCr and CuNi alloys, respectively.

Abstract: A multi-layered metal bond pad for a semiconductor die having a conductive metal layer and an overlying ruthenium electrode layer. The ruthenium electrode layer protects the conductive metal from oxidation due to ambient environmental conditions. An interconnect structure such as a wire bond or solder ball may be attached to the ruthenium layer to connect the semiconductor die to a lead frame or circuit support structure. Also disclosed are processes for forming the ruthenium layer.

Abstract: Formed on the semiconductor chip surface are electrode pads, on which electroless Ni plated bumps are formed. The electroless Ni plated bumps are arranged in at least two rows in parallel with the two sides of the semiconductor chip, opposing each other. Each electroless Ni bump is 5 &mgr;m or more in height and the surface is coated with Au plating as a metal film. The surface of the conductor leads is coated with Sn plating. The conductor leads and bumps are heated and pressed by a bonding tool to crate Au/Sn eutectic alloy junctions.

Abstract: A copper-containing, wire-bonding pad structure for bonding to gold wires. The structure includes a nickel-containing film to improve metallurgical characteristics. The structure also has a laminated impurity film within the copper pad, which complexes with the nickel-containing pad to prevent a destructive interaction between nickel and copper at elevated temperatures, or during the lifetime of the device or the wirebond.

Abstract: A semiconductor body with a layer of solder material and a method for soldering the semiconductor body include a chromium layer applied to a rear side of the semiconductor body, and a tin layer applied to the chromium layer. The semiconductor is subsequently soldered directly to the metal substrate, that is without further additives, by being heated to temperatures above 250° C. This metal layer system for soldering power semiconductors to cooling bodies enables two metal layers to be dispensed with as compared with known four metal layer systems.

Abstract: In a semiconductor device, an opening having a high aspect ratio extends from a back surface of a GaAs substrate and is formed by anisotropic dry etching. After an Au film is deposited on the entire back surface of the GaAs substrate, including inside of the opening, a Ni alloy is non-electrolytically plated. The Ni film can also be deposited on the inner wall and the bottom of the opening. An IC substrate or FET may have the Ni film only at an area corresponding to the via hole. The back surface of the IC substrate or FET and the front surface of a package substrate are bonded to each other by AuSn solder poorly wetting the Ni film.

Abstract: A process for forming metal interconnect structures, and metal via structures, using electroplating, or electroless plating procedures, has been developed. The process features the use of disposable conductive layers, used as seed layers for the plating procedures. After formation of the desired metal structures, on the portion of seed layer, exposed in an opening in the photoresist shape, the photoresist shape, and the underlying portion of the disposable conductive layer, are removed, resulting in the desired metal structures.

Abstract: The present invention is directed toward the formation of implanted thermally and electrically conductive structures in a dielectric. An electrically conductive structure, such as an interconnect, is formed through ion implantation into several levels within a dielectric layer to penetrate into an electrically conductive region beneath the dielectric layer, such as a semiconductor substrate. Ion implantation continues in discreet, overlapping implantations of the ions from the electrical conductive region up to the top of the dielectric layer so as to form a continuous interconnect. Structural qualities achieved by the method of the present invention include a low interconnect-conductive region resistivity and a low thermal-cycle stress between the interconnect and the dielectric layer in which the interconnect has been implanted.

Abstract: There is described a circuit electrode formed in an integrated circuit package, which imparts sufficient bonding strength to a soldered section and prevents oxidation of the surface of an Ni—P film without fail. A circuit electrode to be electrically connected to a pattern formed on an organic substrate is formed. An electroless high-concentration Ni—P plating film containing phosphorous at a concentration of 7 to 12 wt. % is formed to a thickness of 3 to 10 &mgr;m so as to cover predetermined portions of the pattern. An electroless low-concentration Ni—P plating film containing phosphorous at a concentration of 3 wt. % or less is formed to a thickness of 0.5 to 10 &mgr;m so as to cover the electroless high-concentration Ni—P plating film. An electroless gold plating film is formed, as an oxidation prevention film, to a thickness of 0.05 to 0.5 &mgr;m so as to cover the surface of the electroless low-concentration Ni—P plating film.

Abstract: A low-thermal expansion circuit board comprising an insulating layer made of an organic polymer having thereon a wiring conductor for bare chip mounting, wherein the wiring conductor is an iron-nickel-based alloy layer having a copper layer on at least one side thereof; and a low-thermal expansion multilayer circuit board having a plurality of the low-thermal expansion circuit boards via an adhesive layer, the adhesive layer having through-holes filled with solder to connect the circuits layers.

Abstract: This invention relates to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface. The semiconductor device has a semiconductor chip, a lead member having a lead portion and an outer connecting terminal connected integrally to the lead portion, the lead portion electrically connected to the semiconductor chip, the lead portion extending outwardly from the semiconductor chip, the outer connecting terminal extending downwardly from the lead portion, a sealing resin sealing the semiconductor chip and the lead portion, a bottom face of the semiconductor chip and a bottom face of the lead portion being exposed from the sealing resin, and an insulating member covering the bottom face of the semiconductor chip and the bottom face of the lead portion.

Abstract: A layered lead is disclosed including a layer of structural material which has top and bottom sides, a layer of fatigue-resistant material on the top and bottom surfaces and a layer of bonding material covering the fatigue-resistant layer on the bottom surface for connection to a contact on a chip. An asymmetrical distribution of bonding material on the top and bottom sides may be used to provide reinforcement of the lead against stress. The fatigue-resistant material also acts as a barrier against diffusion between the metal layers.

Abstract: A thin film transistor (TFT) device including a first electrode including at least one of a gate, a source and a drain formed on a transparent insulating substrate, an insulating film layer covering both the first electrode and the transparent insulating substrate, and a transparent film electrode formed on the insulating film layer. The first electrode includes a first layer made of pure Al or Al alloy and a second layer, formed by an impurity selected from one of N, O, Si and C, added to the Al or Al alloy. The second layer of the first electrode is provided at an interconnection between the transparent film electrode and the first layer of the first electrode.

Abstract: In a chip package, when a Ni/Au layer is formed by electroless plating, there is no problem with density increasing of interconnections and the like, since leads for plating and tie bars are not formed. However, the adhesive strength of solder balls to ball pads is low, so that the adhesion tends to be unstable. In the present invention, no leads for plating are formed, while the adhesive strength of solder balls to ball pads is improved by electroplating the ball pads with a Ni/Au layer. In addition, an increase in the density of interconnections and an improvement of the electrical properties is also obtained. The Ni/Au layer is formed by electroplating on the base metal layer surface which is not covered with a DFR (Dry Film Resist) by applying an electric current to the base metal layer.

Abstract: An interconnection contact structure assembly including an electronic component having a surface and a conductive contact carried by the electronic component and accessible at the surface. The contact structure includes an internal flexible elongate member having first and second ends and with the first end forming a first intimate bond to the surface of said conductive contact terminal without the use of a separate bonding material. An electrically conductive shell is provided and is formed of at least one layer of a conductive material enveloping the elongate member and forming a second intimate bond with at least a portion of the conductive contact terminal immediately adjacent the first intimate bond.

Abstract: A process for producing a terminal metal pad structure electrically interconnecting a package and other components. More particularly, the invention encompasses a process for producing a plurality of corrosion-resistant terminal metal pads. Each pad includes a base pad containing copper which is encapsulated within a series of successively electroplated metal encapsulating films to produce a corrosion-resistant terminal metal pad.

Abstract: An integrated circuit chip (10, 50, 100) may comprise an integrated circuit (14, 54, 108, 110, 112) formed in a semiconductor layer (12, 52, 102). A thermal contact (16, 56, 116) may be formed at a high temperature region of the integrated circuit (14, 54, 108, 110, 112). A thick plated metal layer (40, 80, 140) may be generally isolated from the integrated circuit (14, 54, 108, 110, 112). The thick plated metal layer (40, 80, 140) may include a base (42, 82, 142) and an exposed surface (44, 84, 144) opposite the base (42, 82, 142). The base (42, 82, 142) may be coupled to the thermal contact (16, 56, 116) to receive thermal energy of the high temperature region. The exposed surface (44, 84, 144) may dissipate thermal energy received by the thick plated metal layer (40, 80, 140).

Abstract: A wiring substrate to which an IC chip is connected through soldering is formed from ceramic having electrode pads formed of a metallization layer. At least one nickel layer is formed on the electrode pads. The nickel layer has a thickness in the range of 2.5 &mgr;m to 8 &mgr;m. The nickel layer is preferably composed of a plurality of plated layers, and the outermost layer thereof is preferably formed through Ni-B plating. A gold plating layer is preferably formed on the outermost nickel layer. Further, heating is advantageously performed at least one time during the formation of the plurality of nickel layers.

Abstract: An interconnection structure suitable for the connection of microelectronic circuit chips to packages is provided by this invention. In particular, the invention pertains to the area-array or flip-chip technology often called C4 (controlled collapse chip connection). The structure comprises an adhesion/barrier layer deposited on a passivated substrate (e.g., a silicon wafer), optionally an additional adhesion layer, a solderable layer of a metal selected from the group consisting of Ni, Co, Fe, NiFe, NiCo, CoFe and NiCoFe on the adhesion/barrier layer, and a lead-free solder ball comprising tin as the predominate component and one or more alloying elements selected from Bi, Ag, and Sb, and further optionally including one or more elements selected from the group consisting of Zn, In, Ni, Co and Cu.

Abstract: An integrated circuit chip (10) includes a substrate (12), a plurality of transistors (16) provided in the substrate (12), a circuit pattern (14) provided on a top surface of the substrate (12) and a metal layer (42) comprising at least two metals in substantially eutectic proportions provided on a bottom surface of the substrate, the bottom surface of the metal layer (42) being exposed. The integrated circuit chip (10) can be attached to a farther substrate, e.g., a housing, using automated attachment techniques. The chip (10) can be attached to the housing by picking up the integrated circuit chip (10) with the metal layer (42) provided on the bottom surface thereof and placing the integrated circuit chip (10) onto a housing so the bottom surface of the integrated circuit chip (10) faces the housing with the metal layer (42) there between; and then heating the metal layer (42) to a temperature above its eutectic temperature to melt the metal layer and attach the integrated circuit chip (10) to the housing.

Abstract: An article comprising a metal circuit and/or a heat-radiating metal plate formed on a ceramic substrate, wherein the metal circuit and/or the heat-radiating metal plate comprise either (1) the following first metal-second metal bonded product, wherein the first metal and the second metal are different, or (2) the following first metal-third metal-second metal bonded product, and wherein in (1) and (2), the first metal is bonded to the ceramic substrate; first metal: a metal selected from the group consisting of aluminum (Al), lead (Pb), platinum (Pt) and an alloy containing at least one of these metal components; second metal: a metal selected from the group consisting of copper (Cu), silver (Ag), gold (Au), aluminum (Al) and an alloy containing at least one of these metal components; and third metal: a metal selected from the group consisting of titanium (Ti), nickel (Ni), zirconium (Zr), molybdenum (Mo), tungsten (W) and an alloy containing at least one of these metal components.

Abstract: A leadframe having the desirable features of palladium plated leadframes, such as compatibility with both wire bonding and solder reflow, as well as good adhesion to molding compounds is provided by plating the interior lead frame portions with one microinch of palladium and the external leads which contact solder with three microinches of palladium. A low cost method for fabricating the leadframe based on a unique combination of proven processes is provided.

Abstract: In a semiconductor device having a laminated metal layer in which a metal layer whose main component is aluminum and a metal layer whose main component is nickel are laminated on each other, the ratio (tAl/tNi) of the thickness (tAl) of the metal layer whose main component is aluminum to that (tNi) of the metal layer whose main component is nickel is controlled to 5 or larger, so that part of the metal layer whose main component is aluminum remains even if an Al—Ni intermetallic compound is formed.

Abstract: A lead frame lead and method of fabrication of the leadframe. A leadframe is formed from one of copper or copper-based material having a layer of an alloy of palladium and nickel and a coating of palladium formed over the alloy on the leadframe. The coating of palladium is from about 3 to about 10 microinches and preferably about 3 microinches. The palladium/nickel layer is from about 10 to about 40 microinches and preferably about 10 microinches and is an alloy having from about 40 to about 90 percent by weight nickel and the remainder essentially palladium. A preferred ratio is 75 percent by weight nickel and 25 percent by weight palladium. A semiconductor device is fabricated by providing a copper or copper-based leadframe and forming a layer of the palladium/nickel alloy over the entire leadframe followed by a palladium layer thereover while maintaining the assembly temperature below about 180 degrees C during subsequent device assembly.

Abstract: An electrode substrate comprises a backing substrate carrying thereon a metal electrode layer and/or a recording layer, the layer or layers having a smooth surface area with a surface roughness of less than 1 nm by more than 1 &mgr;m2. The smooth surface of the metal electrode layer and/or the recording layer is formed by firstly forming the layer on another substrate having a corresponding smooth surface and then peeling another substrate off the layer after the layer is bonded to the surface of the backing substrate, whereby the smooth surface profile of another substrate is transferred to the surface of the layer formed on the backing substrate.

Abstract: A package for mounting an integrated circuit chip to a circuit board or the like is provided. The package includes a chip carrier which has a metal substrate including first and second opposed faces. A dielectric coating is provided on at least one of the faces, which preferably is less than about 20 microns in thickness, and preferably has a dielectric constant from about 3.5 to about 4.0. Electrical circuitry is disposed on the dielectric coating, said circuitry including chip mounting pads, connection pads and circuit traces connecting the chip mounting pads to the connection pads. An IC chip is mounted by flip chip or wire bonding or adhesive connection on the face of the metal substrate which has the dielectric coating thereon. In any case, the IC chip is electrically connected to the chip mounting pads either by the solder ball or wire bond connections.

Abstract: A multi-layer plated lead frame is provided. The lead frame has a structure in which a first precious metal plating layer, an intermediate plating layer, and a second precious metal plating layer are sequentially formed on a substrate made of ferroalloy. The lead frame shows improvement in all properties including wire bonding, anti-corrosion, and solderability.

Abstract: To markedly reduce wafer warping of semiconductor wafers without weakening the strength of adhesion to substrate materials, a novel back side metallizing system is presented. On a silicon semiconductor body an aluminum layer and a diffusion barrier layer that includes titanium are provided. A titanium nitride layer is incorporated into the titanium layer because it has been demonstrated that the titanium nitride layer can compensate for a large proportion of the wafer warping that occurs. Preferably, the usual tempering for improving the ohmic contact between the aluminum layer and the silicon semiconductor body is not performed after the complete metallizing of the semiconductor body, but rather after a first, thin aluminum layer has been deposited onto the silicon semiconductor body.

Abstract: An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A 2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.

Abstract: A high temperature metallization system for use with a semiconductor device (23). The semiconductor device (23) has a multi-layer metallization system (36). An adhesion layer (37) of the metallization system (36) is formed on a semiconductor substrate (20). A barrier layer (38) that contains a nickel alloy is formed on the adhesion layer (37). A protective layer (39) is formed on the barrier layer (38). The barrier layer (38) inhibits solder components from diffusing toward the semiconductor substrate (20) during high temperature processing.

Abstract: The present invention relates generally to a new sequence of methods and materials to improve the process yield and to enhance the reliability of multilevel interconnection with sub-half-micron geometry by making judicious use of composite insulators to prevent metal thinning over hard metal via plugs and by preventing process induced metal spike formation. The method takes advantage of the double damascene process. The metal spikes and the metal thinning resulting from over etch process is prevented in this method by using a pair of insulators which require different chemistries for etching.

Abstract: A reactor for corona destruction of volatile organic compounds (VOCs), a multi-surface catalyst for the reactor and a method of making the catalyst for the reactor. The reactor has a catalyst of a high dielectric material with an enhanced surface area. A catalyst layer stack is formed by depositing a high dielectric layer on a substrate and, then depositing a conductive layer on the dielectric layer. The catalyst layer stack is bombarded by low RF energy ions to form an enhanced surface area and to form a protective layer over the conductive layer. Catalyst layer stacks may be joined back to form double-sided catalyst layer stacks. The catalyst layer stack may be diced into small pieces that are used in the reactor or the whole catalyst layer stack may be used.

Abstract: A semiconductor integrated circuit structure includes a semiconductor substrate; an electronic element disposed in the substrate; a first electrically insulating layer disposed on the substrate and the electronic element; a first electrically conducting interconnection layer electrically connected to the electronic element and disposed at least partly on the first electrically insulating layer; a second electrically insulating layer disposed on the first electrically conducting interconnection layer; a second electrically conducting interconnection layer disposed on the second electrically insulating layer; and a through-hole penetrating the second electrically insulating layer to the first electrically conducting interconnection layer, part of the second interconnection layer being disposed within the through-hole and contacting the first electrically conducting interconnection layer wherein the first electrically conducting interconnection layer includes a current barrier including at least one opening in t

Abstract: A lead structure is provided in a semiconductor device, having a body of a lead having at least a part of which is in contact with an adhesive which bonds with an insulation tape, and a protection layer selectively provided on the body of the lead so that the protection layer coats at least the part of the body in contact with the adhesive to completely isolate the body of the lead from the adhesive, to prevent an ion migration of a material of the body and also to prevent leakage of currents from and into the body of the lead.

Abstract: Two wafers are bonded together through an annealing process that maintains temperatures at CMOS compatible levels (i.e., below 500 degrees Celsius). A layer of palladium (Pd) is formed on a first wafer. Preferably an adhesion layer of chromium (Cr) attaches the palladium layer to the first wafer. The palladium layer is engaged with silicon (Si) from a second wafer, and the engaged wafers are annealed to form a palladium-silicide (PdSi) bond between the palladium layer of the first wafer and the silicon of the second wafer. In addition to bonding the first wafer to the second wafer, the palladium-silicon bond may be used to form an electrical connection between the two wafers so that circuits on both wafers may communicate to one another through the palladium-silicon bond.

Abstract: A first insulating film is formed on an integrated circuit chip on which an I/O pad is formed. A first opening portion is formed above the I/O pad. A conductive layer and a barrier metal layer which are electrically connected to the I/O pad through the first opening portion are stacked on the first insulating film. The conductive layer and the barrier metal layer are patterned by a single mask. A second insulating film is formed on the resultant structure. A second opening portion is formed in the second insulating film at a position different from that of the first opening portion. A solder bump or metal pad is formed on the barrier metal layer in the second opening portion. The position of the solder bump or metal pad is defined by the second opening portion.

Abstract: A first method of forming a thin film transistor substrate having at least an electrode interconnection, wherein a first low resistive metal layer is formed, which extends on the top surface of the substrate by sputtering method. A second low resistive metal layer is formed, which is highly resistant to chemicals and extends on the top of the first low resistive metal layer by sputtering method. A photo-resist film is applied on the second low resistive metal layer for exposure and development thereof to form a photo-resist etching mask. The first and second low resistive metal layers are subjected to an isotropic etching by use of the photo-resist etching mask. A third low resistive metal layer which is highly resistant to chemicals are formed over an entire region of the substrate by sputtering method. The third low resistive metal layer is subjected to a reactive ion etching to leave the third low resistive metal layer on the opposite sides of the first low resistive metal layer.

Abstract: A semiconductor package has a die and a plurality of leads electrically connected to the die with bonding wires. A heat spreader has an upper face thermally contacted with the die. The heat spreader is formed by a copper core having at least a portion of surface sequentially coated with a metal medium layer and an insulation layer, wherein the metal medium layer has an adhesion degree with insulation material higher than copper. A package body encapsulates the die, the heat spreader and the plurality of leads, wherein the surface area of the heat spreader that contacts with the package body is coated with the metal medium layer and the insulation layer.

Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.

Abstract: A semiconductor device having a CMOS structure comprising N-channel type and P-channel type insulated gate semiconductor devices combined in a complementary manner, wherein the threshold voltage of the insulated gate semiconductor devices is controlled by using the difference in work function between the gate electrode and the active layer. The present semiconductor device has excellent uniformity and reproducibility.