Abstract: A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction results primarily by building the memory arrays with 6F2 or smaller memory cells in a type of cross point memory cell layout. The memory arrays utilize stacked digitlines and vertical digitline twisting to achieve folded architecture operation and noise performance.

Abstract: A three dimensional circuit structure including tapered pillars between first and second signal lines. An apparatus including a first plurality of spaced apart coplanar conductors disposed in a first plane over a substrate; a second plurality of spaced apart coplanar conductors disposed in a second plane, the second plane parallel to and different from the first plane; and a plurality of cells disposed between one of the first conductors and one of the second conductors, wherein each of the plurality of cells have a re-entrant profile.

Abstract: There are provided a high density and low manufacturing cost wiring board with high reliability in connection, a semiconductor device and a producing method therefor.The invention relates to a wiring board comprising a board having an electrode and being coated with an insulation layer with a hole for exposing the electrode; a wiring consisting of a Cr or Ti layer, which is connected to the electrode and closely contacts with the insulation layer, and of a Cu layer which is closely contacts with the Cr or Ti layer; a protective film which covers the wiring and is provided with another hole for soldering; and a solder for the outer connection which is mounted in the both holes and brought to diffuse into the Cu layer to produce an alloy, and brought to reach the Cr or Ti layer thereby connecting the solder to the Cr or Ti layer.

Abstract: A semiconductor device includes a first insulating layer which is formed above a semiconductor substrate including a plurality of semiconductor elements and which includes lower-layer damascene wiring, a second insulating layer which is formed on the first insulating layer and which includes a second damascene wiring and an aligning wiring pattern forming a first step, and a first aligning surface wiring pattern including a surface wiring pattern to cover the second damascene wiring and a first aligning surface wiring pattern which is formed on the aligning wiring pattern and which has a second step reflecting the first step. The surface wiring pattern and the first aligning surface wiring pattern are formed using one surface wiring layer. A novel multilayer wiring structure thus obtained is suitably manufactured by the damascene process.

Abstract: A semiconductor device has a bump electrode formed in an opening of a passivation film of the device. The bump electrode is confined within the opening and formed away from via holes, which connects a top wiring layer for the bump electrode and a lower wiring layer connected to source and drain layers of the device.

Abstract: A solder ball array type package structure is able to control collapse. The package includes a substrate, a carrier, a plurality of dies, a molding compound and a plurality of solder balls. The substrate has at least one active surface. Pads are located on the first surface of the substrate. The carrier has at least an active surface and a back surface opposite the active surface. A plurality of dies are located on the back surface and the active surface of the carrier. The dies arranged on the active surface are electrically connected to the carrier by flip chip technology. A molding compound encapsulates on the back surface of the carrier to cover the dies on the back surface of the carrier. Solder balls having a base material are provided on the active surface of the carrier in array. At least three solder balls coated with the base material having a high melting-temperature core are further provided in the periphery of the array.

Abstract: A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction results primarily by building the memory arrays with 6F2 or smaller memory cells in a type of cross point memory cell layout. The memory arrays utilize stacked digitlines and vertical digitline twisting to achieve folded architecture operation and noise performance.

Abstract: A semiconductor device of the present invention is made up of a semiconductor chip and a single wiring tape resembling a film carrier and including a wiring layer that has a preselected pattern. The wiring tape is adhered to at least the top, bottom and one side of a semiconductor chip. The semiconductor device has outer connecting portions arranged on the above surface of the chip. The semiconductor device is comparable in package size with a bare chip. A semiconductor module having a plurality of such semiconductor devices arranged bidimensionally or tridimensionally achieves desirable electric characteristics while obviating the dense arrangement of a number of wirings.

Abstract: A balanced twist design for differential small signal pairs which is balanced in terms of resistance, capacitance and process variance. In the twist design of the present invention, each routing (6, 10) passes through two layers of metal. In addition, each routing (6, 10) passes through the same number of vias (9, 13, 14, 15), and experiences the same number of bends. Each routing (6, 10) is also exposed to the same sidewall crosstalk since the length and width of each routing (6, 10) in both metal layers is approximately the same. As a result, the new twist design reduces signal degradation, enhances signal separation, and allows increased clock speed of the integrated circuit.

Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.

Abstract: The signal-to-noise ratio of amorphous silicon (a-Si:H) image sensor arrays is limited by electronic noise, which is largely due to data line capacitance. To reduce data line capacitance, an air-gap (i.e., vacuum or gas-filled space) is produced at crossover points separating the data lines and gate lines. This air-gap crossover structure is formed by depositing a release material on the gate lines, forming the data lines on the release material, and then removing (etching) the release material such that the data lines form an arch extending over the gate lines. A dielectric material is then applied to strengthen the data line, and the sensor pixels are then formed.

Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.

Abstract: A method for forming a stack DRAM cell with CUB wherein coupling noise is eliminated is described. Bit-lines are formed according to one of three methods. In a first method, a first pair of bit-lines is fabricated in a first metal layer and a second pair of bit-lines is fabricated in a second metal layer separated from the first metal layer by an insulating layer wherein the first pair of bit-lines is horizontally spaced from the second pair of bit-lines. In a second method, a first of each pair of bit-lines is fabricated in a first metal layer and a second of each pair of bit-lines is fabricated in a second metal layer separated from the first metal layer by an insulating layer wherein the first of each pair of bit-lines is horizontally spaced from the second of each pair of bit-lines. In a third method, each bit-line is divided into segments.

Abstract: An integrated circuit device structure which avoids misalignment when a contact hole is formed to expose a contact pad and a method of fabricating the same, are provided. The integrated circuit device includes a semiconductor substrate having a conductive region and an insulating region, a contact pad on the conductive region of the semiconductor substrate, an auxiliary pad adjacent to the contact pad, and an interlevel insulating layer on the semiconductor substrate and having a contact hole for exposing both the contact pad and the auxiliary pad.

Abstract: A bump arrangement of a flip-chip is disclosed. The bump arrangement comprises: a conductive bumps array formed at a core region of the flip-chip, a first ring of conductive bumps surrounding the conductive bumps array, a second ring surrounding the first ring, a third ring surrounding the second ring, and a fourth ring surrounding the third ring. In the four rings of bumps, the bumps of the third ring and the fourth ring are staggered each other and most of them are provided for I/O signal terminal so as to reduce the length conductive traces for I/O signal connection. The bumps in the first and the second ring are provided for power connection or ground connection. The first ring, the second ring, the third ring, the fourth ring and the bump at the core region are connected to conductive traces of an interconnection layer through a redistribution layer. The redistribution layer is located in between a passivation layer and the interconnection layer.

Abstract: An object of the present invention is to provide a semiconductor device and a method of manufacturing the semiconductor device which can improve the flatness after the chemical mechanical polishing by inserting necessary and minimum dummy patterns and has high throughput.

Abstract: In a wiring board having a mounting region on which an integrated circuit having a plurality of terminals is mounted, and having a plurality of substrate-side wiring lines to be connected to the integrated circuit formed thereon, a conductor pattern is formed to extend in a substantially radial form from a prescribed point in the mounting region to reach two or more of the substrate-side wiring lines to be grounded.

Abstract: An address element, including a polysilicon resistor functioning as a heating element and blocking diode preventing sneak current to unaddressed elements, is selectively addressed using row and column address lines in a thin film structure having a minimum number of address lines and a minimum number of layers. The resistor heater element is well suited for igniting a fuel cell such as a fuel cell in an array of fuel cells disposed in a thin film microthruster.

Abstract: A multilayered wiring board comprising a first stacked structure consisting essentially of a first insulating layer having a first parallel conductor array and a second insulating layer formed thereon, having a second parallel conductor array oriented orthogonal to the first parallel conductor array, the first and second parallel conductor arrays being electrically interconnected by a first through conductor array; and a second stacked structure consisting essentially of a third insulating layer having a third parallel conductor array crossing at an angle of 30 to 60 degrees to the first parallel conductor array and a fourth insulating layer formed on top of the third insulating layer, having a fourth parallel conductor array orthogonal to the third parallel conductor array, the third and fourth parallel conductor arrays being electrically interconnected by a second through conductor array, wherein the second stacked structure is overlaid on the first stacked structure by interposing therebetween an intermedi

Abstract: A semiconductor die has three rows or more of bond pads with minimum pitch. The die is mounted on a package substrate having three rows or more of bond fingers and/or conductive rings. The bond pads on the outermost part of the die (nearest the perimeter of the die) are connected by a relatively lower height wire achieved by reverse stitching to the innermost ring(s) or row (farthest from the perimeter of the package substrate) of bond fingers. The innermost row of bond pads is connected by a relatively higher height wire achieved by ball bond to wedge bond to the outermost row of the bond fingers. The intermediate row of bond pads is connected by relatively intermediate height wire by ball bond to wedge bond to the intermediate row of bond fingers. The varying height wire allows for tightly packed bond pads. The structure is adaptable for stacked die.

Abstract: A conductive electrode pad is formed on a partial area of an insulating surface. An insulating film covers the electrode pad. The insulating film has an opening exposing at least a partial upper surface of the electrode pad. A barrier layer of conductive material is formed on the partial upper surface exposed on the bottom of the opening and on the surface of the insulating film near the opening. A conductive bump is adhered to the barrier layer. A step is formed on the surface of a layer under the barrier layer between an outer periphery of the barrier layer and an outer periphery of the opening.

Abstract: A semiconductor device is disclosed that includes a die having an active surface bearing integrated circuitry, the die including a plurality of bond pads thereon at least some of which are connected to the integrated circuitry and having at least one electrically conductive wire bond made between first and second bond pads of the plurality of bond pads for providing external electrical connection between the two bond pads.

Abstract: An integrated-circuit package with a quick-to-count finger layout design on substrate is proposed, which can help fabrication engineers to visually check the total number of fingers on the substrate in a quick and accurate manner. The proposed integrated-circuit package is characterized by the provision of a line-up array of fingers which includes a plurality of first-shape fingers partitioned equally in number into a plurality of subgroups; and a plurality of second-shape fingers, which are substantially visually distinguishable in outer appearance from the first-shape fingers, and which are interposed between adjacent subgroups of the first-shape fingers to serve as count tokens. This finger layout design allows the fabrication engineers to visually check the total number of the line-up array of fingers on the substrate simply by counting through the second-shape fingers that serve as count tokens and then multiply the result by the number of first-shape fingers in each subgroup plus one.

Abstract: A method and apparatus for creating air gaps to act as insulators within a semiconductor die. Wires, support structures, and sacrificial structures are constructed from vias and trenches. A top layer die is subdivided so that spaces reside between each adjacent subsection. The air gaps are created by etching the sacrificial structures via allowing etchant to seep through the spaces between subsections. After the air gaps have been created, the spaces residing between the subsections are sealed.

Abstract: A high density wordline strapping arrangement is obtained by routing three primary metal-2 wordline straps in the same space as four polysilicon wordline, and routing the fourth wordline strap in a metal-4 layer over the primary metal-2 wordline straps. Stitches in metal-3 connect metal-2 primary wordline straps to metal-4 wordline straps. Therefore, contact spacing and metal pitch limitations are relaxed to allow four metal wordline straps to occupy the same pitch as four polysilicon wordlines. The wordlines are twisted to keep the fully balanced and to minimise coupling between wordline straps and neighbouring power and signal lines. Hence, a smaller memory cell array can be formed according to the wordline packing arrangement of the present invention.

Abstract: A method and apparatus is provided for forming an electronic assembly whereby an insulating polymer matrix having a plurality of conductor holes is attached to a first substrate wherein the conductor holes align with a corresponding contact array on the first substrate. Subsequently, a flexible, electrically conductive adhesive is provided within the plurality of conductor holes and a solid conductive material, preferably having a high melting temperature, is attached to at least one end thereof. The insulating polymer matrix with the electrically conductive adhesive and the solid conductive material is then cured at a temperature sufficient to completely cure the matrix to completely surround the electrically conductive adhesive, as well as permanently attaching the matrix and conductive adhesive to the first substrate and permanently attaching the solid conductive material to the conductive adhesive.

Abstract: A customizable integrated circuit including a plurality of electrically conducting routing layers formed on a substrate for interconnecting a plurality of logic units formed on the substrate, including a first routing layer including a plurality of elongate conductors extending generally in a given direction, a second routing layer including a plurality of transversely extending conductors, each adapted for interconnecting a termination of one of the plurality of elongate conductors to a beginning of another one of the plurality of elongate conductors; and at least a third routing layer including a plurality of local routing conductors, a plurality of customizable connections, preferably arranged generally in at least one row, between pairs of the plurality of elongate conductors via individual ones of the plurality of transversely extending conductors and, preferably, customizable connections between individual ones of the plurality of elongate conductors and a plurality of individual ones of the local routi

Abstract: Provided are a manufacturing process for a semiconductor device capable of transferring a pattern corrected with respect of optical distortion of an exposure apparatus, a mask, and a manufacturing apparatus for a semiconductor deavice.

Abstract: There is a bi-level bit line architecture. Specifically, there is a DRAM memory cell and cell array that allows for six square feature area (6F2) cell sizes and avoids the signal to noise problems. Uniquely, the digit lines are designed to lie on top of each other like a double decker overpass road. Additionally, this design allows each digit line to be routed on both conductor layers, for equal lengths of the array, to provide balanced impedance. Now noise will appear as a common mode noise on both lines, and not as differential mode noise that would degrade the sensing operation. Furthermore, digit to digit coupling is nearly eliminated because of the twist design.

Abstract: A method of and an apparatus for electrically interconnecting two integrated circuits devices includes mounting the two devices face to face. A first device is mounted for example to a substrate or lead frame. The first device includes a plurality of electrical/physical mounting structures preferably positioned along one edge. The mounting structure provide both electrical interconnection and physical mounting. A second device includes a corresponding plurality of mounting structures configured as a mirror image of the mounting structures on the first device. The mounting structures on the second device are also positioned along one of its edges so that once the mounting structures are brought together in a face to face relationship, the second device cantilevers off the edge of the first device. Under certain circumstances, a dummy block can be mounted to the substrate adjacent to the first device to act as a strut or support for the second device.

Abstract: A semiconductor device is made up of a first insulating layer having a through hole; a first interconnection which comprises a first conductive layer, a first barrier layer, and a first main interconnection, and a second interconnection connected to one of the first conductive layer and the first barrier layer. Accordingly, the semiconductor device can avoid a problem so that the Cu of the first main interconnection transfers from a portion connected to the second interconnection due to cause electromigration, the connected portion becomes a void, and the first interconnection is disconnected to the second interconnection.

Abstract: A semiconductor device, a mounting structure thereof, a liquid crystal device, and an electronic apparatus having an improved bump electrode structure, such that the bump electrodes and corresponding electrode terminals can be electrically connected through an anisotropic conductive film without compromising, or causing deterioration of, the electrical characteristics or reliability of the device, even when the bump electrodes are formed with a narrow pitch. Since the bump electrodes of the semiconductor device are tapered inward from top to bottom, the base portions of adjacent bump electrodes are spaced apart from each other by wider gaps than the corresponding upper portions. Thus, a large number of conductive particles in the conductive film do not gather between adjacent bump electrodes to cause short-circuiting therebetween.

Abstract: A method for interconnecting high-temperature silicon carbide (SiC) devices enables such high-temperature devices to be used in fabricating electronic circuits of significant scale. This method comprises empirically measuring operational characteristics of a plurality of the devices to be interconnected, the operational characteristics comprising devices which are measured to be non-working and devices which are measured to be working; characterizing the operational characteristics in an operational characteristics map; designing interconnection paths between and among the devices that are characterized to be working by the operational characteristics map; and excluding from the interconnection paths, devices that are characterized to be non-working by the operational characteristics map.

Abstract: A wire-bonded semiconductor device with an improved wire-arrangement scheme is proposed, which can help minimize abnormal wire sweep during encapsulation process. Among the bonding wires on the semiconductor device, those located in corners would be mostly susceptible to abnormal wire sweep, particularly a high-loop bonding wire that is located in immediate adjacency to a low-loop bonding wire located in one corner of the wire-bonded semiconductor device. To solve this problem, the low-loop bonding wire that is located in immediate adjacency to the sweep-susceptible high-loop bonding wire is erected substantially to the same loop height as the high-loop bonding wire, so that it can serve as a shield to the sweep-susceptible high-loop bonding wire against the flow of injected resin during encapsulation process, thus preventing abnormal wire sweep.

Abstract: An address element, including a polysilicon resistor functioning as a heating element and blocking diode preventing sneak current to unaddressed elements, is selectively addressed using row and column address lines in a thin film structure having a minimum number of address lines and a minimum number of layers. The resistor heater element is well suited for igniting a fuel cell such as a fuel cell in an array of fuel cells disposed in a thin film microthruster.

Abstract: Provided are a manufacturing process for a semiconductor device capable of transferring a pattern corrected with respect of optical distortion of an exposure apparatus, a mask, and a manufacturing apparatus for a semiconductor device. The manufacturing process, regarding optical distortion of said exposure apparatus as a variation in reduction rate of a transferred pattern in each of regions, includes: a first step transferring a fundamental pattern formed on a reference photomask for measuring the optical distortion to measure a size of a transferred pattern in a corresponding one of regions; and a second step of, based on a result obtained in said first step, forming a corrected photomask having a pattern corrected in said corresponding one of regions with respect to said optical distortion.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: A multilayer thin film structure having defined strap repair lines thereon and a method for repairing interconnections in the multilayer thin film structure (MLTF) and/or making engineering changes (EC) are provided. The method comprises determining interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, defining the top surface metallization including a series of orthogonal X conductor lines and Y conductor lines using photoresist and lithography and additive or phototool to selectively expose the photoresist to define top surface strap connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization.

Abstract: There is a bi-level bit line architecture. Specifically, there is a DRAM memory cell and cell array that allows for six square feature area (6F2) cell sizes and avoids the signal to noise problems. Uniquely, the digit lines are designed to lie on top of each other like a double decker overpass road. Additionally, this design allows each digit line to be routed on both conductor layers, for equal lengths of the array, to provide balanced impedance. Now noise will appear as a common mode noise on both lines, and not as differential mode noise that would degrade the sensing operation. Furthermore, digit to digit coupling is nearly eliminated because of the twist design.

Abstract: A multi-layer semiconductor circuit comprising a plurality of conductive lines having air as a dielectric between the sides of the conductive lines in a first layer and having a structurally supportive non-metal cap layer at least partially covering the top of the conductive lines in the first layer and separating the air dielectric and conductive lines in the first layer from any subsequent layers. In a multi-layer semiconductor circuit with a plurality of conductive lines, at least the top, the bottom, and the opposite sides of each line are encapsulated by an adhesion-promotion barrier layer, and the barrier layer on the top of each conductive line has an upper surface that is flush with (a) a planar lower surface of a cap layer over the barrier layer, (b) a planar upper surface of a dielectric layer between the conductive lines, or (c) a combination thereof. The dielectric layer between the conductive lines may be air.

Abstract: A semiconductor structure for measuring a dielectric constant and clarifying a polarization effect of an interlevel dielectric layer is disclosed. The semiconductor structure comprises a substrate having a conductive layer thereon, an interlevel dielectric layer formed over the substrate, and a plurality of via walls formed into the interlevel dielectric layer connecting, overlapping and aligning with the conductive layer. The conductive layer comprises two areas of equidistant conductive lines and two conductive lines. Each area comprises two pluralities of equidistant conductive lines and one interposed individually between the other. The pluralities of equidistant conductive lines of the two areas are perpendicular to each other and connected by the two conductive lines. The via walls comprises pluralities of equidistant via walls connecting and aligning with the pluralities of equidistant conductive lines of the two areas.

Abstract: A half-bridge circuit includes: a vertically designed n-conducting first MOS transistor that is integrated in a first semiconductor body having a front side and a rear side; and a vertically designed p-conducting second MOS transistor that is integrated in a second semiconductor body having a front side and a rear side. The first and second transistors are connected in series between a first connection terminal and a second connection terminal. The half-bridge circuit also includes a drive circuit for driving the first and second transistors. The first and second transistors are applied to a common connection plate.

Abstract: A semiconductor bilateral switch that minimizes the on-state resistance by making a common-source connection between the switch transistors internal to the package. Wire bonds internally connecting the source electrodes of the transistors also provide the function of one or both of a current sense resistor and fuse element.

Abstract: A semiconductor device having reduced self and mutual capacitance of bonded wires is provided by coating the wires with a foamed polymer effectively having a very low dielectric constant. Additional benefits are realized by electrically insulating the wires against short-circuiting, by cushioning, the wires with a low modulus sheath, and by protecting, protecting chip bond pad metallization.

Abstract: In a wiring board wherein an opening is defined at a predetermined position of a film-like insulating substrate, an electric wiring provided with a connection terminal covering the opening is disposed on a principal plane of the insulating substrate, and a conductive member to be connected with the connection terminal of the electric wiring is disposed inside the opening; the conductive member having a thickness from a surface on which the electric wiring of the insulating substrate has been disposed is thinner than that of the insulating substrate.

Abstract: A semiconductor device including a structure having an upper surface and an contact surface formed at the upper surface of the structure. An insulating material is formed over the contact surface and a conductive runner extends over the active area such that a lower surface of the conductive runner is above and separated from the active area. A widened portion is formed in the conductive runner with an opening formed in the widened portion and self-aligned to edges of the widened portion. A conductive pillar is self-aligned to the opening and extends downward through the opening, through the insulating material, to the active area. The conductive runner provides local interconnection that can be routed over device features formed in and on the structure without using an additional metal layer.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60°. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: The present invention provides a multilayer circuit board for mounting thereon a semiconductor chip or other electronic elements having electrode terminals or other connection terminals which are arranged in a grid, staggered, or close-packed manner in an improved form to enable reduction in the number of the wiring layers for lead wiring lines, thereby facilitating the production of multilayer circuit boards and providing an improved product reliability.

Abstract: On transistors P1, P2, N1 and N2 constituting an NAND gate, a interconnection pattern W of metal having high melting point and aluminum interconnection patterns Al1 and Al2 are stacked. A local line LL for connecting transistors P1, P2, N1 and N2 to each other is formed by the interconnection pattern W of metal having high melting point, signal lines SL and SL′ for signal input/output between the NAND gate and the outside are formed by aluminum interconnection pattern Al1, and power supply lines VL and VL′ for applying power supply potentials Vcc and Vss to the NAND gate are formed by the aluminum interconnection pattern Al2. As compared with the prior art in which the local line LL is formed by the aluminum interconnection pattern Al1, the degree of freedom in layout can be improved and the layout area can be reduced.

Abstract: A connecting strength at a bonding site between a wiring layer 1c and a conductor 1d is enhanced by comparing a bonding strength between a wiring layer 14 provided by covering the conductor 1d on an insulating base 1a and the conductor 1d with a bonding strength between the wiring layer 1c and the insulating base 1a in an adjacency of the conductor to set the latter relatively lower.