With Adhesive Means Patents (Class 257/783)
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Patent number: 8674495Abstract: A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.Type: GrantFiled: February 25, 2011Date of Patent: March 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Pao Shu, Chun-Wen Cheng, Kuei-Sung Chang, Hsin-Ting Huang, Shang-Ying Tsai, Jung-Huei Peng
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Publication number: 20140061954Abstract: This disclosure relates generally to a semiconductor device and method of making the semiconductor device by pressing an electrical contact of a chip into a bonding layer on a carrier. The bonding layer is cured and coupled, at least in part, to the electrical contact. A molding layer is applied in contact with the chip and a first major surface of the bonding layer. Distribution circuitry is coupled to the electrical contact.Type: ApplicationFiled: August 29, 2012Publication date: March 6, 2014Inventor: Chuan Hu
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Publication number: 20140061905Abstract: Disclosed are photo sensitizers that include a polyol moiety covalently bonded to a fused aromatic moiety. Also disclosed is a method for improving UV laser ablation performance of a coating, such as a cationic UV curable coating, by incorporating an oxalyl-containing additive into the cationic UV curable or other coating. Oxalyl-containing sensitizers having the formula Q-O—C(O)—C(O)—O—R1 wherein Q represents a fused aromatic moiety and R1 is an alkyl or aryl group, are also disclosed, as are oxalyl-containing oxetane resins, oxalyl-containing polyester polyols, and cationic UV curable coating formulations that include oxalyl-containing additives.Type: ApplicationFiled: April 19, 2013Publication date: March 6, 2014Applicant: NDSU Research FoundationInventors: Dean C. Webster, Zhigang Chen
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Patent number: 8659175Abstract: An integrated circuit package system is provided including mounting a first integrated circuit device over a carrier, mounting a second integrated circuit device having an adhesive spacer over the first integrated circuit device in an offset configuration, connecting a first internal interconnect between the carrier and the first integrated circuit device with the first internal interconnect within the adhesive spacer, connecting a second internal interconnect between the carrier and the second integrated circuit device, and encapsulating the first integrated circuit device, the second integrated circuit device, the first internal interconnect and the second internal interconnect.Type: GrantFiled: June 12, 2007Date of Patent: February 25, 2014Assignee: Stats Chippac Ltd.Inventors: Jong Wook Ju, Taeg Ki Lim, Hyun Joung Kim
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Patent number: 8653668Abstract: A bonding structure and a copper bonding wire for semiconductor device include a ball-bonded portion formed by bonding to the aluminum electrode a ball formed on a front end of the copper bonding wire. After being heated at any temperature between 130° C. and 200° C., the ball-bonded portion exhibits a relative compound ratio R1 of 40-100%, the relative compound ratio R1 being a ratio of a thickness of a Cu—Al intermetallic compound to thicknesses of intermetallic compounds that are composed of Cu and Al and formed on a cross-sectional surface of the ball-bonded portion.Type: GrantFiled: February 3, 2011Date of Patent: February 18, 2014Assignees: Nippon Steel & Sumikin Materials Co., Ltd., Nippon Micrometal CorporationInventors: Tomohiro Uno, Takashi Yamada, Atsuo Ikeda
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Patent number: 8648476Abstract: The present invention provides a dicing tape-integrated wafer back surface protective film including: a dicing tape including a base material and a pressure-sensitive adhesive layer formed on the base material; and a wafer back surface protective film formed on the pressure-sensitive adhesive layer of the dicing tape, in which the wafer back surface protective film is colored. It is preferable that the colored wafer back surface protective film has a laser marking ability. The dicing tape-integrated wafer back surface protective film can be suitably used for a flip chip-mounted semiconductor device.Type: GrantFiled: June 26, 2013Date of Patent: February 11, 2014Assignee: Nitto Denko CorporationInventors: Naohide Takamoto, Takeshi Matsumura
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Patent number: 8643188Abstract: A semiconductor module system includes a substrate, at least one semiconductor chip, and a number of at least two electrically conductive first connecting elements. The substrate has a bottom side and a top side spaced apart from the bottom side in a vertical direction. The at least one semiconductor chip is arranged on the top side. Each one of the first connecting elements has a first end which protrudes away from an insulation carrier of the substrate in a direction perpendicular to the vertical direction. The semiconductor system further includes a connecting system with a number of N?1 connectors. A first one of the connectors includes at least two electrically conductive second connecting elements. Each one of the second connecting elements has a first end. The first end of each one of the first connecting elements is electrically conductively connectable to the first end of one of the second connecting elements.Type: GrantFiled: June 3, 2011Date of Patent: February 4, 2014Assignee: Infineon Technologies AGInventors: Thilo Stolze, Olaf Kirsch
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Patent number: 8643161Abstract: A semiconductor device includes a package substrate having a front surface and a backside surface; an electrode pad formed on the front surface; an outer connection pad formed on the backside surface and electrically connected to the electrode pad; a semiconductor chip mounted on the front surface and having an electrode electrically connected to the electrode pad; a sealing resin layer having a through hole formed with a die-molding and reaching the electrode pad for sealing the semiconductor chip; and a through electrode filled in the through hole with a conductive material and having one end portion electrically connected to the electrode pad and the other end portion exposed from the sealing resin layer.Type: GrantFiled: July 5, 2011Date of Patent: February 4, 2014Assignee: Oki Semiconductor Co., Ltd.Inventor: Hidenori Hasegawa
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Patent number: 8642391Abstract: A method of forming, on a surface of a substrate, at least one hydrophilic attachment area for the purpose of self-assembling a component or a chip, in which a hydrophobic area, which delimits the hydrophilic attachment area, is produced.Type: GrantFiled: April 7, 2009Date of Patent: February 4, 2014Assignee: Commissariat a l'energie atomique et aux energies alternativesInventors: Lea Di Cioccio, Francois Grossi, Pierric Gueguen, Laurent Vandroux
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Patent number: 8637945Abstract: A component having a robust, but acoustically sensitive microphone structure is provided and a simple and cost-effective method for its production. This microphone structure includes an acoustically active diaphragm, which functions as deflectable electrode of a microphone capacitor, a stationary, acoustically permeable counter element, which functions as counter electrode of the microphone capacitor, and an arrangement for detecting and analyzing the capacitance changes of the microphone capacitor. The diaphragm is realized in a diaphragm layer above the semiconductor substrate of the component and covers a sound opening in the substrate rear. The counter element is developed in a further layer above the diaphragm. This further layer generally extends across the entire component surface and compensates level differences, so that the entire component surface is largely planar according to this additional layer.Type: GrantFiled: April 7, 2010Date of Patent: January 28, 2014Assignee: Robert Bosch GmbHInventors: Frank Reichenbach, Thomas Buck, Jochen Zoellin, Franz Laermer, Ulrike Scholz, Kathrin van Teeffelen, Christina Leinenbach
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Patent number: 8638001Abstract: An object of the present invention is to provide an adhesive sheet that can capture cations mixed in from outside during various processes of manufacturing a semiconductor device to prevent deterioration in electrical characteristics of a semiconductor device to be manufactured and to improve product reliability. It is an adhesive sheet for producing a semiconductor device, in which when 2.5 g of the adhesive sheet is soaked in 50 ml of an aqueous solution containing 10 ppm of copper ions, and the solution is left at 120° C. for 20 hours, the concentration of copper ions in the aqueous solution is 0 to 9.9 ppm.Type: GrantFiled: May 16, 2012Date of Patent: January 28, 2014Assignee: Nitto Denko CorporationInventors: Yuta Kimura, Yasushi Inoue, Takeshi Matsumura
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Patent number: 8633592Abstract: In one embodiment, an interconnect structure between an integrated circuit (IC) chip and a substrate comprises a plurality of materials.Type: GrantFiled: July 26, 2011Date of Patent: January 21, 2014Assignee: Cisco Technology, Inc.Inventors: Michael G. Lee, Chihiro Uchibori
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Patent number: 8633600Abstract: A device includes a semiconductor material having a first surface. A first material is applied to the first surface and a fiber material is embedded in the first material.Type: GrantFiled: September 21, 2010Date of Patent: January 21, 2014Assignee: Infineon Technologies AGInventors: Manfred Mengel, Joachim Mahler, Khalil Hosseini
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Publication number: 20140008819Abstract: A substrate structure is provided, including a substrate and a strengthening member bonded to a surface of the substrate. The strengthening member has a CTE (Coefficient of Thermal Expansion) less than that of the substrate so as to effectively prevent warpage from occurring to the substrate structure.Type: ApplicationFiled: October 25, 2012Publication date: January 9, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chien-Feng Chan, Chun-Tang Lin, Yi-Che Lai
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Publication number: 20140001655Abstract: A device comprising a substrate, an integrated circuit (IC) die attached to the substrate on one side, a plurality of contact pads on an active side of the IC die, a plurality of thermally and electrically conductive legs, each of the legs attached to a respective one of the contact pads, and an encapsulating material formed around the substrate, the IC die, and a portion of the legs. A contact end of each of the legs is exposed, and one of the contact ends conducts a signal from a transistor in the IC die.Type: ApplicationFiled: June 29, 2012Publication date: January 2, 2014Inventor: MIN DING
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Patent number: 8618653Abstract: An integrated circuit package system includes: providing a singulated, layered structure equivalent in size to an integrated circuit die and having an adhesive layer, an electrical insulator layer, and a heat slug; attaching the integrated circuit die to a base; attaching bond wires to a top of the base for electrical connection between the integrated circuit die and the base; attaching the singulated, layered structure to the integrated circuit die wherein the bond wires are surrounded by the adhesive layer; and encapsulating the integrated circuit die and a portion of the heat slug with a molding compound.Type: GrantFiled: January 30, 2008Date of Patent: December 31, 2013Assignee: Stats Chippac Ltd.Inventors: WonJun Ko, Taeg Ki Lim, Sungmin Song
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Publication number: 20130341735Abstract: A stress isolator that allows a sensor to be attached to materials of the same coefficient of thermal expansion and still provide the required elastic isolation between the sensor and the system to which it is mounted. The isolator is made of two materials, borosilicate glass and silicon. The glass is the same material as the mounting surface of the microelectromechanical system (MEMS) sensors. The silicon makes an excellent isolator, being very elastic and easy to form into complex shapes. The two materials of the isolator are joined using an anodic bond. The construction of the isolator can be specific to different types of MEMS sensors, making the most of their geometry to reduce overall volume.Type: ApplicationFiled: June 26, 2012Publication date: December 26, 2013Applicant: HONEYWELL INTERNATIONAL INC.Inventors: Mark Eskridge, Shifang Zhou
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Publication number: 20130334713Abstract: The present disclosure relates to the field of fabricating microelectronic devices, wherein a microelectronic device substrate, such as a microelectronic wafer, may be thinned by a backgrinding process using a patterned adhesive tape that reduces slurry seepage and adhesive contamination while also reducing the potential of electrostatic discharge damage. The patterned adhesive tape may comprise a base film and adhesive material patterned on the base film such that an edge or periphery portion of the microelectronic device substrate may contact the adhesive material, but substantially no adhesive material contacts interconnectors formed on the microelectronic device substrate. The base film of the patterned adhesive tape may have an electrically conductive coating or layer, or may be electrically conductive itself to reduce the potential of electrostatic discharge damage during the backgrinding process.Type: ApplicationFiled: December 22, 2011Publication date: December 19, 2013Inventors: Dingying D. Xu, Wen Feng, Xavier Brun, Sandeep Iyer, Aaron Reichman
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Publication number: 20130334712Abstract: A method for manufacturing a chip package is provided. The method includes forming a layer over a carrier; forming further carrier material over the layer; selectively removing one or more portions of the further carrier material thereby releasing one or more portions of the layer from the further carrier material; and adhering a chip including one or more contact pads to the carrier via the layer.Type: ApplicationFiled: June 15, 2012Publication date: December 19, 2013Applicant: INFINEON TECHNOLOGIES AGInventor: Georg Meyer-Berg
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Patent number: 8610290Abstract: An integrated circuit chip has one or more electrically conductive nano-fibers formed on one or more contact pads of the integrated circuit chip. The one or more electrically conductive nano-fibers are configured to provide an adhesive force by intermolecular forces and establish an electrical connection with one or more contact pads disposed on the surface of a chip package.Type: GrantFiled: January 12, 2009Date of Patent: December 17, 2013Assignees: Lewis & Clark College, The Regents of the University of CaliforniaInventors: Kellar Autumn, Ronald S. Fearing, Steven D. Jones
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Publication number: 20130328218Abstract: A semiconductor device has an external terminal formed through the use of an electrolysis plating method. A front surface of a semiconductor wafer is placed over a front surface of a first support heated to a first temperature. An adhesive sheet is then bonded to a back surface of the semiconductor wafer, after which the semiconductor wafer is subjected to heat treatment at a second temperature higher than the first temperature. After the semiconductor wafer and the adhesive sheet are cut along cutting regions, a plurality of semiconductor chips each having an adhesive patch bonded thereto are obtained. A mother substrate is placed over a front surface of a second support heated to a third temperature and the semiconductor chips are fixed to an upper surface of the mother substrate via the adhesive patch.Type: ApplicationFiled: August 13, 2013Publication date: December 12, 2013Applicant: Renesas Electronics CorporationInventor: Hiroaki NARITA
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Patent number: 8604623Abstract: The present invention relates generally to thermally-conductive pastes for use with integrated circuits, and particularly, but not by way of limitation, to self-orienting microplates of graphite.Type: GrantFiled: July 20, 2012Date of Patent: December 10, 2013Assignee: International Business Machines CorporationInventors: Gareth Hougham, Paul A. Lauro, Brian R. Sundlof, Jeffrey D. Gelorme
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Patent number: 8604595Abstract: An electronic component includes lead fingers and a die paddle. A tape pad is mounted below the lead fingers and the die paddle. A first semiconductor chip is bonded onto the tape pad by a layer of first adhesive and a second semiconductor chip is bonded onto the die paddle by a layer of second adhesive. Electrical contacts are disposed between the contact areas of the semiconductors chips and the lead fingers. An encapsulating compound covers part of the lead fingers, the tape pad, the semiconductor chips and the electrical contacts.Type: GrantFiled: August 14, 2008Date of Patent: December 10, 2013Assignee: Infineon Technologies AGInventors: Chee Chian Lim, May Ting Hng
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Patent number: 8598719Abstract: A semiconductor element mounting board includes: a board having surfaces; a semiconductor element provided at a side of one of the surfaces of the board; a bonding agent layer through which the board and the semiconductor element are bonded together, the bonding agent layer having a storage modulus at 25° C. of 5 to 1,000 MPa; a first layer into which the semiconductor element is embedded, the first layer provided on the one surface of the board; a second layer provided on the other surface of the board, the second layer being constituted from the same material as that of the first layer, the constituent material of the second layer having the same composition ratio as that of the constituent material of the first layer; and surface layers provided on the first and second layers, respectively, each of the surface layers being formed from at least a single layer.Type: GrantFiled: June 3, 2009Date of Patent: December 3, 2013Assignee: Sumitomo Bakelite Company LimitedInventors: Mitsuo Sugino, Hideki Hara, Toru Meura
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Patent number: 8592996Abstract: A semiconductor device wherein a semiconductor element made of Si or Si group material mounted on a substrate, the semiconductor element is mounted on the substrate and the semiconductor element is bonded to a silver bonding material via a oxide film formed on the semiconductor element. The bonding material comprising silver oxide particles having an average particle size of 1 nm to 50 nm and an organic reducing agent is used for bonding in air, which gives a high bonding strength to the oxide on the semiconductor element.Type: GrantFiled: June 29, 2010Date of Patent: November 26, 2013Assignee: Hitachi, Ltd.Inventors: Toshiaki Morita, Yusuke Yasuda, Eiichi Ide
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Patent number: 8558400Abstract: A semiconductor package includes a wiring board including an upper connection pad provided on a first surface and a lower connection pad provided on a second surface opposite to the first surface, a semiconductor chip having a bonding pad area in which a bonding pad is provided and an adhesive area except the bonding pad area, and being mounted on the first surface of the wiring board in a flip-chip manner such that the bonding pad is electrically connected to the upper connection pad, a first molding layer provided between the adhesive area of the semiconductor chip and the first surface of the wiring board, and a second molding layer provided between the bonding pad area of the semiconductor chip and the first area of the wiring board while covering the first surface of the wiring board and the semiconductor chip. The first molding layer has a lower modulus than the second molding layer.Type: GrantFiled: August 5, 2011Date of Patent: October 15, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Woo Park, Eunchul Ahn
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Patent number: 8558397Abstract: The present invention provides a dicing tape-integrated wafer back surface protective film including: a dicing tape including a base material and a pressure-sensitive adhesive layer formed on the base material; and a wafer back surface protective film formed on the pressure-sensitive adhesive layer of the dicing tape, in which the wafer back surface protective film is colored. It is preferable that the colored wafer back surface protective film has a laser marking ability. The dicing tape-integrated wafer back surface protective film can be suitably used for a flip chip-mounted semiconductor device.Type: GrantFiled: June 27, 2012Date of Patent: October 15, 2013Assignee: Nitto Denko CorporationInventors: Naohide Takamoto, Takeshi Matsumura
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Patent number: 8552551Abstract: Adhesive/spacer structures used to adhere a first device, such as a die, or a package, to a second device in a stacked semiconductor assembly, include a plurality of spaced-apart adhesive/spacer islands securing the first and the second devices to one another at a chosen separation. Either or both of the first and second devices can be a die; or, either or both of the devices can be a package. A package includes a die mounted onto and electrically interconnected to, a substrate, and where one package is stacked over either a lower die or a lower package, the upper package may be oriented either so that the die attach side of the upper package faces toward the lower die or lower package substrate or so that the die attach side of the upper package faces away from the lower die or lower package substrate.Type: GrantFiled: May 20, 2005Date of Patent: October 8, 2013Assignee: CHIPPAC, Inc.Inventors: Sang Ho Lee, Jong Wook Ju, Hyeog Chan Kwon, Marcos Karnezos
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Patent number: 8552546Abstract: Provided is a semiconductor package. The semiconductor package may include a first semiconductor package having first semiconductor chips sequentially stacked on a substrate. In example embodiments, the first semiconductor chips may have a cascaded arrangement in which first sides and second sides of the semiconductor chips define cascade patterns. The cascaded arrangement may extend in a first direction to define a space between the first sides of the first semiconductor chips and the substrate. The semiconductor package may also include at least one first connection wiring at the second sides of the semiconductor chips, the at least one first connection wiring being configured to electrically connect the substrate with the first semiconductor chips. In addition, the semiconductor package may further include a first filling auxiliary structure adjacent to the first sides of the first semiconductor chips.Type: GrantFiled: October 1, 2010Date of Patent: October 8, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: In-Sang Song, Seok-Keun Lim, In-Wook Jung, Bong-Ken Yu, Sang-Wook Park, Ji-Seok Hong
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Publication number: 20130256857Abstract: In one embodiment, a method of forming a semiconductor package comprises providing a first die having contact regions on a top surface but not on an opposite bottom surface. A dielectric liner layer is deposited under the bottom surface of the first die. The first die is attached with the deposited dielectric liner layer to a die paddle of a substrate.Type: ApplicationFiled: March 27, 2012Publication date: October 3, 2013Applicant: Infineon Technologies AGInventors: Hermann Gruber, Joachim Mahler, Uwe Hoeckele, Anton Prueckl, Thomas Fischer, Matthias Schmidt
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Patent number: 8546958Abstract: The present invention provides a pressure-sensitive adhesive sheet for protecting a semiconductor wafer, which does not cause curve (warpage) in the semiconductor wafer, when the semiconductor wafer is ground, is excellent in followability to a pattern, has adequate stress dispersibility in a grinding operation, suppresses the crack in a wafer and chipping in a wafer edge, and does not leave a residue of a tackiness agent on the surface of the wafer. The protective sheet has one face having tackiness, does not have an interface existing between a substrate and the tackiness agent and is made of one layer, and the pressure-sensitive adhesive sheet has different tack strengths on both faces from each other.Type: GrantFiled: September 1, 2011Date of Patent: October 1, 2013Assignee: Nitto Denko CorporationInventors: Takashi Habu, Fumiteru Asai, Tomokazu Takahashi, Eiichi Imoto, Yuta Shimazaki
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Publication number: 20130249119Abstract: Provided is a semiconductor integrated circuit device having flexible pin arrangement. A semiconductor integrated circuit is bonded to a die pad with an insulating paste, and the potential of the die pad is fixed through a bonding wire from an Al pad provided on the surface of the semiconductor integrated circuit. In the case of a P-type semiconductor substrate, the die pad is set as a terminal other than a terminal having a minimum operating potential of the semiconductor integrated circuit.Type: ApplicationFiled: March 18, 2013Publication date: September 26, 2013Applicant: SEIKO INSTRUMENTS INC.Inventor: Hirofumi HARADA
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Patent number: 8525351Abstract: A semiconductor device includes a die pad, a semiconductor element which is loaded on the die pad, and a sealing resin. A plurality of electrically conductive portions each having a layered structure including a metal foil comprising copper or a copper alloy, and electrically conductive portion plating layers provided at both upper and lower ends of the metal foil are arranged around the die pad. The die pad has a lower die pad plating layer, and the semiconductor element is loaded on the die pad comprising such a die pad plating layer. Electrodes provided on the semiconductor element are electrically connected with top ends of the electrically conductive portions via wires, respectively. The lower electrically conductive portion plating layers of the electrically conductive portions and the die pad plating layer of the die pad are exposed outside from the sealing resin on their back faces.Type: GrantFiled: August 10, 2011Date of Patent: September 3, 2013Assignees: Dai Nippon Printing Co., Ltd., Nitto Denko CorporationInventors: Chikao Ikenaga, Kentarou Seki, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
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Publication number: 20130221542Abstract: A device includes a spacer, which includes a recess extending from a top surface of the spacer into the spacer, and a conductive feature including a first portion and a second portion continuously connected to the first portion. The first portion extends into the recess. The second portion is on the top surface of the spacer. A die is attached to the spacer, and a lower portion of the first die extends into the recess.Type: ApplicationFiled: February 24, 2012Publication date: August 29, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Ru Chang, Chung-Kai Wang, Ming-Che Wu
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Patent number: 8519549Abstract: An anisotropic conductive film (ACF) is disclosed. The ACF includes a film, an adhesive layer positioned on the film, and one or more conductive balls within the adhesive layer. The conductive balls include a first core part having a first hardness, a second core part covering the first core part and having a second hardness that is greater than the first hardness, and a conductive part covering the second core part, respectively.Type: GrantFiled: September 23, 2010Date of Patent: August 27, 2013Assignee: Samsung Display Co., Ltd.Inventors: Jung-Min Lee, Choong-Ho Lee
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Patent number: 8513061Abstract: The present invention relates to a through silicon via (TSV) for 3D packaging to integrate a semiconductor device and a method for manufacturing the same, and more particularly, to a through silicon via (TSV) for 3D packaging of a semiconductor device that is capable of improving production efficiency, having very high electric conductivity, and minimizing electrical signal delay, without using a carrier wafer by self-aligning substrates in a low temperature state and sequentially bonding a plurality of semiconductor dies (or semiconductor chips), and a method of manufacturing the same.Type: GrantFiled: February 22, 2011Date of Patent: August 20, 2013Assignee: Korea Institute of Machinery & MaterialsInventors: Jae-Hak Lee, Chang-Woo Lee, Joon-Yub Song, Tae-Ho Ha
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Patent number: 8513816Abstract: The present invention relates to a film for flip chip type semiconductor back surface, which is to be disposed on the back surface of a semiconductor element to be flip chip-connected onto an adherend, the film containing a resin and a thermoconductive filler, in which the content of the thermoconductive filler is at least 50% by volume of the film, and the thermoconductive filler has an average particle size relative to the thickness of the film of at most 30% and has a maximum particle size relative to the thickness of the film of at most 80%.Type: GrantFiled: June 30, 2011Date of Patent: August 20, 2013Assignee: Nitto Denko CorporationInventors: Naohide Takamoto, Goji Shiga, Fumiteru Asai
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Patent number: 8508043Abstract: A topographical feature is formed proximate to a conductive bond pad that is used to couple a solder bump to a semiconductor die. The topographical feature is separated from the conductive bond pad by a gap. In one embodiment, the topographical feature is formed at a location that is slightly beyond the perimeter of the solder bump, wherein an edge of the bump is aligned vertically to coincide with the gap separating the conductive bond pad from the topographical feature. The topographical feature provides thickness enhancement of a non-conductive layer disposed over the semiconductor die and the conductive bond pad and stress buffering.Type: GrantFiled: November 16, 2011Date of Patent: August 13, 2013Assignee: International Business Machines CorporationInventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, David L. Questad, Wolfgang Sauter, Timothy D. Sullivan
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Patent number: 8507803Abstract: The invention offers a board-connecting structure that can provide electrodes with a fine pitch and that can combine the insulating property and the connection reliability. The structure of connecting printed wiring boards 10 and 20 electrically connects a plurality of first electrodes 12 and 13 provided to be adjacent to each other on a first board 11 with a plurality of second electrodes 22 and 23 provided to be adjacent to each other on a second board 21 through an adhesive 30 that contains conductive particles 31 and that has anisotropic conductivity. By heating and pressing the adhesive placed between the mutually facing first electrode 12 and second electrode 22 and between the mutually facing first electrode 13 and second electrode 23, an adhesive layer 30a is formed between the first board 11 and the second board 21 and in the adhesive layer 30a, a cavity portion 33 is formed between the first electrodes 12 and 13 and between the second electrodes 22 and 23.Type: GrantFiled: March 12, 2010Date of Patent: August 13, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventors: Masamichi Yamamoto, Kyouichirou Nakatsugi, Ayao Kariya, Katsuhiro Satou, Yasuhiro Okuda
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Patent number: 8508039Abstract: In a method and system in accordance with the present invention, solder balls are added on top of vertically integrated MEMS with CMOS by using wafer scale fabrication compatible with existing chip scale packaging capabilities. In the present invention, both the MEMS and the CMOS dies are fabricated in equal dimensions. On the MEMS level, silicon islands are defined by DRIE etching to be bonded on top of CMOS pads. These conducting silicon islands later provide electrical connections between the CMOS pads and the conducting traces that lead to solder balls on top.Type: GrantFiled: May 8, 2008Date of Patent: August 13, 2013Assignee: Invensense, Inc.Inventors: Steven S. Nasiri, Goksen G. Yaralioglu
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Patent number: 8507080Abstract: Composite with a first part composed of a thermoset material and with a second part composed of a thermoplastic material, and with an adhesion-promoter layer located between these, where the first part has been bonded by way of the adhesion-promoter layer to the second part, and where the adhesion-promoter layer comprises pyrolytically deposited semiconductor oxides and/or pyrolytically deposited metal oxides.Type: GrantFiled: April 26, 2006Date of Patent: August 13, 2013Assignee: Infineon Technologies AGInventors: Joachim Mahler, Alfred Haimerl, Wolfgang Schober, Michael Bauer, Angela Kessler
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Patent number: 8502400Abstract: A dam stiffener for a package substrate is presented. In an embodiment, the dam stiffener comprises a thermally curable polymer, and is simultaneously cured with the underfill material to act as stiffener to the substrate. In another embodiment, a curable reservoir material can be dispensed to fill the space between the integrated circuit die and the dam stiffener, forming a thick reservoir layer, acting as an additional stiffener for the package substrate.Type: GrantFiled: March 6, 2012Date of Patent: August 6, 2013Assignee: Intel CorporationInventors: Prasanna Karpur, Sriram Muthukumar
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Patent number: 8501583Abstract: A resin containing a conductive particle and a gas bubble generating agent is supplied in a space between the substrates each having a plurality of electrodes. The resin is then heated to melt the conductive particle contained in the resin and generate gas bubbles from the gas bubble generating agent. A step portion is formed on at least one of the substrates. In the process of heating the resin, the resin is pushed aside by the growing gas bubbles, and as a result of that, the conductive particle contained in the resin is led to a space between the electrodes, and a connector is formed in the space. At the same time, the resin is led to a space between parts of the substrates at which the step portion is formed, and cured to fix the distance between the substrates.Type: GrantFiled: July 6, 2009Date of Patent: August 6, 2013Assignee: Panasonic CorporationInventors: Takashi Kitae, Seiji Karashima, Susumu Sawada, Seiichi Nakatani
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Patent number: 8492856Abstract: An electronic component includes: a semiconductor substrate having a first surface and a second surface opposing to the first surface; a trans-substrate conductive plug that penetrates the semiconductor substrate from the first surface to the second surface; an electronic element provided in the vicinity of the first surface of the semiconductor; and a sealing member that seals the electronic element between the sealing member and the first surface, wherein the electronic element is electrically connected to the trans-substrate conductive plug.Type: GrantFiled: June 22, 2012Date of Patent: July 23, 2013Assignee: Seiko Epson CorporationInventors: Haruki Ito, Nobuaki Hashimoto
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Patent number: 8492898Abstract: A printed circuit board to which a localised solder connection is to be made, the surface of said printed circuit board having a continuous or non-continuous coating of a composition comprising a halo-hydrocarbon polymer at a thickness of from 1 nm to 10 ?m.Type: GrantFiled: February 18, 2008Date of Patent: July 23, 2013Assignee: Semblant Global LimitedInventors: Frank Ferdinandi, Rodney Edward Smith, Mark Robson Humphries
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Patent number: 8482122Abstract: A conductive pad structure, configured in a peripheral circuit area of a device substrate, is provided. The conductive pad structure includes a conductive pad and a plurality of conductive spacers. The conductive spacers are configured on the conductive pad and arranged as a non-closed pattern on the conductive pad. Besides, a chip package structure and a device substrate that both have the above-mentioned conductive pad structure are also provided.Type: GrantFiled: March 25, 2011Date of Patent: July 9, 2013Assignee: Chunghwa Picture Tubes, Ltd.Inventor: Yen-Chieh Lin
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Publication number: 20130161837Abstract: A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art.Type: ApplicationFiled: June 7, 2012Publication date: June 27, 2013Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chia-Yin Chen, Yu-Ching Liu, Yueh-Chiung Chang, Yu-Po Wang
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Publication number: 20130161838Abstract: A semiconductor device bonded by an anisotropic conductive film, the anisotropic conductive film including a phenoxy resin including a fluorene-substituted phenoxy resin; and a radically polymerizable resin including a fluorene-substituted acrylate.Type: ApplicationFiled: December 20, 2012Publication date: June 27, 2013Inventors: Jae Sun HAN, Hyun Wook KIM, Hyun Hee NAMKUNG, Jin Young SEO, Kwang Jin JUNG, Dong Seon UH
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Patent number: 8472196Abstract: A power module includes a first heat sink, first and second power chips, a thermo-conductive insulating layer, a lead frame and a molding compound. The first heat sink has a first area and a second area. The first power chip is disposed in the first area. The thermo-conductive insulating layer is disposed in the second area. The second power chip is disposed on the heat sink through the thermo-conductive insulating layer. The lead frame is electrically connected to at least one of the first and second power chips. The molding compound covers the first and second power chips, the thermo-conductive insulating layer and a portion of the lead frame. The first heat sink is electrically connected to at least one of the first and second power chips. Because the first power chip is not disposed on the first heat sink through the thermo-conductive insulating layer, the cost can be reduced.Type: GrantFiled: March 16, 2011Date of Patent: June 25, 2013Assignee: Delta Electronics, Inc.Inventors: Jian-Hong Zeng, Shou-Yu Hong, Qi-Feng Ye, Yi-Cheng Lin
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Patent number: 8471392Abstract: An image pickup apparatus according to an embodiment includes: an image pickup device chip including an image pickup device formed on a first principal surface thereof and an external terminal for the image pickup device formed on a second principal surface thereof; a wiring board including a distal end portion including a connection pad, a flexure portion flexed at an angle of no less than 90 degrees, and an extending portion, the wiring board including a wiring layer extending from the distal end portion to the extending portion via the flexure portion, the wiring board being kept within a space immediately above the second principal surface of the image pickup device chip; a bonding layer that joins the second principal surface of the image pickup device chip and the distal end portion of the wiring board; and a bonding wire that electrically connects the external terminal and the connection pad.Type: GrantFiled: February 10, 2011Date of Patent: June 25, 2013Assignee: Olympus CorporationInventor: Kazuaki Kojima