Abstract: A semiconductor device includes: a substrate; first and second pads disposed adjacent to each other on the substrate; an electrically conductive tape adhered to the first and second pads and having a through hole at an inner portion of the first pad; an electrically conductive adhesive in the through hole and having a thermal conductivity higher than the thermal conductivity of the electrically conductive tape; a semiconductor chip mounted on the first pad via the electrically conductive adhesive; and an electronic component part mounted on the second pad via the electrically conductive tape.

Abstract: A mounting structure of an electronic component includes a plurality of joining portions that join a plurality of first electrode terminals on the electronic component to a plurality of second electrode terminals on a circuit board. The joining portions each include a first projecting electrode formed on the first electrode terminal, a second projecting electrode formed on the second electrode terminal, and a solder portion that joins the first projecting electrode to the second projecting electrode. The end face of the first projecting electrode is larger in area than the end face of the second projecting electrode, and at least a part of the second electrode terminals exposed from the circuit board has a larger area than the bottom of the second projecting electrode.

Abstract: A bump structure includes a first bump and a second bump. The first bump is disposed on a connection pad of a substrate. The first bump includes a lower portion having a first width, a middle portion having a second width smaller than the first width, and an upper portion having a third width greater than the second width. The second bump is disposed on the upper portion of the first bump.

Abstract: A method of attaching a die to a carrier using a temporary attach material is disclosed. The method comprises attaching the temporary attach material between a surface of the die and a surface of the carrier. The temporary attach material attaches the die to the carrier. The method comprises bonding at least one connector to the die and the carrier. The connector includes a first end bonded to the carrier and a second end bonded to the die. The method further comprises encapsulating at least a portion of the die and at least a portion of the at least one connector by an encapsulation material.

Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of reducing edge warping in a supported semiconductor wafer involves adhering a backside of a semiconductor wafer to an inner portion of a carrier tape of a substrate carrier comprising a tape frame mounted above the carrier tape. The method also involves adhering an adhesive tape to a front side of the semiconductor wafer and to at least a portion of the substrate carrier. The adhesive tape includes an opening exposing an inner region of the front side of the semiconductor wafer.

Abstract: A method of attaching a die to a substrate is disclosed. A major surface of the die has an array of electrical contacts, and is covered with a tape segment having an array of apertures in register with the contacts. Solder balls are inserted into the apertures. The die is positioned against a substrate with the solder balls in register with the die pads on the surface of the substrate, and a heat treatment process is performed to bond the conductive elements to the corresponding bond pads.

Abstract: A semiconductor device is described advantageously making use of the interposer principle. The semiconductor device comprises at least one semiconductor die, a window substrate being an inorganic substrate comprising at least one window-shaped cavity for mounting the at least one semiconductor die, the window substrate having interconnect structures. Furthermore, the at least one semiconductor die is positioned inside the at least one cavity and is connected to the interconnect structures, providing connections to another level of assembly or packaging of the semiconductor device. The invention also relates to a method of manufacturing such a semiconductor device.

Abstract: A heat dissipation adhesive film, a semiconductor device including the same, and a method of fabricating the semiconductor device, the heat dissipation adhesive film being placeable between a protective layer encasing a semiconductor element therein and a heat dissipation metal layer on the protective layer to bond the protective layer to the heat dissipation metal layer, wherein an adhesive strength between the heat dissipation adhesive film and the protective layer and an adhesive strength between the heat dissipation adhesive film and the heat dissipation metal layer are each about 3 kgf/25 mm2 or greater.

Abstract: Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.

Abstract: An insulating adhesive film is formed by laminating a first insulating adhesive layer which contains a filler in an insulating adhesive composition and a second insulating adhesive layer which contains no filler in an insulating adhesive composition. H/2<Tf<H?Tf+Tn is satisfied, wherein H is the height of the bump of the IC chip, Tf is the thickness of the first insulating adhesive layer, and the Tn is the thickness of the second insulating adhesive layer. The side of the substrate on which an electrode is formed and the side of an IC chip on which a bump is formed are connected via the insulating adhesion film arranged such that the first insulating adhesive layer and the electrode-forming side of the electronic component are opposed to thereby connect the electrode of the substrate and the bump of the IC chip.

Abstract: A semiconductor device bonded by an anisotropic conductive film, the anisotropic conductive film including a conductive adhesive layer and an insulating adhesive layer stacked thereon, an amount of reactive monomers in the conductive adhesive layer being higher than an amount of reactive monomers in the insulating adhesive layer.

Abstract: The film for back surface of flip-chip semiconductor according to the present invention is a film for back surface of flip-chip semiconductor to be formed on a back surface of a semiconductor element having been flip-chip connected onto an adherend, wherein a tensile storage elastic modulus at 23° C. after thermal curing is 10 GPa or more and not more than 50 GPa. According to the film for back surface of flip-chip semiconductor of the present invention, since it is formed on the back surface of a semiconductor element having been flip-chip connected onto an adherend, it fulfills a function to protect the semiconductor element. In addition, since the film for back surface of flip-chip semiconductor according to the present invention has a tensile storage elastic modulus at 23° C. after thermal curing of 10 GPa or more, a warp of the semiconductor element generated at the time of flip-chip connection of a semiconductor element onto an adherend can be effectively suppressed or prevented.

Abstract: A method for bonding wafers includes forming a first bonding part on a surface of a first wafer by stacking a diffusion preventing layer formed of a material having low wettability with AuSn above the first wafer and forming a bonding layer on a surface of the diffusion preventing layer such that the bonding layer stays back of an edge of the diffusion preventing layer, forming a second bonding part on a surface of a second wafer, and bonding the first bonding part and the second bonding part by eutectic bonding with an AuSn solder under a condition that the first wafer and the second wafer are opposed to each other.

Abstract: Stacked semiconductor chips include a bonding-wire-free interconnection electrically connecting the semiconductor chips to each. An opening in an adhesion layer between the semiconductor chips may provide a path for the interconnection from a bonding pad on one semiconductor chip, along a sidewall insulation layer of the semiconductor chip, along a sidewall insulation layer of another semiconductor chip to a bonding pad on the other semiconductor chip.

Abstract: There is reduced the difference in inductance between bonding wires to be coupled to two semiconductor chips stacked one over another. A semiconductor device includes external terminals, lower and upper semiconductor chips, and first and second bonding wires. The lower semiconductor chip has first bonding pads, and the upper semiconductor chip has second bonding pads. The first bonding wire couples the first bonding pad of the lower semiconductor chip and the external terminal, and the second bonding wire couples the second bonding pad of the upper semiconductor chip and the external terminal. The diameter of the second bonding wire is larger than the diameter of the first bonding wire.

Abstract: Disclosed is an adhesive composition which includes (a) an epoxy resin, (b) a curing agent and (c) a polymer compound incompatible with said epoxy resin, and further optionally includes (d) a filler and/or (e) a curing accelerator. Also disclosed are a process for producing an adhesive composition, including mixing (a) the epoxy resin and (b) the curing agent with (d) the filler, followed by mixing the resultant mixture with (c) the polymer compound incompatible with the epoxy resin; an adhesive film including the above-mentioned adhesive composition formed into a film; a substrate for mounting a semiconductor including a wiring board and the above-mentioned adhesive film disposed thereon on its side where chips are to be mounted; and a semiconductor device which includes the above-mentioned adhesive film or the substrate for mounting a semiconductor.

Abstract: A method of making a stacked semiconductor package having at least a leadframe, a first die mounted above and soldered to the lead frame and a first clip mounted above and soldered to the first die. The method includes positioning the leadframe, first die and first clip in a vertically stacked relationship and nonsolderingly locking the first clip in laterally nondisplaceble relationship with the leadframe. A stacked semiconductor package and an intermediate product produced in making a stacked semiconductor package are also disclosed.

Abstract: A device comprising a substrate, an integrated circuit (IC) die attached to the substrate on one side, a plurality of contact pads on an active side of the IC die, a plurality of thermally and electrically conductive legs, each of the legs attached to a respective one of the contact pads, and an encapsulating material formed around the substrate, the IC die, and a portion of the legs. A contact end of each of the legs is exposed, and one of the contact ends conducts a signal from a transistor in the IC die.

Abstract: A sulfonium borate complex that is capable of reducing the amount of fluorine ions generated during thermal cationic polymerization, and is capable of providing a thermal cationic polymerizable adhesive with low-temperature fast curing properties is represented by a structure represented by the formula (1). In the formula (1), R1 is an aralkyl group, R2 is a lower alkyl group, and R3 is a lower alkoxycarbonyl group. X is a halogen atom, and n is an integer of from 1 to 3.

Abstract: A method of making an electronic device includes forming an electrically conductive pattern on a substrate, forming a coverlay layer on the substrate and the electrically conductive pattern, forming a partially cured, tacky adhesive layer on the coverlay layer, and forming openings in the coverlay layer and the partially cured, tacky adhesive layer aligned with the electrically conductive pattern. The method includes positioning an IC on the partially cured, tacky adhesive layer and thereafter curing the partially cured tacky adhesive layer to thereby simultaneously mechanically secure and electrically interconnect the IC to the substrate, the IC having bond pads on a surface thereof.

Abstract: Methods of forming a Ni material on a bond pad are disclosed. The methods include forming a dielectric material over an at least one bond pad, forming an opening within the dielectric material to expose the at least one bond pad, curing the dielectric material to form a surface of the dielectric material having a steep curvilinear profile, and forming a nickel material over the at least one bond pad. The dielectric material having a steep curvilinear profile may be formed by altering at least one of a curing process of the dielectric material and a thickness of the dielectric material. The dielectric material may be used to form a relatively thick Ni material on bond pads smaller than about 50 ?m. Semiconductor structures formed by such methods are also disclosed.

Abstract: A substrate for a semiconductor package includes: a first dielectric having a first surface and a second surface which faces away from the first surface and possesses waveform shaped portions, and formed with first holes penetrating the first and second surfaces; and circuit traces formed over the second surface of the first dielectric and having waveform shaped portions disposed over the waveform shaped portions of the second surface of the first dielectric. The waveform shaped portions of the second surface of the first dielectric and the waveform shaped portions of the circuit traces form a stress-resistant structure.

Abstract: Described herein is a sealant laminated composite for collectively sealing a semiconductor device's mounting surface of a substrate on which semiconductor devices are mounted or a semiconductor device's forming surface of a wafer on which semiconductor devices are formed. The composite can include a support wafer and an uncured resin layer constituted of an uncured thermosetting resin formed on one side of the support wafer. In certain aspects, the sealant laminated composite is very versatile, even when a large diameter or thin substrate or wafer is sealed.

Abstract: This disclosure relates generally to a semiconductor device and method of making the semiconductor device by pressing an electrical contact of a chip into a bonding layer on a carrier. The bonding layer is cured and coupled, at least in part, to the electrical contact. A molding layer is applied in contact with the chip and a first major surface of the bonding layer. Distribution circuitry is coupled to the electrical contact.

Abstract: A substrate includes a die-bonding zone and a glue spreading pattern. The die-bonding zone is set to bond a die. The glue spreading pattern is placed in the die-bonding zone and includes a containing space. The die is placed on the glue spreading pattern, an area of a bottom of the die is greater than an area of an opening of the glue spreading pattern, the containing room of the glue spreading pattern is filled with a glue, and the die is bonded to the substrate by means of the glue.

Abstract: In one embodiment, a method of forming a semiconductor package comprises providing a first die having contact regions on a top surface but not on an opposite bottom surface. A dielectric liner layer is deposited under the bottom surface of the first die. The first die is attached with the deposited dielectric liner layer to a die paddle of a substrate. A bond layer is disposed between the substrate and the dielectric liner layer.

Abstract: Electronic assemblies including substrates and their manufacture are described. One assembly includes a die embedded in a dielectric layer in a multilayer substrate, and a dielectric region embedded in the dielectric layer in the multilayer substrate. The multilayer substrate includes a die side and a land side, with the first dielectric region and the dielectric layer extending to the die side. A plurality of vias are positioned within the first dielectric region, the vias extending to pads on the die side. Other embodiments are described and claimed.

Abstract: A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

Abstract: A resin composition excellent in both characteristics of preservation stability and connection reliability is provided by a resin composition that contains (a) an epoxy compound, (b) a microcapsule type hardening acceleration agent, and (c) an inorganic particle whose surface is modified with a compound that has an unsaturated double bond.

Abstract: An anisotropic conductive film includes a conductive adhesive layer including conductive particles and insulating particles, and an insulating adhesive layer not including conductive particles. In the anisotropic conductive film, the conductive particles and the insulating particles of the conductive adhesive layer have a total particle density of 7.0×105/d2 to 10.0×105/d2 (particles) per square millimeter (mm2) (where d is a diameter of the conductive particles in ?m).

Abstract: Sidewall protection processes are provided for Cu pillar bump technology, in which a protection structure on the sidewalls of the Cu pillar bump is formed of at least one of non-metal material layers, for example a dielectric material layer, a polymer material layer, or combinations thereof.

Abstract: In a semiconductor chip, a first semiconductor chip 21 is provided on a chip-mounting component 11, and bonding wires 36 connected to electrode pads 21E of the first semiconductor chip 21 are fixed by being covered with a first insulating adhesive 31. A second semiconductor chip 22 is mounted by being stacked on the first semiconductor chip 21, with the first insulating adhesive 31 therebetween. This structure can prevent problems such as breaking and short-circuits of bonding wires of the chip disposed directly on a substrate when another chip is mounted by being stacked.

Abstract: A microelectronic assembly can include first, second and third stacked substantially planar elements, e.g., of dielectric or semiconductor material, and which may have a CTE of less than 10 ppm/° C. The assembly may be a microelectronic package and may incorporate active semiconductor devices in one, two or more of the first, second or third elements to function cooperatively as a system-in-a-package. In one example, an electrically conductive element having at least a portion having a thickness less than 10 microns, may be formed by plating, and may electrically connect two or more of the first, second or third elements. The conductive element may entirely underlie a surface of another one of the substantially planar elements.

Abstract: The present invention provides a dicing tape-integrated wafer back surface protective film including: a dicing tape including a base material and a pressure-sensitive adhesive layer formed on the base material; and a wafer back surface protective film formed on the pressure-sensitive adhesive layer of the dicing tape, in which the wafer back surface protective film is colored. It is preferable that the colored wafer back surface protective film has a laser marking ability. The dicing tape-integrated wafer back surface protective film can be suitably used for a flip chip-mounted semiconductor device.

Abstract: In various embodiments, a chip arrangement is provided. The chip arrangement may include a chip carrier and a chip mounted on the chip carrier. The chip may include at least two chip contacts and an insulating adhesive between the chip and the chip carrier to adhere the chip to the chip carrier. The at least two chip contacts may be electrically coupled to the chip carrier.

Abstract: Embodiments of the present disclosure are directed to die adhesive films for integrated circuit (IC) packaging, as well as methods for forming and removing die adhesive films and package assemblies and systems incorporating such die adhesive films. A die adhesive film may be transparent to a first wavelength of light and photoreactive to a second wavelength of light. In some embodiments, the die adhesive film may be applied to a back or “inactive” side of a die, and the die surface may be detectable through the die adhesive film. The die adhesive film may be cured and/or marked with laser energy having the second wavelength of light. The die adhesive film may include a thermochromic dye and/or nanoparticles configured to provide laser mark contrast. UV laser energy may be used to remove the die adhesive film in order to expose underlying features such as TSV pads.

Abstract: A system and method for chip package fabrication is disclosed. The chip package includes a base re-distribution layer having an opening formed therein, an adhesive layer having a window formed therein free of adhesive material, and a die affixed to the base re-distribution layer by way of the adhesive layer, the die being aligned with the window such that only a perimeter of the die contacts the adhesive layer. A shield element is positioned between the base re-distribution layer and adhesive layer that is generally aligned with the opening formed in the base re-distribution layer and the window of the adhesive layer such that only a perimeter of the shield element is attached to the adhesive layer. The shield element is separated from the die by an air gap and is configured to be selectively removable from the adhesive layer so as to expose the front surface of the die.

Abstract: A semiconductor package is provided, which includes: a semiconductor substrate having opposite first and second surfaces; an adhesive layer formed on the first surface of the semiconductor substrate; at least a semiconductor chip disposed on the adhesive layer; an encapsulant formed on the adhesive layer for encapsulating the semiconductor chip; and a plurality of conductive posts penetrating the first and second surfaces of the semiconductor substrate and the adhesive layer and electrically connected to the semiconductor chip, thereby effectively reducing the fabrication cost, shortening the fabrication time and improving the product reliability.

Abstract: A package-on-package assembly includes first and second packages and an adhesion member positioned between the first and second packages and adhering the first and second packages to one another. The first package may include a first substrate having a first surface and a second surface facing each other and including a land pad formed on the first surface, a first semiconductor chip formed on the first surface, and a first encapsulant member encapsulating the first surface and the first semiconductor chip and including a through-via spaced apart from the first semiconductor chip and exposing the land pad and a trench formed between the first semiconductor chip and the through-via, and wherein at least a portion of the trench is filled with adhesion member material.

Abstract: A module substrate may include a substrate body on which a plurality of chip mounting regions having connection pads are defined. Repair structures may be respectively formed, or placed, in the chip mounting regions. Each repair structure includes conductive layer patterns formed over the connection pads in each chip mounting region, an insulation layer pattern formed over the substrate body in each chip mounting region in such a way as to expose the conductive layer patterns, plastic conductive members formed between the connection pads and the conductive layer patterns, and a plastic insulation member formed between the substrate body and the insulation layer pattern in each chip mounting region.

Abstract: A chip packaging apparatus includes a substrate, a load frame attached to the substrate by an adhesive material, the load frame being formed to define an aperture and a semiconductor chip mounted on the substrate within the aperture. A thickness of the adhesive material between the load frame and the substrate is varied and adjusted such that a surface of the load frame opposite the substrate is disposed substantially in parallel to a surface of the chip opposite the substrate.

Abstract: An optoelectronic component includes a first substrate on which are arranged an active region and a first contact region, and a first contact layer arranged in the first contact region. The second component includes a second substrate on which is arranged at least one second contact layer arranged in a second contact region. The first contact layer connects electrically conductively with the active region and additionally is bonded to the second contact layer by an adhesive layer. The adhesive layer includes an electrically conductive adhesive. The first contact layer and/or the second contact layer are patterned at least in part.

Abstract: An I/O pad structure in an integrated circuit (IC) comprises a first vertical region in the IC including a top metal layer and one or more semiconductor devices formed thereunder, the top metal layer in the first vertical region serving as a first pad, the semiconductor devices being electrically connected to the first pad, and a second vertical region in the IC next to the first vertical region including the top metal layer and one or more through-silicon-vias (TSVs) formed thereunder, the top metal layer in the second vertical region serving as a second pad, and no semiconductor devices being formed beneath the second pad, the TSVs being electrically connected to the second pad, wherein the first and the second pad are electrically connected through at least one metal layer.

Abstract: A semiconductor package includes first and second semiconductor elements electrically interconnected by a connection structure. The first and second semiconductor elements are joined by a protection structure that includes an adhesive layer surrounded by a retention layer.

Abstract: An epoxy resin composition including (A) an epoxy resin that is solid at room temperature and has a softening point of 40° C. to 110° C., (B) a curing agent that is solid at room temperature and has a softening point of not less than 40° C. to 110° C., (C) a curing accelerator, (D) an inorganic filler having a mass-average particle size of 0.05 to 5 ?m, (E) a diluent, and (F) a specific dimethyl silicone, in which at least one of the component (A) and the component (B) is silicone-modified is provided. The composition can be used in a silicon chip die attach method or to produce a semiconductor device containing a silicon chip, a substrate and a cured product of the composition, in which the silicon chip is bonded to the substrate via the cured product.

Abstract: Disclosed is a light emitting device module including a package body, a first lead frame and a second lead frame provided on the package body, a light emitting device electrically connected to the first lead frame and the second lead frame, a first pad and a second pad respectively formed on the lower surfaces of the first lead frame and the second lead frame, and a third pad formed on the lower surface of the package body, wherein at least one of the first pad, the second pad and the third pad includes a plurality of sub-pads.

Abstract: The present invention provides a dicing tape-integrated wafer back surface protective film including: a dicing tape including a base material and a pressure-sensitive adhesive layer formed on the base material; and a wafer back surface protective film formed on the pressure-sensitive adhesive layer of the dicing tape, in which the wafer back surface protective film is colored. It is preferable that the colored wafer back surface protective film has a laser marking ability. The dicing tape-integrated wafer back surface protective film can be suitably used for a flip chip-mounted semiconductor device.

Abstract: A semiconductor assembly comprises a semiconductor wafer, an adhesive coating disposed on the back side of the wafer, and a bare dicing tape, preferably UV radiation transparent. The assembly is prepared by the method comprising (a) providing a semiconductor wafer, (b) disposing a wafer back side coating on the semiconductor wafer, (c) partially curing the wafer back side coating to the extent that it adheres to the back side of the wafer and remains tacky, and (d) contacting the bare dicing tape to the partially cured and tacky wafer back side coating, optionally with heat and pressure.

Abstract: A method of making an electronic device includes forming an electrically conductive pattern on a substrate, forming a coverlay layer on the substrate and the electrically conductive pattern, forming a partially cured, tacky adhesive layer on the coverlay layer, and forming openings in the coverlay layer and the partially cured, tacky adhesive layer aligned with the electrically conductive pattern. The method includes positioning an IC on the partially cured, tacky adhesive layer and thereafter curing the partially cured tacky adhesive layer to thereby simultaneously mechanically secure and electrically interconnect the IC to the substrate, the IC having bond pads on a surface thereof.

Abstract: Thermally-induced stress on a silicon micro-electromechanical pressure transducer (MEMS sensor) is reduced by attaching the MEMS sensor to a plastic filled with low CTE fillers that lowers the plastic's coefficient of thermal expansion (CTE) to be closer to that of silicon. The MEMS sensor is attached to the housing using an epoxy adhesive/silica filler mixture, which when cured has a CTE between about ten PPM/° C. and about thirty PPM/° C. in order to match the housing CTE. The adhesive also has a glass transition temperature (Tg) above the operating temperature range. This design provides good sealing of the sensor and stable sensor outputs.