Abstract: The semiconductor device includes a wiring substrate having a plurality of ball lands formed on a lower surface of a core layer, a solder resist film covering the lower surface of the core layer, a via conductor layer penetrating the core layer and connected to the ball lands, and an upper surface wiring formed on the upper surface of the core layer, the upper surface wiring having one end formed as a bonding land and the other end connected to the via conductor layer. The semiconductor device further includes a semiconductor chip arranged on the wiring substrate, a solder ball connected to the ball lands. The solder resist film has an eliminating portion that exposes the lower surface of the core layer, and the upper surface wiring has a thin-wire portion and a thick-wire portion, and when seen in a plan view, the thick-wire portion overlaps the eliminating portion.

Abstract: The invention provides an addition-curable silicone composition which provides a cured product having good performance at a low temperature and excellent resistance to a temperature change, and to provide a semiconductor device having a high reliability, whose semiconductor element is encapsulated with the cured product. The invention provides an addition-curable silicone composition comprising (A) a branched organopolysiloxane having at least two alkenyl groups and represented by the formula (1) with a short branch consisting of 1 to 4 siloxane units, (B) an organohydrogenpolysiloxane having at least two hydrosilyl groups, in an amount such that a ratio of the number of the hydrosilyl groups in component (B) to the number of the alkenyl groups in component (A) is 0.4 to 4, and (C) a hydrosilylation catalyst in a catalytic amount. The invention also provides a semiconductor device provided with a cured product obtained by curing the condensation-curable silicone composition.

Abstract: Sintering die-attach materials provide a lead-free solution for semiconductor packages with superior electrical, thermal and mechanical performance to prior art alternatives. Wafer-applied sintering materials form a metallurgical bond to both semiconductor die and adherends as well as throughout the die-attach joint and do not remelt at the original process temperature. Application to either one or both sides of the wafer, as well as paste a film application are disclosed.

Abstract: A semiconductor device and method for encapsulating the semiconductor device are provided. The method includes: forming a plurality of wire bonds on a surface of the semiconductor device by bonding each of a plurality of copper wires onto corresponding ones of a plurality of aluminum pads; applying a protective material around the plurality of wire bonds, the protective material having a first pH; and encapsulating at least a portion of the semiconductor device and the protective material with an encapsulating material having a second pH, wherein the first pH of the protective material is for neutralizing the second pH of the encapsulating material around the plurality of wire bonds.

Abstract: Flexible structures and method of providing a flexible structure are disclosed. In some embodiments, a method of providing a flexible structure includes: providing a flex substrate having a device bonded to a first side of the flex substrate; and attaching a rigid layer to a second side of the flex substrate opposite the first side using an adhesive layer.

Abstract: According to one exemplary embodiment, a semiconductor package includes a substrate having lower and upper surfaces. The semiconductor package further includes at least one passive component coupled to first and second conductive pads on the upper surface of the substrate. The semiconductor package further includes at least one semiconductor device coupled to a first conductive pad on the lower surface of the substrate. The at least one semiconductor device has a first electrode for electrical and mechanical connection to a conductive pad external to the semiconductor package. The at least one semiconductor device can have a second electrode electrically and mechanically coupled to the first conductive pad on the lower surface of the substrate.

Abstract: A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package.

Abstract: A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.

Abstract: A wafer processing laminate is provided comprising a support, a temporary adhesive layer on the support, and a wafer laid on the temporary adhesive layer. The temporary adhesive layer has a trilayer structure consisting of a first bond layer (A) of thermoplastic organosiloxane polymer which is releasably bonded to the circuit-forming front surface of the wafer, a second bond layer (B) of thermosetting modified siloxane polymer which is laid on the first bond layer, and a third bond layer (A?) of thermoplastic organosiloxane polymer which is laid on the second bond layer and releasably bonded to the support.

Abstract: A chip-on-film package comprises a film substrate comprising upper and lower surfaces, and a side having a bending part. A first output interconnection formed on the upper surface of the film substrate extends from a semiconductor chip disposed on the upper surface toward the bending part. A second output interconnection includes an upper output interconnection formed on the upper surface of the film substrate, and a lower output interconnection formed on the lower surface and extending onto the bending part. An input interconnection includes an upper input interconnection formed on the upper surface of the film substrate and a lower input interconnection formed on the lower surface and extending away from the bending part. Through-vias are formed to pass through the film substrate and electrically connect the upper output interconnection to the lower output interconnection, and the upper input interconnection to the lower input interconnection.

Abstract: A preassembly semiconductor device comprises chip soldering structures on a semiconductor chip and substrate soldering structures on a substrate corresponding to the chip soldering structures. The substrate soldering structures extend toward the chip soldering structures for forming solder connections with the chip soldering structures. The chip and the substrate are in preassembly positions relative to one another. The height of the substrate soldering structures is greater than the height of the chip soldering structures. A pre-applied underfill is contiguous with the substrate and is sufficiently thick so as to extend substantially no further than the full height of the substrate soldering structures.

Abstract: In a method of manufacturing a semiconductor device, a first semiconductor element is mounted on a carrier. A b-stage curable polymer is deposited on the carrier. A second semiconductor element is affixed on the polymer.

Abstract: A semiconductor package structure, comprises a substrate, a die region having one or more dies disposed on the substrate, and at least one stress relief structure disposed at one or more corners of the substrate, the at least one stress relief structure being adjacent to at least one die of the one or more dies.

Abstract: An installation card for a smart SIM Overlay and an installation method using the same are provided. The installation card comprises a carrier plate, a first adhesive layer, a smart overlay and a second adhesive layer. The carrier plate has a notch and a surface. The first adhesive layer adheres to the surface of the carrier plate. The smart overlay is adheres to the first adhesive layer, and the smart overlay is positioned corresponding to the notch. The second adhesive layer is adhered to the smart overlay.

Abstract: An electrode for a spark plug includes an electrode base material and a noble metal element, the noble metal element being fastened to the electrode base material using a welding connection. The welding connection has a maximum extension perpendicular to an area of the electrode at which the noble metal element is fastened, and the welding connection has a maximum width at the area. A ratio of the maximum extension to the maximum width is greater than, or equal to 3.

Abstract: The present invention relates to die-die stacking structure and the method for making the same. The die-die stacking structure comprises a top die having a bottom surface, a first insulation layer covering the bottom surface of the top die, a bottom die having a top surface, a second insulation layer covering the top surface of the bottom die, a plurality of connection members between the top die and the bottom die and a protection material between the first insulation layer and the second insulation layer. The plurality of connection members communicates the top die with the bottom die. The protection material bridges the plurality of connection members to form a mesh layout between the first insulation layer and the second insulation layer.

Abstract: A system for bonding a die to a high power dielectric carrier such as a ceramic dielectric core with double-sided conductive layers is described. In the system, the upper conductive layer has a first area whose surface has a first wettability. A second area that at least partially surrounds the first area has a surface with a second wettability that is greater than the first wettability. During bonding, an adhesive material bonding a chip to the substrate spreads among the first area by a downward force placed on the chip. Due to the difference in wettability, the adhesive material then spreads among the second area by a wetting force generated by the greater second wettability of the second area surface causing the chip to be drawn down until reaching a predetermined position. The predetermined position can be determined by substrate protrusions or substrate cavities.

Abstract: The connection arrangement (100, 200, 300, 400) comprises at least one electric and/or electronic component (1). The at least one electric and/or electronic component (10) has at least one connection face (11), which is connected in a bonded manner to a join partner (40) by means of a connection layer (20). The connection layer (20) can for example be an adhesive, soldered, welded, sintered connection or another known connection that connects joining partners while forming a material connection. Furthermore, a reinforcement layer (30?) is arranged adjacent to the connection layer (20) in a bonded manner. The reinforcement layer (30?) has a higher modulus of elasticity than the connection layer (20). A particularly good protective effect is achieved if the reinforcement layer (30?) is formed in a frame-like manner by an outer and an inner boundary (36, 35) and, at least with the outer boundary (36) thereof, encloses the connection face (11) of the at least one electric and/or electronic component (10).

Abstract: A method of manufacturing a semiconductor device includes attaching a curable film to a first connection member including a first circuit terminal, attaching a conductive film to a second connection member including a second circuit terminal, and thermally compressing the first connection member to the second connection member, with the first connection member and the second connection member placed such that the curable film and the conductive film face each other.

Abstract: A method of manufacturing a chip package is provided. The method may include electrically contacting at least one first chip, the first chip including a first side and a second side opposite the first side, with its second side to an electrically conductive carrier. An insulating layer is formed over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip. At least one second chip is arranged over the insulating layer. An encapsulating material is formed over the first chip and the second chip. Electrical contacts are formed through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip.

Abstract: A junction at which at least two conductors are connected together includes a compound region containing Cu, Sn and at least one element selected from the group consisting of Si, B, Ti, Al, Ag, Bi, In, Sb, Ga and Zn. The compound region forms a nanocomposite metal diffusion region with the conductor.

Abstract: A method of forming an assembly of a substrate and a flip-chip having solder balls thereon, the method having steps of: placing the flip chip with the solder balls in contact with the substrate to form a first interim assembly at a first predetermined temperature; providing an encapsulant to the first interim assembly to form a second interim assembly at a second predetermined temperature that is lower than a melting temperature of the solder balls and higher than the first predetermined temperature; and subjecting the second interim assembly to an environment of a third predetermined temperature that is sufficient to melt the solder balls. An encapsulant for use in forming an assembly of a substrate and a flip-chip having solder balls thereon, the encapsulant consisting essentially of: an epoxy resin; an anhydride curing agent; a fluxing agent having a hydroxyl (—OH) group; and an inorganic filler.

Abstract: An integrated circuit package system that includes: providing a substrate with a protective coating; attaching a labeling film to a support member in a separate process; joining the protective coating and the labeling film; and dicing the substrate, the protective coating, and the labeling film to form the integrated circuit package system.

Abstract: In various embodiments, a chip arrangement is provided. The chip arrangement may include a chip carrier and a chip mounted on the chip carrier. The chip may include at least two chip contacts and an insulating adhesive between the chip and the chip carrier to adhere the chip to the chip carrier. The at least two chip contacts may be electrically coupled to the chip carrier.

Abstract: In one embodiment, a semiconductor component, such as a wavelength converter wafer, is described wherein the wavelength converter is bonded to an adjacent inorganic component with a cured bonding layer comprising polysilazane polymer. The wavelength converter may be a multilayer semiconductor wavelength converter or an inorganic matrix comprising embedded phosphor particles. In another embodiment, the semiconductor component is a pump LED component bonded to an adjacent component with a cured bonding layer comprising polysilazane polymer. The adjacent component may the described wavelength converter(s) or another component comprised of inorganic material(s) such as a lens or a prism. Also described are methods of making semiconductor components such as wavelength converters and LED's.

Abstract: Flip chip packages are described that include two or more thermal interface materials (TIMs). A die is mounted to a substrate by solder bumps. A first TIM is applied to the die, and has a first thermal resistance. A second TIM is applied to the die and/or the substrate, and has a second thermal resistance that is greater than the first thermal resistance. An open end of a heat spreader lid is mounted to the substrate such that the die is positioned in an enclosure formed by the heat spreader lid and substrate. The first TIM and the second TIM are each in contact with an inner surface of the heat spreader lid. A ring-shaped stiffener may surround the die and be connected between the substrate and heat spreader lid by the second TIM.

Abstract: A semiconductor device has a flipchip or PoP semiconductor die mounted to a die attach area interior to a substrate. The substrate has a contact pad area around the die attach area and flow control area between the die attach area and contact pad area. A first channel is formed in a surface of the substrate within the flow control area. The first channel extends around a periphery of the die attach area. A first dam material is formed adjacent to the first channel within the flow control area. An underfill material is deposited between the die and substrate. The first channel and first dam material control outward flow of the underfill material to prevent excess underfill material from covering the contact pad area. A second channel can be formed adjacent to the first dam material. A second dam material can be formed adjacent to the first channel.

Abstract: Provided is a semiconductor device, including an anisotropic conductive film connecting the semiconductor device, the anisotropic conductive film having a maximum stress of 0.4 kgf/mm2 or more; and a stress-strain curve having a slope (A) of greater than 0 and less than or equal to 0.2 kgf/(mm2·%) as represented by the following equation 1: slope(A)=(½Smax?S0)/x??(1), wherein: Smax=maximum stress, x=strain (%) at half (½) of the maximum stress, and S0=stress at a strain of 0.

Abstract: A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.

Abstract: According to various embodiments, a wafer arrangement may be provided, the wafer arrangement may include: a wafer including at least one electronic component having at least one electronic contact exposed on a surface of the wafer; an adhesive layer structure disposed over the surface of the wafer, the adhesive layer structure covering the at least one electronic contact; and a carrier adhered to the wafer via the adhesive layer structure, wherein the carrier may include a contact structure at a surface of the carrier aligned with the at least one electronic contact so that by pressing the wafer in direction of the carrier, the contact structure can be brought into electrical contact with the at least one electronic contact of the at least one electronic component.

Abstract: A semiconductor device includes: a substrate; first and second pads disposed adjacent to each other on the substrate; an electrically conductive tape adhered to the first and second pads and having a through hole at an inner portion of the first pad; an electrically conductive adhesive in the through hole and having a thermal conductivity higher than the thermal conductivity of the electrically conductive tape; a semiconductor chip mounted on the first pad via the electrically conductive adhesive; and an electronic component part mounted on the second pad via the electrically conductive tape.

Abstract: A semiconductor package, wherein, in bonding of members constituting the semiconductor package, by using bonding layers containing copper and a low-melting-point metal such as tin, the bonding is performed in a temperature range where the occurrence of warpage or distortion of the members is suppressed, and after the bonding, a high melting point is obtained; and by configuring the members so that all the surfaces of the members which become bonding surfaces of bonding layers are parallel to each other, all the thickness directions of the bonding layers are aligned to be in the same direction, and during the formation of the bonding layers, the pressing direction is set to be one-way direction which is the direction of laminating the members.

Abstract: Articles containing a matrix material and plurality of copper nanoparticles in the matrix material that have been at least partially fused together are described. The copper nanoparticles are less than about 20 nm in size. Copper nanoparticles of this size become fused together at temperatures and pressures that are much lower than that of bulk copper. In general, the fusion temperatures decrease with increasing applied pressure and lowering of the size of the copper nanoparticles. The size of the copper nanoparticles can be varied by adjusting reaction conditions including, for example, surfactant systems, addition rates, and temperatures. Copper nanoparticles that have been at least partially fused together can form a thermally conductive percolation pathway in the matrix material.

Abstract: Methods of forming a semiconductor structure include exposing a carrier substrate to a silane material to form a coating, removing a portion of the coating at least adjacent a periphery of the carrier substrate, adhesively bonding another substrate to the carrier substrate, and separating the another substrate from the carrier substrate. The silane material includes a compound having a structure of (XO)3Si(CH2)nY, (XO)2Si((CH2)nY)2, or (XO)3Si(CH2)nY(CH2)nSi(XO)3, wherein XO is a hydrolyzable alkoxy group, Y is an organofunctional group, and n is a nonnegative integer. Some methods include forming a polymeric material comprising Si—O—Si over a first substrate, removing a portion of the polymeric material, and adhesively bonding another substrate to the first substrate.

Abstract: A package system includes a first substrate and a second substrate. The second substrate is electrically coupled with the first substrate. The second substrate includes at least one first opening. At least one electrical bonding material is disposed between the first substrate and the second substrate. A first portion of the at least one electrical bonding material is at least partially filled in the at least one first opening.

Abstract: A method of attaching a die to a substrate is disclosed. A major surface of the die has an array of electrical contacts, and is covered with a tape segment having an array of apertures in register with the contacts. Solder balls are inserted into the apertures. The die is positioned against a substrate with the solder balls in register with the die pads on the surface of the substrate, and a heat treatment process is performed to bond the conductive elements to the corresponding bond pads.

Abstract: A wafer substrate bonding structure may be provided that includes: a first substrate; and a conductive thin film which is disposed on the first substrate and includes a resin and conductive corpuscles included in the resin.

Abstract: In accordance with certain embodiments, semiconductor dies are at least partially coated with a conductive adhesive prior to singulation and subsequently bonded to a substrate having electrical traces thereon.

Abstract: A semiconductor package includes a first structural body having a first surface and a second surface which faces away from the first surface, and formed with first connection members on the first surface; a second structural body placed over the first structural body, and formed with second connection members on a surface thereof which faces the first surface of the first structural body; and an interposer interposed between the first structural body and the second structural body, and having a body which is formed with openings into which the first connection members and the second connection members are inserted and a conductive layer which is formed to fill the openings.

Abstract: The present invention includes a temporary fixing step of temporarily fixing a semiconductor element on an adherend interposing an adhesive sheet therebetween, a wire-bonding step of bonding wires to the semiconductor element, and a step of sealing the semiconductor element with a sealing resin, and in which the loss elastic modulus of the adhesive sheet at 175-C is 2000 Pa or more.

Abstract: Provided is a stress-relieving, second-level interconnect structure that is low-cost and accommodates thermal coefficient of expansion (TCE) mismatch between low-TCE packages and printed circuit boards (PCBs). The interconnect structure comprises at least a first pad, a supporting pillar, and a solder bump, wherein the first pad and supporting pillar are operative to absorb substantially all plastic strain, thereby enhancing compliance between the two electronic components.

Abstract: A module having multiple die includes a first die on a first substrate and an inverted second package stacked over the first die, with, where necessary, provision is made for a standoff between the second package and the first die. Also, methods for making the module include steps of providing a first package having a first die attached onto an upward facing side of a first package substrate, and stacking an inverted second package over the die on the first package, provision being made where necessary for a standoff between the second package and the first package die to avoid damaging impact between the downward-facing side of the second package and wire bonds connecting the first die to the first package substrate.

Abstract: A semiconductor device includes an electrode including a plurality of pillars, a semiconductor element configured to be electrically-connected with the electrode, a substrate having electrode patterns, and a conductive adhesive layer located between the substrate and the electrode, the conductive adhesive layer including conductive substances configured to electrically-connect the pillars and the electrode patterns to each other, and including a body which encloses the conductive substances.

Abstract: A packaged semiconductor device may include a leadframe and a die carrier mounted to the leadframe. The die carrier is formed from an electrically and thermally conductive material. A die is mounted to a surface of the die carrier with die attach material having a melting point in excess of 240° C. A first electrical interconnect couples the die and the leadframe. A housing covers portions of the leadframe, die carrier, die and first electrical interconnect.

Abstract: A PoP (package-on-package) package includes a bottom package coupled to a top package. Terminals on the top of the bottom package are coupled to terminals on the bottom of the top package with an electrically insulating material located between the upper surface of the bottom package and the lower surface of the top package. The bottom package and the top package are coupled during a process that applies force to bring the packages together while heating the packages.

Abstract: A semiconductor wafer assembly formed by bonding a support wafer to a thin wafer using a double-sided bonding release tape. The support wafer provides support for the thin target wafer such that existing handling tools can accommodate transporting and processing the assembly without compromising the profile of the thin target wafer.

Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.

Abstract: A packaging system for preventing underfill overflow includes a package substrate having a solder mask a die attach site, a solder mask dam on the solder mask proximal to the die attach site, and a trench in the solder mask proximal to the die attach site. The trench and the solder mask dam are adapted to constrain flow of an underfill material.

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A first conductive layer having first and second segments is formed over a surface of the substrate with a first vent separating an end of the first segment and the second segment and a second vent separating an end of the second segment and the first segment. A second conductive layer is formed over the surface of the substrate to electrically connect the first segment and second segment. The thickness of the second conductive layer can be less than a thickness of the first conductive layer to form the first vent and second vent. The semiconductor die is mounted to the substrate with the bumps aligned to the first segment and second segment. Bump material from reflow of the bumps is channeled into the first vent and second vent.

Abstract: A stacked microelectronic assembly includes a dielectric element and a first and second microelectronic element stacked one on top of the other with the first microelectronic element underlying at least a portion of the second microelectronic element. The first microelectronic element and the second microelectronic element have front surfaces on which exposed on a central region of the front surface are contacts. A spacer layer may be provided under a portion of the second microelectronic element opposite a portion of the second microelectronic element overlying the first microelectronic element. Additionally, a third microelectronic element may be substituted in for the spacer layer so that the first microelectronic element and the third microelectronic element are underlying opposing sides of the second microelectronic element.