Abstract: According to the present invention, an epoxy resin composition for semiconductor encapsulant including (A) an epoxy resin, (B) a curing agent, (C) an inorganic filler, and (D) a compound in which a copolymer of a 1-alkene having 5 to 80 carbon atoms and maleic anhydride is esterified with an alcohol having 5 to 25 carbon atoms in the presence of a compound represented by General Formula (1), wherein R1 in General Formula (1) is selected from the group consisting of an alkyl group having 1 to 5 carbon atoms, a halogenated alkyl group having 1 to 5 carbon atoms, and an aromatic group having 6 to 10 carbon atoms is provided.

Abstract: An embodiment is directed to a polysiloxane having a moiety represented by the following Chemical Formula 1: *—Si-AR—Si—*??[Chemical Formula 1] wherein, in the Chemical Formula 1, AR is or includes a substituted or unsubstituted C6 to C30 arylene group.

Abstract: A device in accordance with one embodiment comprises component (1) and an encapsulation arrangement (2) for the encapsulation of the component (1) with respect to moisture and/or oxygen, wherein the encapsulation arrangement (2) has a first layer (21) and thereabove a second layer (22) on at least one surface (19) of the component (1), the first layer (21) and the second layer (22) each comprise an inorganic material, and the second layer (22) is arranged directly on the first layer (21).

Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The method includes: stacking and adhering a second semiconductor chip on a first semiconductor chip via an adhesive layer; adjusting at least one of an elasticity modulus of the adhesive layer, a sink amount of the adhesive layer, a thickness of a protective film at a surface of the first chip, and an elasticity modulus of the protective film such that “y” in a following formula is 70 or less; and sealing the chips by a molding resin with filler particles. y=74.7?82.7a1+273.2a2?9882a3+65.8a4 a1: a logarithm of the modulus of elasticity [MPa] of the adhesive layer a2: the sink amount [mm] of the adhesive layer a3: the thickness [mm] of the protective film a4: a logarithm of the modulus of elasticity [MPa] of the protective film.

Abstract: A multichip module has a substrate, which receives several flip chip and for other semiconductor die on one surface and has vias extending through the substrate from the flip chip bottom electrodes to solder ball electrodes on the bottom of the substrate. Passive components are also mounted on the top of the substrate and are connected to further vias which extend to respective ball contacts at the substrate bottom. In one embodiment, the bottom surfaces and electrodes of the die are insulated and their tops (and drain electrodes) are connected by a moldable conductive layer. In another embodiment the top surface of the substrate is covered by an insulation cap, which may be finned for improved thermal properties. The passives are upended to have their longest dimension perpendicular to the substrate surface and are between the fin valleys.

Abstract: A semiconductor device includes a carrier and a first chip attached to the carrier. The semiconductor device includes a sintered insulation material over at least a portion of the carrier and the first chip.

Abstract: A resin composition containing a silica-based filler which differs in refractive index by ±0.03 from the curable base resin and has a thermal conductivity no lower than 0.5 W/m·K, and a light-emitting diode encapsulated with said resin composition. The resin composition is preferably prepared from a curable silicone resin which imparts a cured product having a refractive index of 1.45 to 1.55 and cristobalite powder dispersed therein.

Abstract: A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip.

Abstract: A semiconductor device includes (i) a tape base material, (ii) a wiring pattern, (iii) a semiconductor element which is electrically connected with the wiring pattern, (iv) a top-side insulating protective film which covers a top surface of the tape base material and has an top-side opening section provided in a region where the top-side insulating protective film faces the semiconductor element, and (v) a reverse-side insulating protective film which covers a reverse surface of the tape base material and has a reverse-side opening section provided on a reverse side below the top-side opening section. The top-side insulating protective film has a protruding opening section extending outwardly from the region. An opening of the reverse-side opening section is 1.00 time to 8.50 times larger in an area than the region.

Abstract: A semiconductor encapsulation material which exhibits a low viscosity and further improved moldability in encapsulation even when highly loaded with an inorganic filler; an amorphous siliceous powder suitable for the preparation of a resin composition useful as the encapsulation material; and a process for the production of the amorphous siliceous powder. An amorphous siliceous powder having a content of Si and Al of 99.5 mass % or above in terms of oxides, wherein the Al content in the particle size region of 15 ?m to less than 70 ?m is 100 to 30000 ppm in terms of oxides; the Al content in the particle size region of 3 ?m to less than 15 ?m is 100 to 7000 ppm in terms of oxides; and the Al content in the whole particle size region is 100 to 25000 ppm in terms of oxides. It is preferable that the (A)/(B) ratio of the Al content (A) in the particle size region of 15 ?m to less than 70 ?m to the Al content (B) in the particle size region of 3 ?m to less than 15 ?m be 1.0 to 20.

Abstract: A manufacturing technique for constructing passive electronic components in vertical configurations is disclosed. Electrically passive components are constructed in a structure that is substantially perpendicular to target platform including a first plane to provide a larger electrode contact area and a smaller physical dimension. Passive components structured to be substantially perpendicular to a plane associated with a target platform can be directly connected to pad contacts of an integrated circuit or substrate or can be embedded in a package to reduce the area overhead of a passive component while improving the effectiveness of the passive components in their applications.

Abstract: The present invention relates to techniques including a phenolic oligomer of general formula (1): wherein n is an integer of 0 to 15, Rs are allyl groups, a1 and a3 are each independently 0, 1, 2 or 3, each a2 is independently 0, 1 or 2, each R? is independently a hydrogen atom, an alkyl group having 1 to 10 carbon atoms or an aryl group, and proviso that at least one of a1, each a2 and a3 represents 2, and a method for producing such phenolic oligomer.

Abstract: A method for producing a semiconductor chip laminate, which comprises applying an adhesive to a substrate or other semiconductor chip; laminating the semiconductor chip on the substrate or other semiconductor chip via the adhesive; uniformly wetting and spreading the adhesive on an entire region for bonding the semiconductor chip on the substrate or other semiconductor chip; and curing the adhesive. In the application step, an area for applying adhesive is 40% to 90% of the region for bonding the semiconductor chip located on the substrate or other semiconductor chip, immediately after laminating, an area with the adhesive thereon is 60% to less than 100% of the region for bonding the semiconductor chip on the substrate or other semiconductor chip, and in wetting and spreading the adhesive, a viscosity of adhesive between the substrate or other semiconductor chips and the semiconductor chip at 0.5 rpm is 1 Pas to 30 Pas.

Abstract: The present invention provides a semiconductor device which is not easily damaged by external local pressure. The present invention further provides a method for manufacturing a highly-reliable semiconductor device, which is not destructed by external local pressure, with a high yield. A structure body, in which high-strength fiber of an organic compound or an inorganic compound is impregnated with an organic resin, is provided over an element layer having a semiconductor element formed using a non-single crystal semiconductor layer, and heating and pressure bonding are performed, whereby a semiconductor device is manufactured, to which the element layer and the structure body in which the high-strength fiber of an organic compound or an inorganic compound is impregnated with the organic resin are firmly fixed together.

Abstract: A composite material including an arrangement of approximately aligned nanofilaments overlying at least another arrangement of approximately aligned nanofilaments, the longitudinal axis of the nanotubes of the first arrangement being approximately perpendicular to the longitudinal axis of the nanotubes of the other arrangement, and the arrangements forming at least one array. A resin material having nanoparticles dispersed throughout is disposed among the array(s) of nanofilaments, and cured, and openings may be formed into or through the composite material corresponding to spaces provided in the array of nanofilaments. A composite material according to embodiments forms a microelectronic substrate or some portion thereof, such as a substrate core.

Abstract: Disclosed is a resin composition for encapsulating a semiconductor containing a curing agent, an epoxy resin (B) and an inorganic filler (C), wherein the curing agent is a phenol resin (A) having a predetermined structure. Also disclosed is a semiconductor device obtained by encapsulating a semiconductor element with a cured product of the resin composition for encapsulating a semiconductor.

Abstract: A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-dis

Abstract: An insulating member of the invention can include an epoxy resin, a first inorganic filler diffused in the epoxy resin and having an average particle diameter of 1 to 99 nm, and a second inorganic filler diffused in the epoxy resin and having an average particle diameter of 0.1 to 100 ?m. The first and second inorganic fillers can be independent of each other, and can be selected from a group including Al2O3, SiO2, BN, AlN, and Si3N4, and the blending ratios of the first and second inorganic fillers in the insulating member can be 0.1 to 7% by weight and 80 to 95% by weight respectively. A metal base substrate can be formed by forming a metal foil and a metal base on either surface of the insulating member.

Abstract: In one embodiment, a flip chip LED is formed with a high density of gold posts extending from a bottom surface of its n-layer and p-layer. The gold posts are bonded to submount electrodes. An underfill material is then molded to fill the voids between the bottom of the LED and the submount. The underfill comprises a silicone molding compound base and about 70-80%, by weight, alumina (or other suitable material). Alumina has a thermal conductance that is about 25 times better than that of the typical silicone underfill, which is mostly silica. The alumina is a white powder. The underfill may also contain about 5-10%, by weight, TiO2 to increase the reflectivity. LED light is reflected upward by the reflective underfill, and the underfill efficiently conducts heat to the submount. The underfill also randomizes the light scattering, improving light extraction. The distributed gold posts and underfill support the LED layers during a growth substrate lift-off process.

Abstract: A functional particle (100) contains an inorganic particle (101), a first layer (103) coating the inorganic particle (101), and a second layer (105) coating the first layer (103). Any one or two component(s) of a resin, a curing agent and a curing accelerator is (are) contained in the first layer (103), and the others are (is) contained in the second layer (105).

Abstract: A resin composition for obtaining a cured resin material exhibiting improved heat resistance and a higher glass transition temperature is disclosed. The resin composition contains a resin selected from a) a thermosetting resin and a curing agent, or b) a thermoplastic resin, and an inorganic filler with an average particle diameter of 1000 nm or less.

Abstract: The present invention relates to an epoxy resin composition for semiconductor encapsulation, including the following ingredients A to E: A: an epoxy resin; B: a silicone mixture containing the following ingredients b1 and b2, with a weight ratio of the ingredients b1 and b2 being from 5/95 to 25/75 in terms of b1/b2: b1: a silicone compound having an amino group in both ends thereof and having a weight average molecular weight of from 600 to 900, and b2: a silicone compound having an amino group in both ends thereof and having a weight average molecular weight of from 10,000 to 20,000; C: a phenol resin; D: a curing accelerator; and E: an inorganic filler containing the following ingredients e1 and e2: e1: a crystalline silica, and e2: a fused silica.

Abstract: A structure for encapsulating at least one electronic device, including at least one first cavity bounded by a support and at least one cap provided on the support and wherein the electronic device is encapsulated, at least one aperture passing through the cap and communicating the inside of the first cavity with at least one portion of getter material provided in at least one second cavity which is arranged on the support and adjacent to the first cavity, at least one part of said portion of getter material being provided on the support or against at least one outer side wall of the first cavity, the first cavity and the second cavity forming together a hermetically sealed volume.

Abstract: A flexible barrier film has a thickness of from greater than zero to less than 5,000 nanometers and a water vapor transmission rate of no more than 1×10?2 g/m2/day at 22° C. and 47% relative humidity. The flexible barrier film is formed from a composition, which comprises a multi-functional acrylate. The composition further comprises the reaction product of an alkoxy-functional organometallic compound and an alkoxy-functional organosilicon compound. A method of forming the flexible barrier film includes the steps of disposing the composition on a substrate and curing the composition to form the flexible barrier film. The flexible barrier film may be utilized in organic electronic devices.

Abstract: A method of manufacturing a filling of a gap region. The method includes the steps of: applying a carrier fluid and filler particles in a gap region between a first surface and a second surface; exposing the filler particles to a force field for driving the filler particles towards a preferred direction; and withholding the filler particles in a gap region by using a barrier element for forming a path of attached filler particles between the first surface and the second surface.

Abstract: Embodiments disclosed herein generally include methods of sealing a cavity in a device structure. The cavity may be opened by etching away sacrificial material that may define the cavity volume. Material from below the cavity may be sputter etched and redeposited over and in passageways leading to the cavity to thereby seal the cavity. Material may be sputter etched from above the cavity and redeposited in the passageways leading to the cavity as well. The sputter etching may occur in a substantially inert atmosphere. As the sputter etching is a physical process, little or no sputter etched material will redeposit within the cavity itself. The inert gases may sweep out any residual gases that may be present in the cavity after the cavity has been opened. Thus, after the sputter etching, the cavity may be substantially filled with inert gases that do not negatively impact the cavity.

Abstract: In order to easily inject underfill resin and perform molding with reliability, groove sections are formed on a surface of a circuit board such that the ends of the groove sections extend to semiconductor elements. Low-viscosity underfill resin applied dropwise is guided by the groove sections and flows between the circuit board and the semiconductor elements. The underfill resin hardly expands to regions outside the semiconductor elements.

Abstract: Apparatus for assembling a semiconductor device has a plate with body and a surface heatable to a controlled a temperature profile from location to location across the plate. Mesas at same temperature of plate protrude from the surface are configured to support a portion of the substrate. Movable capillaries have openings for blowing cooled gas onto selected locations of the assembly. At least one movable syringe movable has an opening for dispensing a polymer precursor.

Abstract: Disclosed is a resin composition for semiconductor encapsulation, containing an epoxy resin (A), a curing agent (B), and an inorganic filler material (C), the epoxy resin (A) including an epoxy resin (A-1) represented by formula (1), and the epoxy resin (A-1) containing a component represented by the formula (1) in which n?1, and a component (a1) represented by the formula (1) in which n=0 (wherein in the formula (1), R1 represents a hydrocarbon group having 1 to 6 carbon atoms; R2 represents a hydrocarbon group having 1 to 6 carbon atoms, or an aromatic hydrocarbon group having 6 to 14 carbon atoms, while R1s and R2s may be respectively identical with or different from each other; a represents an integer from 0 to 4; b represents an integer from 0 to 4; and n represents an integer of 0 or larger).

Abstract: A thermally enhanced electronic package comprises a chip, a substrate, an adhesive, and an encapsulation. The adhesive or the encapsulation is mixed with carbon nanocapsules. The substrate includes an insulation layer and a wiring layer formed on the substrate. The adhesive covers the chip and the substrate. The chip is electrically connected to the wiring layer. The encapsulation covers the chip and the substrate.

Abstract: A semiconductor device includes: a semiconductor chip mounted on a mounting substrate; a first resin filling a gap between the chip and the substrate; a frame-shaped stiffener surrounding the chip; a first adhesive for bonding the stiffener to the substrate; a lid for covering the stiffener and an area surrounded by the stiffener; and a second resin filling a space between the stiffener and the chip. A thermal expansion coefficient of the second resin is smaller than that of the first resin. The first resin includes an underfill part filling a gap between the chip and the substrate and a fillet part extended from the chip region.

Abstract: Disclosed herein is a light emitting device, which includes a first substrate, a protective layer, a second substrate, a buffer member and a sealant. The first substrate has an illuminating member thereon. The protective layer covers the illuminating member and has a first coefficient of thermal expansion. The second substrate is disposed over the protective layer. The buffer member is disposed between the first and second substrates and surrounds the protective layer, wherein the buffer member has a second coefficient of thermal expansion which is less than the first coefficient. The sealant surrounds the buffer member and seals off the space between the first and second substrates, wherein the sealant has a third coefficient of thermal expansion which is less than the second coefficient.

Abstract: An integrated circuit is attached to a package substrate. The integrated circuit is electrically connected to the package substrate using a plurality of bond wires connected between a plurality of bond posts and a plurality of bond pads. A first plurality of the bond pads are along a first side of the integrated circuit and coupled to a first plurality of the bond posts with a first plurality of the bond wires. A second plurality of the bond pads are along a second side of the integrated circuit and coupled to a second plurality of the bond posts with a second plurality of the bond wires. Mold compound is injected through a plurality of openings in the package substrate. A first opening is between the first plurality of bond posts and the first side. A second opening is between the second plurality of bond posts and the second side.

Abstract: This invention relates to curable sealants that provide low moisture permeability and good adhesive strength after cure. The composition comprises an aromatic compound having meta-substituted reactive groups and a cationic or radical initiator.

Abstract: An electroconductive bonding material contains a thermosetting resin, a low-melting-point metal powder which is melted at a temperature equal to or lower than the thermosetting temperature of the thermosetting resin, a high-melting-point metal powder which is not melted at a temperature equal to or lower than the thermosetting temperature of the thermosetting resin and which reacts with the low-melting-point metal powder to form a reaction product having a high melting point of 300° C. or higher during heat-hardening of the thermosetting resin, and a reducing substance which removes an oxide formed on the surface of the high-melting-point metal powder. The total content of the low-melting-point metal powder and the high-melting-point metal powder is 75% to 88% by weight, and the particle size ratio D1/D2 of the average particle size D1 of the low-melting-point metal powder to the average particle size D2 of the high-melting-point metal powder is 0.5 to 6.0.

Abstract: A composite material including an arrangement of approximately aligned nanofilaments overlying at least another arrangement of approximately aligned nanofilaments, the longitudinal axis of the nanotubes of the first arrangement being approximately perpendicular to the longitudinal axis of the nanotubes of the other arrangement, and the arrangements forming at least one array. A resin material having nanoparticles dispersed throughout is disposed among the array(s) of nanofilaments, and cured, and openings may be formed into or through the composite material corresponding to spaces provided in the array of nanofilaments. A composite material according to embodiments forms a microelectronic substrate or some portion thereof, such as a substrate core.

Abstract: A protection layer is coated or otherwise formed over the interconnect structure. The interconnect structure includes a metal line (such as top and bottom metal layers connected by a metal via) and a low-K material. The protection layer includes a vertically aligned dielectric or other material dispersed with carbon nanotubes. The protection layer could include one or multiple layers of carbon nanotubes, and the carbon nanotubes could have any suitable dispersion, alignment, and pattern in each layer of the protection layer. Among other things, the carbon nanotubes help to reduce or prevent damage to the interconnect structure, such as by reducing or preventing the collapse of the low-K material or delamination between the metal line and the low-K material.

Abstract: This invention is a semiconductor wafer having an active side and a back side opposite the active side, which back side is coated with a filled, spin-coatable coating, wherein the coating comprises a resin and a spherical filler characterized by an average particle diameter of greater than 2 ?m and a single peak particle size distribution. In another embodiment the invention is a method for producing a spin-coatable, B-stageable coating with a thixotropic index of 1.2 or less. In a third embodiment the invention is a method for producing a coated semiconductor wafer.

Abstract: The extent of a bow of a semiconductor device is suppressed in a case where the fillet width of an underfill resin is asymmetrical. The center position 12 of a chip 1 is caused to deviate from the center position 13 of a wiring substrate 2 in a direction (the direction of the arrow B) reverse to the deviation direction (the direction of the arrow A) of the center position 11 of an underfill resin 4 from the center position 12 of the chip 1. The center position 14 of a resin for encapsulation 6 is caused to deviate from the center position 13 of the wiring substrate 2 in the same direction (the direction of the arrow A) as the deviation direction (the direction of the arrow A) of the center position 11 of the underfill resin 4 from the center position 12 of the chip 1.

Abstract: The present invention discloses a flip-chip semiconductor package and a chip carrier thereof. The chip carrier includes a groove formed around a chip-mounting area. The groove may be formed along a periphery of the chip-mounting area or at corners thereof. The groove is filled with a filler of low Young's modulus so as to absorb and eliminate thermal stress, thereby preventing delamination between an underfill and a flip chip mounted on the chip-mounting area.

Abstract: A resin composition for encapsulation, which contains 100 parts by weight of a synthetic resin, 10 to 500 parts by weight of a carbon precursor having a volume resistivity of 102 to 1010 ?·cm, 0 to 60 parts by weight of a conductive filler having a volume resistivity lower than 102 ?·cm and 100 to 1,500 parts by weight of an other inorganic filler.

Abstract: Underfill flow guide structures and methods of using the same are provided with a module. In particular the underfill flow guide structures are integrated with a substrate and are configured to prevent air entrapment from occurring during capillary underfill processes.

Abstract: Disclosed is a resin composition for encapsulating a semiconductor containing a curing agent, an epoxy resin (B) and an inorganic filler (C), wherein the curing agent is a phenol resin (A) having a predetermined structure. Also disclosed is a semiconductor device obtained by encapsulating a semiconductor element with a cured product of the resin composition for encapsulating a semiconductor.

Abstract: An integrated circuit package comprises a molding compound covering a semiconductor die. A healing substance is on the surface of the semiconductor die at an interface of the molding compound and the semiconductor die. The healing compound comprises a catalyst and a plurality of microcapsules containing a sealing compound. If the molding compound becomes delaminated from the semiconductor die the microcapsules rupture and spill the sealing compound. When the sealing compound is spilled and contacts the catalyst the sealing compound and catalyst polymerize and fasten the molding compound to the semiconductor die.

Abstract: A stacked integrated circuit package system is provided including providing a first device and a second device with the first device, the second device, or a combination thereof having an integrated circuit die; forming a conductive spacer structure over the first device with the conductive spacer structure having a spacer filler around a conductive element; mounting the second device over the conductive spacer structure and the first device; and encapsulating the first device, the second device, and the conductive spacer structure.

Abstract: An integrated circuit package system includes: forming an external interconnect; connecting an integrated circuit die and the external interconnect; forming a package encapsulation, having a recess, covering the integrated circuit die with a portion of the external interconnect exposed by the recess; and connecting an integrated circuit device and the external interconnect in the recess.

Abstract: Use of Pb-free solder has become essential due to the environmental problem. A power module is formed by soldering substrates with large areas. It is known that in Sn-3Ag-0.5Cu which hardly creeps and deforms with respect to large deformation followed by warpage of the substrate, life is significantly shortened with respect to the temperature cycle test, and the conventional module structure is in the situation having difficulty in securing high reliability. Thus, the present invention has an object to select compositions from which increase in life can be expected at a low strain rate. In Sn solder, by doping In by 3 to 7% and Ag by 2 to 4.5%, the effect of delaying crack development at a low strain rate is found out, and as a representative composition stable at a high temperature, Sn-3Ag-0.5Cu-5In is selected. Further, for enhancement of reliability, a method for partially coating a solder end portion with a resin is shown.

Abstract: A cost-effective, ultra-compact, hybrid power module packaging system and method for making allows device operation in conventional and high temperature ranges over 300° C. Double metal leadframes are directly bonded to the front- and backside of semiconductor chips, and injection-molded high temperature polymer materials encapsulate the module. The invention eliminates the use of unreliable metal wirebonds and solders joints, and expensive aluminum nitride ceramic substrates commonly used in conventional and high temperature hybrid power modules. Advantages of the new power modules include high current carrying capability, low package parasitic impedance, low thermo-mechanical stress under high temperature cycling, low package thermal resistance (double-side cooling), modularity for easy system-level integration, and low-cost manufacturing of devices compatible with current electronic packaging industry. A first embodiment uses molybdenum leadframes for operation in temperatures over 300° C.

Abstract: An electronic part mounting structure includes electronic part having a plurality of electrode terminals, a substrate provided with connection terminals in locations corresponding to these electrode terminals, and protruding electrode for connecting one of electrode terminals and one of connection terminals, where electrode terminal of electronic part and connection terminal of substrate are connected through protruding electrode and protruding electrode is formed of a conductive resin including a photosensitive resin and a conductive filler.

Abstract: A wiring structure having a wiring-terminal-connection adhesive that includes a curing agent capable of generating a free radical upon heating, a radically polymerizable substance and silicone particles.