With Specified Filler Material Patents (Class 257/789)
  • Patent number: 8105687
    Abstract: An electroconductive bonding material contains a thermosetting resin, a low-melting-point metal powder which is melted at a temperature equal to or lower than the thermosetting temperature of the thermosetting resin, a high-melting-point metal powder which is not melted at a temperature equal to or lower than the thermosetting temperature of the thermosetting resin and which reacts with the low-melting-point metal powder to form a reaction product having a high melting point of 300° C. or higher during heat-hardening of the thermosetting resin, and a reducing substance which removes an oxide formed on the surface of the high-melting-point metal powder. The total content of the low-melting-point metal powder and the high-melting-point metal powder is 75% to 88% by weight, and the particle size ratio D1/D2 of the average particle size D1 of the low-melting-point metal powder to the average particle size D2 of the high-melting-point metal powder is 0.5 to 6.0.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: January 31, 2012
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Akihiro Nomura, Hidekiyo Takaoka, Kosuke Nakano
  • Patent number: 8105881
    Abstract: A method of fabricating a chip package structure includes the steps of providing a lead frame having a die pad, plural leads and at least one structure enhancement element. A chip is then disposed on the die pad and plural bonding wires are formed to electrically connect the chip to the leads. Then, an upper encapsulant and a first lower encapsulant are formed on an upper surface and a lower surface of the lead frame, respectively. The first lower encapsulant has plural concaves to expose the structure enhancement element. Finally, the structure enhancement element is etched with use of the first lower encapsulant as an etching mask until the die pad and one of the leads connected by the structure enhancement element, or two of the adjacent leads connected thereby are electrically insulated.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: January 31, 2012
    Assignee: ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Jie-Hung Chiou, Yong-Chao Qiao, Yan-Yi Wu
  • Publication number: 20120018906
    Abstract: In a circuit device of the present invention, the lower surface side of a circuit board and part of side surfaces thereof are covered with a second resin encapsulant, and the upper surface side and the like of the circuit board are covered with a first resin encapsulant. Since heat dissipation to the outside of the circuit device is achieved mainly through the second resin encapsulant, a particle size of filler contained in the second resin encapsulant is made larger than a particle size of filler contained in the first resin encapsulant. Heat dissipation to the outside of the circuit device is greatly improved.
    Type: Application
    Filed: July 22, 2011
    Publication date: January 26, 2012
    Applicant: ON Semiconductor Trading, Ltd.
    Inventors: Katsuyoshi MINO, Masaru Kanakubo, Akira Iwabuchi, Masami Motegi
  • Patent number: 8094457
    Abstract: An electronic apparatus includes a substrate, electronic components mounted on the substrate, an antenna mounted on the substrate, and a resin material containing a dielectric constant adjusting material added therein, and sealing the electronic components and the antenna.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: January 10, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Tomoharu Fujii
  • Patent number: 8093699
    Abstract: A circuit device in which highly reliable sealing with a resin can be achieved is provided. A semiconductor chip is provided on one surface of an insulating resin film and a conductive layer that is electrically connected to the semiconductor chip is provided on another surface of the insulating resin film. A solder ball (electrode) for the connection to a circuit board is provided on the conductive layer. An insulating resin layer is further provided between the conductive layer and the circuit board to embed the electrode therein. In this manner, the circuit device is formed. A side face of the semiconductor chip is covered with the insulating resin film.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: January 10, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasuhiro Kohara, Ryosuke Usui, Hideki Mizuhara, Yasunori Inoue
  • Patent number: 8093704
    Abstract: In some embodiments, package on package using a bump-less build up layer (BBUL) package is presented.
    Type: Grant
    Filed: June 3, 2008
    Date of Patent: January 10, 2012
    Assignee: Intel Corporation
    Inventors: Eric C. Palmer, John S. Guzek
  • Patent number: 8088650
    Abstract: A method of fabricating a chip package is provided. A thin metal plate having a first protrusion part, a second protrusion part and a plurality of third protrusion parts are provided. A chip is disposed on the thin metal plate, and a plurality of bonding wires for electrically connecting the chip to the second protrusion part and the second protrusion part to the third protrusion parts is formed. An upper encapsulant and a lower encapsulant are formed on the upper surface and the lower surface of the thin metal plate respectively. The lower encapsulant has a plurality of recesses for exposing a portion of the thin metal plate at locations where the first protrusion part, the second protrusion part and the third protrusion parts are connected to one another. Finally, the thin metal plate is etched by using the lower encapsulant as an etching mask.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: January 3, 2012
    Assignee: ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Yong-Chao Qiao, Jie-Hung Chiou, Yan-Yi Wu
  • Patent number: 8044524
    Abstract: An adhesive for connecting circuit members, which is interposed between a semiconductor chip having protruding connecting terminals and a board having wiring patterns formed thereon for electrically connecting the connecting terminals and the wiring patterns facing each other and bonding the semiconductor chip and the board by applying pressure/heat, containing a resin composition containing a thermoplastic resin, a crosslinkable resin and a hardening agent for forming a crosslink structure of the crosslinkable resin; and composite oxide particles dispersed in the resin composition.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: October 25, 2011
    Assignee: Hitachi Chemical Company, Ltd.
    Inventor: Akira Nagai
  • Patent number: 8034447
    Abstract: The invention intends to provide an electronic component mounting adhesive that can inhibit cracks and peelings in an electronic component mounting structure obtained by joining electronic components each other from occurring and an electronic component mounting structure obtained by joining electronic components with such an electronic component mounting adhesive. In an electronic component mounting structure, a first circuit board and a second circuit board are bonded with an electronic component mounting adhesive. Here, the electronic component mounting adhesive is obtained by dispersing metal particles having the melting temperature Mp lower than the glass transition temperature Tg of a cured material of a thermosetting resin in the thermosetting resin.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: October 11, 2011
    Assignee: Panasonic Corporation
    Inventors: Tadahiko Sakai, Hideki Eifuku, Kouji Motomura
  • Publication number: 20110241227
    Abstract: The invention is aimed at providing a liquid resin composition capable of densely containing a filler and of filling up a narrow gap in a flip-chip-bonded semiconductor device, and a highly-reliable semiconductor device using the same. The liquid resin composition of the present invention contains (A) an epoxy resin; (B) an epoxy resin curing agent; and (C) a filler, wherein content of (C) the filler is 60% by weight or more and 80% by weight or less of the whole liquid resin composition, and contact angle (?) of the liquid resin composition, measured at 110° C. in accordance with JIS R3257, is 30° or smaller.
    Type: Application
    Filed: December 17, 2009
    Publication date: October 6, 2011
    Inventor: Daisuke Oka
  • Patent number: 8008124
    Abstract: An adhesive film for a semiconductor containing an (A) ester (meth)acrylate copolymer and a (B) thermoplastic resin other than the ester (meth)acrylate copolymer, and composed so as to satisfy the following formula (1) for two hours from 10 minutes after starting measurement, in which ? represents an amount of shearing strain produced upon undergoing a shearing stress of 3000 Pa at a frequency of 1 Hz and a temperature of 175° C. on parallel plates of 20 mm in diameter, exhibits superior filling performance in surface unevenness of a substrate through an encapsulating material sealing process, despite that semiconductor chips are stacked in multiple layers in the semiconductor device and hence a wire bonding process imposes a longer thermal history. 0.10???0.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: August 30, 2011
    Assignee: Sumitomo Bakelite Co., Ltd.
    Inventor: Hiroyuki Yasuda
  • Patent number: 8004078
    Abstract: Provided is an adhesive composition for a semiconductor device. For example, the adhesive composition comprises a binder resin and a silicon carbide filler. The silicon carbide filler has relatively high thermal conductivity and a relatively low coefficient of thermal expansion (CTE). Accordingly, the adhesive composition containing the silicon carbide filler exhibits improved heat dissipation performance and electrical performance due to high thermal conductivity and shows inhibition of delamination or cracking of semiconductor devices due to low CTE. The silicon carbide has high thermal conductivity, but is electrically non-conductive. Therefore, an electrically conductive adhesive can be obtained by additional incorporation of a silver (Ag) filler into the binder resin.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: August 23, 2011
    Assignee: Amkor Technology, Inc.
    Inventors: Jae Kyu Song, Bong Chan Kim, Min Yoo
  • Patent number: 7999276
    Abstract: Disclosed are a chip-type LED package and a light emitting apparatus having the same. The chip-type LED package includes a thermally conductive substrate with lead electrodes formed thereon. An LED chip is mounted on the thermally conductive substrate, and a lower molding portion covers the LED chip. In addition, an upper molding portion having hardness higher than that of the lower molding portion covers the lower molding portion. The upper molding portion is formed by performing transfer molding using resin powder. Accordingly, since the lower molding portion can be formed of a resin having hardness smaller than that of the upper molding portion, it is possible to provide a chip-type LED package in which device failure due to thermal deformation of the molding portion can be prevented.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: August 16, 2011
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventor: Yeo Jin Yoon
  • Patent number: 7994646
    Abstract: A semiconductor device is disclosed. One aspect provides a semiconductor device that includes a semiconductor chip including a first face and a second face opposite the first face, an encapsulant including inorganic particles encapsulating the semiconductor chip, a first metal layer attached to the first face of the semiconductor chip, a second metal layer attached the second face of the semiconductor chip, and electrically conducting material configured to connect the first metal layer with the second metal layer.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: August 9, 2011
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Edward Fuergut, Manfred Mengel, Ivan Nikitin
  • Patent number: 7989965
    Abstract: A system for dispensing an underfill material between an integrated circuit (IC) chip and a substrate includes a platform at which the underfill material is supplied. The IC chip and the substrate are mounted at the periphery of the platform. The platform rotates and facilitates the movement of the underfill material toward the IC chip and the substrate. The system further includes a Bernoulli tube that is located proximate to the IC chip and the substrate. The Bernoulli tube generates a low pressure in the proximity of the IC packages. The low pressure facilitates the dispensing of the underfill material between the IC chip and the substrate.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: August 2, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Vittal Raja Manikam, Yit Meng Lee, Vemal Raja Manikam
  • Patent number: 7982322
    Abstract: The present invention provides a liquid resin composition for electronic part sealing that is good in fluidity in a narrow gap, being free from void generation, and that excels in fillet formation; and an electronic part apparatus sealed thereby of high reliability (moisture resistance and thermal shock resistance). The liquid resin composition for electronic part sealing is characterized by comprising (A) an epoxy resin including a liquid epoxy resin, (B) a hardening agent including a liquid aromatic amine, (C) a hydrazide compound having an average particle diameter of less than 2 ?m, and (D) an inorganic filler having an average particle diameter of less than 2 ?m.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: July 19, 2011
    Assignee: Hitachi Chemical Co., Ltd.
    Inventors: Satoru Tsuchida, Shinsuke Hagiwara, Kazuyoshi Tendou
  • Patent number: 7977778
    Abstract: An integrated circuit package system is provided including forming an integrated circuit die, forming an interference-fit feature in the integrated circuit die, fitting a support element within the interference-fit feature, connecting an external interconnect and the integrated circuit die, and encapsulating the integrated circuit die.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: July 12, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Henry Descalzo Bathan, Lionel Chien Hui Tay, Zigmund Ramirez Camacho
  • Patent number: 7973327
    Abstract: A light source and method for fabricating the same are disclosed. The light source includes a die, a light conversion component, and a scattering ring. The die emits light of a first wavelength through a top surface of the die and one or more side surfaces of the die, and is bonded to a mounting substrate. The light conversion component converts light of the first wavelength to light of a second wavelength, the light conversion component having a bottom surface bonded to the top surface of the die. The light conversion component has lateral dimensions such that a space exists around the die, the space being bounded by the substrate and the light conversion component. The scattering ring is positioned in the space such that a portion of the light emitted from the side surfaces of the die is scattered into the light conversion component.
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: July 5, 2011
    Assignee: Bridgelux, Inc.
    Inventor: Scott West
  • Publication number: 20110156283
    Abstract: A microelectronic package comprises a die (110) having a front side (111) containing active circuitry (115) and a back side (112) opposite the front side and a film (120) on the back side of the die. The film has a thickness (121) of at least 20 micrometers, a Young's modulus of at least 10 GPa, and a post-cure glass transition temperature of at least 100° Celsius.
    Type: Application
    Filed: December 28, 2009
    Publication date: June 30, 2011
    Inventors: Shankar Ganapathysubramanian, Leonel R. Arana, Robert L. Sankman, Wen Janet Feng, Robert M. Nickerson
  • Patent number: 7969023
    Abstract: An integrated circuit package in package system includes: providing a substrate with a first wire-bonded die mounted thereover, and connected to the substrate with bond wires; mounting a triple film spacer above the first wire-bonded die, the triple film spacer having fillers in a first film and in a third film, and having a second film separating the first film and the third film, and the bond wires connecting the first wire-bonded die to the substrate are embedded in the first film; and encapsulating the first wire-bonded die, the bond wires, and the triple film spacer with an encapsulation.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: June 28, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Taeg Ki Lim, JaEun Yun, Byung Joon Han
  • Patent number: 7969027
    Abstract: A semiconductor device comprising an organic substrate, at least one semiconductor chip provided on a surface of the substrate, and a cured resin composition encapsulating the semiconductor chip provided on the surface of the substrate, characterized in that an absolute value of a distance between an imaginary line connecting two diagonally opposite corners of the substrate and a highest or lowest position on the surface of the substrate between the corners is smaller than 600 ?m, as measured with a laser three-dimensional measuring instrument, a total volume ratio of the semiconductor chip to the semiconductor device ranges from 18 to 50%, and the cured resin composition comprises an inorganic filler (C) in such an amount that a weight ratio of the inorganic filler (C) to a total weight of the cured resin composition ranges from 80 to 90%.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: June 28, 2011
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Shoichi Osada
  • Patent number: 7968187
    Abstract: A composite is provided, comprising a substrate and a film on the substrate. The film has an RMS surface roughness of 25 nm to 500 nm, a film coverage of 25% to 60%, a surface energy of less than 70 dyne/cm; and a durability of 10 to 5000 microNewtons. Depending on the particular environment in which the film is to be used, a durability of 10 to 500 microNewtons may be preferred. A film thickness 3 to 100 times the RMS surface roughness of the film is preferred.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: June 28, 2011
    Assignee: Integrated Surface Technologies
    Inventors: Jeff Chinn, W. Robert Ashurst, Adam Anderson
  • Publication number: 20110147954
    Abstract: A semiconductor device of the present invention (1) has a substrate (2); a semiconductor element (3) provided on at least one side of the substrate (2); a first resin (4) obtained by curing a first resin composition which fills a gap between the substrate (2) and the semiconductor element (3); and a second resin (5) which covers the substrate (2) and the first resin (4), and obtained by curing a second resin composition after the first resin composition is cured. In the present invention, adhesion strength between the first resin (4) and the second resin (5) is 18 MPa or larger at room temperature.
    Type: Application
    Filed: September 9, 2009
    Publication date: June 23, 2011
    Inventor: Masahiro Kitamura
  • Patent number: 7964954
    Abstract: An integrated circuit having a semiconductor sensor device including a sensor housing partly filled with a rubber-elastic composition is disclosed. One embodiment has a sensor chip with sensor region arranged in the interior of the housing. The sensor housing has an opening to the surroundings which is arranged in such a way that the sensor region faces the opening. The sensor chip is embedded into a rubber-elastic composition on all sides in the interior of the housing. The sensor housing has a sandwich-like framework having three regions arranged one above another, including an intermediate region with the rubber-elastic composition.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: June 21, 2011
    Assignee: Infineon Technologies AG
    Inventor: Jean Schmitt
  • Publication number: 20110140289
    Abstract: A resin composition containing a silica-based filler which differs in refractive index by ±0.03 from the curable base resin and has a thermal conductivity no lower than 0.5 W/m·K, and a light-emitting diode encapsulated with said resin composition. The resin composition is preferably prepared from a curable silicone resin which imparts a cured product having a refractive index of 1.45 to 1.55 and cristobalite powder dispersed therein.
    Type: Application
    Filed: December 14, 2010
    Publication date: June 16, 2011
    Inventors: Toshio SHIOBARA, Tsutomu KASHIWAGI
  • Patent number: 7960847
    Abstract: A manufacturing method for a packaging structure of SIP (system in package) includes the following steps. First step is providing a substrate having electronic devices thereon. Second step is covering the electronic devices by a mixture of a molding compound and a conductive polymer precursor so as to form a molding structure, wherein the substrate, the electronic devices and the molding structure forms a collective electronic module. Third step is separating the collective electronic module into a plurality of individual electronic modules. Fourth step is performing a doping step by using a doping element for transforming the conductive polymer precursor in the mixture into a conductive layer near the surface of the molding structure. Therefore, the manufacturing method is optimized for forming a shielding structure of the SIP module.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: June 14, 2011
    Assignee: Azurewave Technologies, Inc.
    Inventors: Chung-Er Huang, Ming-Tai Kuo
  • Patent number: 7952212
    Abstract: Applications of smart polymer composites to integrated circuit packaging.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: May 31, 2011
    Assignee: Intel Corporation
    Inventors: Nirupama Chakrapani, James Chris Matayabas, Jr., Vijay Wakharkar
  • Patent number: 7898094
    Abstract: An epoxy resin composition comprising: (A) an epoxy resin having at least three epoxy groups per molecule and an epoxy equivalent of 170 or lower; (B) an epoxy resin having a phenolic nucleus and two epoxy groups in such an amount that a weight ratio of the epoxy resin (B) to the epoxy resin (A) ranges from 35/65 to 65/35; (C) a phenolic curing agent in such an amount that a molar ratio of phenolic hydroxyl groups to the whole epoxy groups in the composition ranges from 0.5 to 1.5; and (D) an inorganic filler in an amount of from 86 to 92 wt %, based on a total weight of the composition. The composition provides encapsulated semiconductor devices much less warped than those encapsulated with a conventional composition.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: March 1, 2011
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shoichi Osada, Takayuki Aoki
  • Patent number: 7897234
    Abstract: A potting compound for electronic components comprises a first composition of asphalt and sand and a second composition that attenuates the forces normally applied by the first composition when it is used alone. The force attenuator preferably comprises solvent-refined heavy paraffinic petroleum oil from about 0.1 to 20 wt % of the compound.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: March 1, 2011
    Assignee: OSRAM SYLVANIA Inc.
    Inventors: John H. Selverian, H. Steven Mackel, William D. Koenigsberg
  • Patent number: 7887716
    Abstract: This invention relates to cationically curable sealants that provide low moisture permeability and good adhesive strength after cure. The composition consists essentially of an electrophoretic device containing an oxetane compound and a photoinitiating system comprising and photoinitiator and optionally a photosensitizer.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: February 15, 2011
    Assignee: Henkel AG & Co. KGaA
    Inventors: Shengqian Kong, Stijn Gillissen
  • Patent number: 7884461
    Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole and a contact conductive via formed therein, a die disposed within the die receiving through hole, a surrounding material filled in the gap except the die area of the die receiving though hole, a re-distribution layer formed on the substrate and coupled to the contact conductive via, a protection layer formed over the re-distribution layer, a cover material formed over the protection layer; and a terminal contact pad formed on the lower surface of the substrate and under the contact conductive via and the die to couple the contact conductive via.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: February 8, 2011
    Assignee: Advanced Clip Engineering Technology Inc.
    Inventors: Dyi-Chung Hu, Chun-Hui Yu
  • Patent number: 7875496
    Abstract: A flip chip mounting method includes holding a circuit board (213) and a semiconductor chip (206), aligning the circuit board (213) with the semiconductor chip (206) while holding them with a predetermined gap therebetween, heating the circuit board (213) or the semiconductor chip (206) to a temperature at which solder powder in a solder resin composition (216) formed of solder powder (214) and a resin (215) is melted, supplying the solder resin composition (216) by a capillary phenomenon, and curing the resin (215), wherein the melted solder powder (214) in the solder resin composition (216) is moved through the predetermined gap across which the circuit board (213) and the semiconductor chip (206) are held, and self-assembled and grown, whereby the connection terminals (211) and the electrode terminals (207) are connected to each other electrically.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: January 25, 2011
    Assignee: Panasonic Corporation
    Inventors: Seiichi Nakatani, Seiji Karashima, Takashi Kitae, Yoshihisa Yamashita, Takashi Ichiryu
  • Patent number: 7842540
    Abstract: A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: November 30, 2010
    Assignee: Ziptronix, Inc.
    Inventors: Qin-Yi Tong, Paul M. Enquist, Anthony Scot Rose
  • Patent number: 7842385
    Abstract: A coated nano particle and an electronic device using the composite nano particle as an illuminator are provided. The composite nano particle includes a nano particle receiving light and emitting light; and a coating material formed on a surface of the nano particle and having an index of refraction different from that of the nano particle. The coated nano particle is made by coating a surface of the nano particle with a material having an index of refraction, which has an intermediate value between an index of refraction of a matrix and an index of refraction of the nano particle as an illuminator, with a predetermined thickness. The light emitted from the nano particle is efficiently transferred to the outside as the light reflected from the matrix and absorbed by the nano particle is suppressed. Therefore, a luminous efficiency of the illuminator is improved, and an electronic device using the illuminator is provided.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: November 30, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Eun-joo Jang, Shin-ae Jun
  • Patent number: 7838896
    Abstract: A light emitting apparatus includes a blue light emitting diode (LED), a first and second phosphor layers. The second phosphor layer is between the blue LED and the first phosphor layer. When a blue beam of a shorter wavelength excites the phosphor layers, the excitation efficiency of the first phosphor layer is greater than that of the second phosphor layer. When a blue beam of a longer wavelength excites the phosphor layers, the excitation efficiency of the first phosphor layer is less than that of the second phosphor layer. Moreover, the wavelength of the peak intensity of the light beam from the first phosphor layer is shorter than that of the second phosphor layer. And, the dividing value between the shorter wavelength and the longer wavelength is within the range from a first wavelength to a second wavelength.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: November 23, 2010
    Assignee: Lite-On Technology Corporation
    Inventors: Hung-Yuan Su, Ru-Shi Liu
  • Patent number: 7830026
    Abstract: A semiconductor device with plastic housing composition includes an internal wiring that is electrically insulated from the plastic housing composition by an insulation layer. The plastic housing composition has a high thermal conductivity and a low coefficient of expansion, the coefficient of expansion being adapted to the semiconductor chip of the semiconductor device. This is achieved by forming the plastic housing composition with electrically semiconducting and/or electrically conducting filler particles. In particular, this plastic housing composition is advantageously used for semiconductor devices with flip-chip contacts and/or for semiconductor devices which are constructed according to the “universal packaging concept”.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: November 9, 2010
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Edward Fuergut
  • Publication number: 20100276818
    Abstract: The device includes at least one optoelectronic component positioned on a substrate and at least one transparent face. The component is covered by a packaging layer which includes at least one barrier layer and a moisture-reactive layer. The reactive layer includes a moisture-reactive material chosen from alkaline-earth metals, alkali metals and organo-metallic derivatives. The material can be positioned in the moisture-reactive layer in the form of a continuous layer or in the form of a plurality of nodules dispersed in an organic matrix.
    Type: Application
    Filed: December 8, 2008
    Publication date: November 4, 2010
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Tony Maindron, David Vaufrey
  • Patent number: 7825528
    Abstract: An epoxy resin composition, and a method of making the same, includes an epoxy resin and a curing agent, the epoxy resin composition also includes inorganic fillers, curing accelerators, and modified silicone oils. The epoxy resin is a modified epoxy resin prepared by glycidyl etherification of a mixture of a novolac type phenolic compound having a biphenyl derivative in the molecule and a 4,4?-dihydroxy biphenyl compound, and the curing agent is a mixture of a polyaromatic curing agent and a polyfunctional curing agent.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: November 2, 2010
    Assignee: Cheil Industries, Inc.
    Inventors: Jo Gyun Kim, Kun Bae Noh, Yoon Kok Park
  • Patent number: 7816770
    Abstract: To hermetically seal a cavity in a microelectronic component, a cap located in a sealing device is positioned above the orifice opening into the cavity. The cap plastically deforms to seal the cavity. The sealing device includes a cavity permitting the cavity of the microelectronic component to be filled. The sealing device slides along the component so as to be positioned opposite either the filling cavity, or the cap.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: October 19, 2010
    Assignees: Commissariat a l'Energie Atomique, Centre National d'Etudes Spatiales
    Inventor: Aymeric Lai
  • Patent number: 7808113
    Abstract: A semiconductor device assembly (200) includes a workpiece (205) having a surface including a die attach region corresponding to regions under an integrated circuit (IC) die 210. The die attach region of workpiece (205) includes non-noble metal surfaces (215) and a plurality of flip chip (PC) pads at pad locations (214). A solder mask layer (207) is on a surface of the workpiece (205) outside the die attach region. The non-noble metal surfaces (215) in the die attach region include an adhesion promoter layer (221), wherein the adhesion promoter layer 221 is absent from the plurality of PC pads (214). An integrated circuit (IC) die (210) having a plurality of bumps (211) bonded in a flip chip arrangement to the workpiece (205). An underfill material (232) fills a space between the bumped IC die (210) and the workpiece (205).
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: October 5, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: Bernardo Gallegos
  • Publication number: 20100244286
    Abstract: Nanoparticles (<100 nm) and submicron particles (<400 nm) can be used as filler material to form a nanocomposite that can be used as an encapsulant for optoelectronic devices. These nanocomposites can function to reduce light scattering and increase thermal, mechanical and dimensional stability of the optoelectronic device. Such nanocomposites can also improve moisture barrier characteristics, lower the dielectric constant and increase resistivity of the optoelectronic device.
    Type: Application
    Filed: October 2, 2009
    Publication date: September 30, 2010
    Inventor: Earl Vincent B. LAGSA
  • Publication number: 20100237513
    Abstract: Applications of smart polymer composites to integrated circuit packaging.
    Type: Application
    Filed: June 30, 2006
    Publication date: September 23, 2010
    Inventors: Nirupama Chakrapani, James Chris Matayabas, JR., Vijay Wakharkar
  • Patent number: 7795744
    Abstract: The objective of the present invention is to provides a cationically curable epoxy resin composition excellent in sealing and adhesive property specifically to glass, excellent reflow resistance property, moisture resistance and water resistance while keeping a good workability intrinsic to a light curable resins. The invention provides a cationically curable epoxy resin composition comprising: (a) an epoxy resin component; (b) a cationic photo-initiator; (c) a cationic thermal-initiator and (d) a filler selected from the group consisting of oxides, hydroxides and carbonates containing a Group II element in the long periodic table.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: September 14, 2010
    Assignee: Henkel Corporation
    Inventors: Chunfu Chen, Yoke Ai Gan
  • Patent number: 7794127
    Abstract: A light emitting diode (10) includes an LED chip (14) and an encapsulant (16) enclosing the LED chip. The LED chip has a light emitting surface (141), and the encapsulant has a light output surface (161) over the light emitting surface. The light output surface defines a plurality of annular, concentric grooves (163). Each groove is cooperatively enclosed by a first groove wall (165) and a second groove wall (166). The first groove wall is a portion of a circumferential side surface of a cone, and a conical tip of the cone is located on the light emitting surface of the LED chip.
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: September 14, 2010
    Assignees: Fu Zhun Precision Industry (Shen Zhen) Co., Ltd., Foxconn Technology Co., Ltd.
    Inventors: Chung-Yuan Huang, Jer-Haur Kuo, Ye-Fei Yu, Lin Yang, Xin-Xiang Zha
  • Patent number: 7790629
    Abstract: A method of depositing oxide materials on a substrate is provided. A deposition chamber holds the substrate, where the substrate is at a specified temperature, and the chamber has a chamber pressure and wall temperature. A precursor molecule containing a cation material atom is provided to the chamber, where the precursor has a line temperature and a source temperature. An oxidant is provided to the chamber, where the oxidant has a source flow rate. Water is provided to the chamber, where the water has a source temperature. By alternating precursor pulses, the water and the oxidant are integrated with purges of the chamber to provide low contamination levels and high growth rates of oxide material on the substrate, where the pulses and the purge have durations and flow rates. A repeatable growth cycle includes pulsing the precursor, purging the chamber, pulsing the water, pulsing the oxidant, and purging the chamber.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: September 7, 2010
    Assignees: The Board of Trustees of the Leland Stanford Junior University, Honda Motor Co., Ltd
    Inventors: Timothy P. Holme, Friedrich B. Prinz, Masayuki Sugawara
  • Patent number: 7786596
    Abstract: A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: August 31, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kuan-Neng Chen, Bruce K. Furman, Edmund J. Sprogis, Anna W. Topol, Cornelia K. Tsang, Matthew R. Wordeman, Albert M. Young
  • Patent number: 7781900
    Abstract: One aspect of the invention relates to a semiconductor device including a housing and a semiconductor chip partly embedded in a plastic housing composition. Another aspect relates to a method for producing the same. The plastic housing composition has at least one host component having a softening temperature and an incorporated component having a phase change temperature. In this case, the softening temperature of the host component is greater than the phase change temperature of the incorporated component.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: August 24, 2010
    Assignee: Infineon Technologies AG
    Inventors: Manuel Carmona, Anton Legen, Ingo Wennemuth
  • Patent number: 7776993
    Abstract: A reworkable thermoset epoxy-containing material that allows for a reworkable assembly such as a reworkable waferlevel underfilled microelectronic package. A method for using the reworkable thermoset material in the formation of a microelectronic package using this material.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: August 17, 2010
    Assignee: International Business Machines Corporation
    Inventors: Stephen Leslie Buchwalter, Claudius Feger, Gareth Hougham, Nancy LaBianca, Hosadurga Shobha
  • Patent number: 7777355
    Abstract: Organometallic colloid(s) is dispersed in a polymer matrix to form an infrared-blocking encapsulant.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: August 17, 2010
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Janet Bee Yin Chua, Kean Loo Keh
  • Publication number: 20100193973
    Abstract: This invention is a semiconductor wafer having an active side and a back side opposite the active side, which back side is coated with a filled, spin-coatable coating, wherein the coating comprises a resin and a spherical filler characterized by an average particle diameter of greater than 2 ?m and a single peak particle size distribution. In another embodiment the invention is a method for producing a spin-coatable, B-stageable coating with a thixotropic index of 1.2 or less. In a third embodiment the invention is a method for producing a coated semiconductor wafer.
    Type: Application
    Filed: July 30, 2009
    Publication date: August 5, 2010
    Inventor: Eunsook Chae