Abstract: A semiconductor integrated device, provided with a semiconductor chip on which a semiconductor integrated circuit is formed and a support substrate laminated on at least one surface of the semiconductor chip, wherein the semiconductor chip and the support substrate are fastened using resin having particle-the minimum film thickness of the resin is larger than the maximum particle diameter of the filler.

Abstract: A semiconductor component includes a substrate and multiple stacked, encapsulated semiconductor dice on the substrate. A first die is back bonded to the substrate and encapsulated in a first encapsulant, and a second die is back bonded to the first encapsulant. The first encapsulant has a planar surface for attaching the second die, and can also include locking features for the second die. The component also includes a second encapsulant encapsulating the second die and forming a protective body for the component. A method for fabricating the component includes the steps of attaching the first die to the substrate, forming the first encapsulant on the first die, attaching the second die to the first encapsulant, and forming the second encapsulant on the second die.

Abstract: A structure for a chip or chip package is disclosed, with final passivation and terminal metallurgy which are mechanically decoupled but electrically coupled to the multilayer on-chip interconnects. This decoupling allows the chip to survive packaging stresses in the final passivation region, with strain relief from the decoupling region and compliant leads therein, so that on-chip interconnect levels do not feel these external packaging or other stresses. This structure is particularly preferred for on-chip interconnects consisting of Cu and low-k dielectric, the latter having inferior mechanical properties relative to SiO2. The decoupled region extends over all chips on the wafer. It may also extend into the edgeseal or dicing channel region so as to allow chip dicing and retention of this mechanical decoupling all around every chip on the wafer.

Abstract: A system for chip packaging includes an adamantoid packaging composition. The adamantoid composition ameliorates the CTE mismatch that typically exists between a packaged die and a resin-impregnated fiberglass mounting substrate. In an embodiment, the system includes a packaging composition that alone exhibits a CTE that is characteristic of an inorganic-filled underfill composite previously known. An embodiment is also directed to the assembly of a chip package that uses an adamantoid packaging composition.

Abstract: A chip package structure comprising a substrate, a chip, a plurality of bumps, a plurality of conductive wires and an insulating material is provided. The substrate has a first surface and a corresponding second surface. The substrate has a slot that penetrates the substrate. The chip is attached to the first surface of the substrate in a position that covers the slot. The conductive wires pass through the slot such that one end of each conductive wire is attached to a contact point on the chip while the other end of the conductive wire is attached to a contact point on the second surface of the substrate. The insulating material fills the space between the chip and the substrate and the slot so that the conductive wires and the bumps are enclosed.

Abstract: There is disclosed a coating material formulation for layering a plurality of electrodes to provide a substrate for the electrochemical synthesis of organic oligomers. Specifically, there is disclosed a coating layer of from about 0.5 to about 100 microns thick and is composed of a mixture of controlled porosity glass (CPG) particles having an average particle size of from about 0.25 to about 25 microns, and a thickening agent.

Abstract: A semiconductor device includes a semiconductor substrate, a first wiring arranged on the semiconductor substrate, a first electrode pad electrically connected to the first wiring, and a porous organic resin film covering the front surface of the semiconductor substrate such that the first electrode pad is exposed to the outside.

Abstract: In a semiconductor device of a structure comprising a thin semiconductor element bonded to a reinforcing plate via a bonding layer of a predetermined thickness, resin binder used for forming the bonding layer contains fillers including a first filler, which has a diameter generally equal to a target thickness of the bonding layer to be adjusted to a value within a range of proper thickness (from 25 ?m to 200 ?m). This can maintain the bonding layer within the range of proper thickness when the semiconductor element is bonded to the plate, and ensure on-board mounting reliability of the semiconductor device.

Abstract: A curable material useful as thermal material comprises at least one vinyl-terminated silicone oil, at least one conductive filler, and at least one hydrogen terminated silicone oil. The hydrogen terminated silicone oil is used to reduce a shear modulus G? of the cured thermal interface material.

Abstract: The application discloses an apparatus comprising an optical die flip-chip bonded to a substrate and defining a volume between the optical die and the substrate, the optical die including an optically active area on a surface of the die facing the substrate, an optically transparent material occupying at least those portions of the volume substantially corresponding with the optically active area, and an underfill material occupying portions of the volume not occupied by the optically transparent material.

Abstract: The particle diameter distribution of the filler material added to the adhesive of the invention has the first peak and the second peak positioned on a side of smaller particle diameters with respect to the first peak by 0.7? or more, and thus the rigidity of the hardened adhesive is improved. Therefore, the connection reliability of the electric device 5 having the semiconductor chip 11 and the substrate 13 by using the adhesive (adhesive film 15) is improved.

Abstract: A semiconductor component with an electromagnetic shielding device against alpha radiation, beta radiation and high-frequency electromagnetic radiation is presented. The semiconductor component includes a semiconductor chip with a circuit integrated therein with a number of electrical terminal areas and at least one ground terminal area. The semiconductor also includes a package that contains the semiconductor chip and also a chip carrier. The chip carrier has a number of external electrical terminals and an external ground terminal. The electrical terminal areas and the ground terminal areas of the semiconductor chip are electrically connected to the external electrical terminals and the external ground terminals of the chip carrier by connecting means. The semiconductor chip and the connecting means are in this case encapsulated by an electrically insulating passivation.

Abstract: The present invention provides an optical semiconductor device comprising: a wiring circuit board; at least one optical semiconductor element mounted on the wiring circuit board; resin layer A that encapsulates the at least one optical semiconductor element therewith; and resin layer B interposed between the resin layer A and the wiring circuit board, and having a tensile modulus as measured at 30° C. of 0.001 to 0.4 GPa.

Abstract: A semiconductor device includes a conductive layer with a plurality of wires, and a bonding pad formed in a region overlapping with the plurality of wires of the conductive layer. One of the wires is connected to the bonding pad, and an insulating protective film is formed between the remaining wires and the bonding pad. The protective film is bridged between adjacent wires at least in a region overlapping with the bonding pad. As a result, the protective film on the wires forms a bridge structure, which is effective in preventing cracking at a lower portion of the protective film. Further, a void formed underneath the bridged portion serves as an air spring to prevent damage to the structural elements, such as the wires, formed under the protective film. Further, because a polyimide film, which serves as a shock absorber, is not required, working efficiency can be improved and chip cost can be reduced.

Abstract: In a manufacturing method of a hybrid integrated circuit device of the invention, transfer molding is carried put by positioning a curved surface formed in a back surface of the substrate on a lower mold die side and a burr formed in a main surface of the substrate on an upper mold die side. This utilizes the curved surface to inject thermosetting resin in an arrow direction to pour the thermosetting resin through a below of the substrate. There are no broken fragments of burr in a thermosetting resin at the below of the substrate. As a result, a required minimum resin thickness is secured at the below of the substrate, thus realizing a hybrid integrated circuit device having a high voltage resistance, an excellent heat dissipation property and a high product quality.

Abstract: A method of silanizing the surface of a low-k interlayer dielectric oxides (carbon doped oxides or organo-silicate glasses) to improve surface adhesion to adjacent thin film layers in damascene integration of microelectronic devices. A low-k interlayer dielectric oxide may be exposed to the vapor of a silane-coupling agent in order to modify its surface energy to improve adhesion with adjacent thin film layers. A low-k interlayer dielectric oxide can also be silanized by dipping the low-k interlayer dielectric oxide in a solution of silane-coupling agent. The silane-coupling agent will cause covalent bonds between the low-k interlayer dielectric oxide and the adjacent thin film thereby improving adhesion.

Abstract: A semiconductor package production method containing a step in which a bond layer made of a single-layer film thermoset bond is provided on the back of a wafer on which many semiconductor devices are formed, a dicing tape is pasted onto its bond layer side, and the bond layer and the wafer are diced simultaneously in order to obtain semiconductor devices with the bond layer, and a step in which the semiconductor devices with the bond layer are detached from the dicing tape and die-attached to interposing substrates serving as bodies to which they are bonded; wherein, the aforementioned film thermoset bond contains an epoxy resin, an epoxy resin hardener, and a phenoxy resin as well as 50-80 wt % of spherical silica, and the bond layer is 100 ?m or thicker. A semiconductor device made by this method and a wafer for use with this method.

Abstract: A chip scale package and a method for its manufacture which include providing sticky interconnects on a surface of a semiconductor die, the interconnects being surrounded by a layer of thermal epoxy.

Abstract: A packaged microchip has a stress sensitive microchip, a package having a package modulus of elasticity, and an isolator between the microchip and the package. The isolator has an isolator modulus of elasticity that has a relationship with the package modulus of elasticity. This relationship causes no more than a negligible thermal stress to be transmitted to the microchip.

Abstract: An integrated circuit package includes a lid with EMI containment features. The lid may include a plurality of projections adapted to couple a ground plane of a circuit board.

Abstract: A no-flow underfill material and process suitable for underfilling a bumped circuit component. The underfill material initially comprises a dielectric polymer material in which is dispersed a precursor capable of reacting to form an inorganic filler. The underfill process generally entails dispensing the underfill material over terminals on a substrate, and then placing the component on the substrate so that the underfill material is penetrated by the bumps on the component and the bumps contact the terminals on the substrate. The bumps are then reflowed to form solid electrical interconnects that are encapsulated by the resulting underfill layer. The precursor may be reacted to form the inorganic filler either during or after reflow.

Abstract: A semiconductor package comprising a semiconductor wafer having an active surface comprising at least one integrated circuit, wherein each integrated circuit has a plurality of bond pads; and at least one cured silicone member covering at least a portion of the active surface, wherein at least a portion of each bond pad is not covered by the silicone member, the silicone member has a coefficient of linear thermal expansion of from 60 to 280 ?m/m° C. between ?40 and 150° C. and a modulus of from 1 to 300 MPa at 25° C., and the silicone member is prepared by the method of the invention.

Abstract: A semiconductor light emitting device ensuring a uniform color tone comprises a semiconductor light emitting element that emits light of a first wavelength upon injection of a current, a fluorescent material portion that contains a fluorescent material excited by light of the first wavelength to emit light of a second wavelength, and a diffuser mixed in an appropriate material around the semiconductor light emitting element.

Abstract: A process for the fabrication of devices that integrate protected microstructures, comprising the following steps: forming, in a body of semiconductor material, at least one microstructure having at least one first portion and one second portion which are relatively mobile with respect to one another and are separated from one another by at least one gap region, which is accessible through a face of the body; and sealing the gap. The sealing step includes depositing on the face of the body a layer of protective material, in such a way as to close the gap region, the protective layer being such as to enable relative motion between the first portion and the second portion of the microstructure.

Abstract: Reworkable thermoset acid-cleavable acetal and ketal based epoxy oligomers can be B-staged into a tack free state. Compositions containing the epoxy oligomers are employed in a reworkable assembly such as a wafer-level underfilled microelectronic package.

Abstract: A multi-chip module is proposed, which is designed to pack two or more semi-conductor chips in a stacked manner over a chip carrier in a single package. The multi-chip module is characterized by the use of adhesive with fillers to allow the topmost chip (i.e. the second chip) superimposed to the bottommost chip (i.e. the first chip) after the first chip electrically connected to the chip carrier. The thickness of the adhesive layer depends on the diameter of the fillers higher than loop height of the bonding wires that is positioned above the active surface of the first chip to prevent the bonding wires connected to the first chip to come in contact with the overlaid chip.

Abstract: Packages for electronic devices are formed from a die such as a silicon die in electrical communication with a substrate through a mating array, e.g. ball array, on the substrate. An underfill material is present between the die and substrate in the region of the array. For large dies (a dimension of 15 mm or greater) failure of the connection between the die and substrate is avoided by employing a particle filled underfill material with specifically chosen Young moduli both below and above the glass transition temperature of the underfill material.

Abstract: A semiconductor package device includes an insulative housing, a semiconductor chip, a terminal and a lead, wherein the insulative housing includes a top surface, a bottom surface, and a peripheral side surface between the top and bottom surfaces, the chip includes a conductive pad, the terminal protrudes downwardly from and extends through the bottom surface and is electrically connected to the pad, the lead protrudes laterally from and extends through the side surface and is electrically connected to the pad, the terminal and the lead are spaced and separated from one another outside the insulative housing, and the terminal and the lead are electrically connected to one another inside the insulative housing and outside the chip.

Abstract: A light emitting device and a method of making the same are provided. The light emitting device includes a light emitting diode and a submount. A phosphormaterial is disposed around at least a portion of the light emitting diode. An underfill is disposed between a first surface of the light emitting diode and a first surface of the submount. The underfill reduces contamination of the light emitting diode by the phosphor material.

Abstract: The present invention provides a wiring board in which electronic components are embedded by means of an embedding resin which attains a high mounting density of the electronic components in the wiring board, which exhibits excellent electrical properties such as insulating property, which prevents random reflection of light, and which reduces non-uniformity in color of the resin during curing thereof. The present invention includes a wiring board in which electronic components are embedded by use of an embedding resin having a dielectric constant of less than or equal to about 5 and tan ? of less than or equal to about 0.08. The embedding resin preferably contains carbon black in an amount of less than or equal to about 1.4 mass %. Moreover, the embedding resin preferably contains at least a thermosetting resin and at least one inorganic filler.

Abstract: A coin-shaped IC tag which can be endowed with a predetermined weight is described. The coin-shaped IC tag ensures a normal operation and affords a satisfactory feeling of weightiness as a value medium. Methods of manufacturing the coin-shaped IC tag are also described. The coin-shaped IC tag comprises an IC tag core. The IC tag core comprises an IC packaging base member including a base and an electronic circuit for communicating data and for recording data, the electronic circuit mounted on the base. The IC tag core also comprises a high specific gravity resin layer joined to the IC packaging base member.

Abstract: A fabrication method of a window-type ball grid array (WBGA) semiconductor package is provided. With a chip being mounted over an opening formed through a substrate and electrically connected to the substrate by bonding wires through the opening, a molding process is performed to form a first encapsulant for encapsulating the chip. Then, a printing process is performed to form a second encapsulant for filling the opening and encapsulating the bonding wires. Finally, a plurality of solder balls are implanted on the substrate at area outside the second encapsulant. By implementing the molding process first and then the printing process, problems such as chip cracks, bond pad contamination and delamination generated in the prior art, can be eliminated.

Abstract: An apparatus for enclosing logic chips includes a substrate upon which a logic chip is mounted and a mold cap disposed upon the substrate and covering the logic chip. The mold cap includes at least one extension of sufficient size and shape to provide structural support to a corner section of the substrate.

Abstract: A semiconductor package and a method for fabricating the same are proposed, wherein, in a molding process for encapsulating a semiconductor chip mounted on a substrate, a mold is used with a molding cavity formed with a plurality of recess portions relatively smaller in height, and with a plurality of air vents for connecting the recess portions to outside of the mold and for ventilate air in the molding cavity. This allows a molding resin used during molding to slow down its flow when flowing into the recess portions, as the molding resin rapidly absorbs heat transmitted from the mold and is increased in viscosity thereof. The slowed down molding resin can therefore be prevented from flashing out of the air vents, so that quality and appearance of the fabricated semiconductor package can be well assured.

Abstract: In an optoelectronic component assembly and a method for the production thereof, the optoelectronic component assembly includes an optoelectronic component arranged on a support element, which is surrounded by a closed dam. An encapsulation is arranged in an inner area of the dam, which encapsulates the optoelectronic component and includes two sealing materials. The inner area of the dam may be filled with a first sealing material up to the top edge of the optoelectronic component. The inner area of the dam located above the optoelectronic component is filled with a second transparent sealing material at least in one area of the window.

Abstract: A surface of an external electrode 3 of an electronic part 4 is formed with a coating containing resin ingredient. Thereby, adhesion strength and reliability may be significantly improved in mounting an electronic part onto a circuit board 1 through the medium of a conductive adhesive. Further, it will be able to mount an electronic part to an element to be mounted by utilizing a conductive adhesive forming an external electrode 3 as a connecting element. Further, surface roughness (Ra) of an external electrode 3 of an electronic part is set to 0.1 ?m or more and to 10.0 ?m or less and preferably to 1.0 ?m or more and to 5.0 ?m or less. Thereby, adhesion strength with a conductive adhesive may be significantly enhanced in comparison with a conventional electronic part presented.

Abstract: An encapsulant for use with opto-electronic devices and optical components incorporates a filler made from a glass that has been processed into particle form and heated to a predetermined temperature for a predetermined time, along with an epoxy having an index of refraction matched to that of the glass and heated to a predetermined temperature for a predetermined time, to prevent settling of the filler particles after mixing the filler particles with the epoxy, and thereby obtaining uniform dispersion of the particles within the epoxy. The encapsulant provides for high light transmittance, and its coefficient of thermal expansion can be varied by varying the amount of filler without substantially altering the optical properties of the encapsulant. The coefficient of thermal expansion variation within the encapsulant preferably is less than 30%, due to uniform dispersion of the filler particles within the epoxy.

Abstract: A silicon wafer has a B-stageable underfill material deposited on the active face of the wafer. The B-stageable underfill comprises a first composition with a lower curing temperature and a second composition with a higher curing temperature, characterized in that the first composition has been fully cured.

Abstract: A novel visible light curable composition for forming a thermally conductive interface and a method of using the same is provided. The composition is used to promote the transfer of heat from a source of heat such as an electronic device to a heat dissipation device such as a heat sink. The composition includes an elastomeric base matrix containing a light curable catalyst, loaded with a thermally conductive filler material such as boron nitride grains or ceramic filler. After the compound is prepared, it is screen or stencil printed onto the desired surface and cured by exposure to visible light. The thermal interface is bonded to the desired surface and has sufficient compressibility to allow it to overcome the voids in the mating surface to which the assembly is mounted.

Abstract: A semiconductor device having reduced self and mutual capacitance of bonded wires is provided by coating the wires with a foamed polymer effectively having a very low dielectric constant. Additional benefits are realized by electrically insulating the wires against short-circuiting, by cushioning, the wires with a low modulus sheath, and by protecting chip bond pad metallization.

Abstract: A die with flip chip bumps including at least one layer of filled underfill on the die surface and a layer of unfilled underfill over the filled underfill and the flip chip bumps. An IC assembly including a substrate with bumps and at least one layer of filled underfill on the substrate surface and a layer of unfilled underfill over the filled underfill and the bumps. A die or IC assembly with a plurality of filled underfill layers with differing CTE. Methods of making the dies and IC assemblies.

Abstract: Filled composite compositions can be used as encapsulants, underfill materials, and potting materials in electronic and optical packages that are subjected to a wide temperature range. The composites contain a matrix and a filler composition. In a preferred embodiment, the matrix is an organic material. The filler composition contains particles of a material that have a negative coefficient of thermal expansion. The filler composition contains particles having a wide range of sizes. Furthermore, the particles exhibit a non-normal, for example, log normal or power-law, particle distribution. The non-normal size distribution of the particles enables the filler composition to be formulated at high levels into organic matrices, resulting in composites that have very low coefficient of thermal expansion to match those of the semiconductor materials in the electronic package or optical components in an optical assembly.

Abstract: The testing method of OLED panels for all pixels on are provided. The methods include positioning anisotropic conductive films and conductive plates over a set of exposed first electrodes and a set of exposed second electrodes. Through the anisotropic conductive film and the conductive plate, the set of first electrodes and the set of second electrodes conduct. Thereafter, the set of first electrodes is connected to a first voltage and the set of second electrodes is connected to a second voltage. Through the voltage difference between the first voltage and the second voltage, all the inside the OLED panels are lit to perform the test.

Abstract: A flip-chip type semiconductor device sealed with a light transmissive epoxy resin composition comprising (A) an epoxy resin having the following general formula (i):  wherein n is 0 or a positive number, (B) a curing accelerator, and (C) an amorphous silica-titania co-melt as at least one of inorganic fillers, said composition satisfying the relationship of the following formula (1): [ { 2 ⁢ ( n A 2 + n C 2

Abstract: A method of mounting a semiconductor device having bumps on a board having pads so that each of the bumps is joined to a corresponding one of the pads is provided. Adhesive to be hardened by heat is provided between the semiconductor device and the board. The method includes the steps of pressing the bumps of the semiconductor device on the pads of the board, and heating a portion in which each of the bumps and a corresponding one of the pads are in contact with each other. A pressure of the bumps to the pads reaches a predetermined value before a temperature of the adhesive to which heat is supplied in the above step reaches a temperature at which the adhesive is hardened.

Abstract: Die attach adhesives and methods for their use, along with the devices that are obtained by the use of the methods. Using semiconductor chips as an example, the adhesives and the method for using them provides an interface between a chip (die) and the chip support. The method includes creating a space between the chip and the chip support of a given sized opening by using inorganic insulator particles having an average particle size of 1 &mgr;m to 1000 &mgr;m and a major axis to minor axis ratio of about 1.0 to 1.5.

Abstract: Various aspects of the present invention provide microelectronic component assemblies and methods for packaging such assemblies. In one example, a microelectronic component assembly includes a substrate and a microelectronic component. This substrate has a recess in its back face and a communication opening extending through a base of the recess. This microelectronic component has an active face positioned within the substrate recess, a back face positioned outside the substrate recess, and a plurality of component contacts carried by the component active face and electrically coupled to the substrate contacts through the communication opening. This exemplary microelectronic component assembly may also include a mold compound which encapsulates the microelectronic component and a portion of the substrate active face. The mold compound may also substantially fill a gap between the periphery of the microelectronic component and a sidewall of the recess.

Abstract: An electronic package includes an IC, such as a die, mounted onto one side of a thin interposer and a pin carrier mounted to an opposing side of the interposer. The pin carrier includes a cavity underneath the die. The cavity allows capacitors, or other electronic components, to be mounted against the interposer beneath the die. The cavity in the pin carrier is filled with an encapsulant to mechanically support the thin interposer in the area of the cavity during operation of an electronic system that includes the package.

Abstract: The present invention provides a thermosetting resin composition useful as an underfilling sealing resin which enables a semiconductor device, such as a CSP/BGA/LGA assembly which includes a semiconductor chip mounted on a carrier substrate, to be securely connected to a circuit board by short-time heat curing and with good productivity, which demonstrates excellent heat shock properties (or thermal cycle properties); and permits the CSP/BGA/LGA assembly to be easily removed from the circuit board in the event of semiconductor device or connection failure. Similarly, the compositions are useful for mounting onto a circuit board semiconductor chips themselves.

Abstract: A package substrate having a finger projection that is either an elevated or removably covered bond finger. The finger portion includes a portion to remain uncovered by a die and an underfill material when the package substrate is coupled to the die. A second portion of the finger projection may allow the first portion to remain uncovered as indicated.