Including Polyimide Patents (Class 257/792)
-
Patent number: 11894403Abstract: A semiconductor package including a semiconductor chip on a package substrate, a transparent substrate on the semiconductor chip, an attachment dam between the semiconductor chip and the transparent substrate, the attachment dam extending along an edge of the semiconductor chip, a first molding layer on the package substrate and surrounding a side surface of the semiconductor chip and including a first epoxy resin, and a second molding layer on the package substrate and filling a space between the semiconductor chip and the first molding layer and including a second epoxy resin. The first epoxy resin includes a first filler containing at least one of silica or alumina. The second epoxy resin includes a second filler containing at least one of silica or alumina. The content of the second filler in the second epoxy resin is greater than a content of the first filler in the first epoxy resin.Type: GrantFiled: April 25, 2021Date of Patent: February 6, 2024Inventor: Dong Kwan Kim
-
Patent number: 11567405Abstract: A photosensitive resin composition is also provided that includes a polymer precursor selected from a polyimide precursor and a polybenzoxazole precursor; a photo-radical polymerization initiator; and a solvent, in which an acid value of an acid group contained in the polymer precursor and having a neutralization point in a pH range of 7.0 to 12.0 is in a range of 2.5 to 34.0 mgKOH/g, and either the polymer precursor contains a radically polymerizable group or the photosensitive resin composition includes a radically polymerizable compound other than the polymer precursor.Type: GrantFiled: November 20, 2019Date of Patent: January 31, 2023Assignee: FUJIFILM CorporationInventors: Takeshi Kawabata, Kenta Yoshida, Yu Iwai, Akinori Shibuya
-
Patent number: 11487202Abstract: A photosensitive resin composition is also provided that includes a polymer precursor selected from a polyimide precursor and a polybenzoxazole precursor; a photo-radical polymerization initiator; and a solvent, in which an acid value of an acid group contained in the polymer precursor and having a neutralization point in a pH range of 7.0 to 12.0 is in a range of 2.5 to 34.0 mgKOH/g, and either the polymer precursor contains a radically polymerizable group or the photosensitive resin composition includes a radically polymerizable compound other than the polymer precursor.Type: GrantFiled: November 20, 2019Date of Patent: November 1, 2022Assignee: FUJIFILM CorporationInventors: Takeshi Kawabata, Kenta Yoshida, Yu Iwai, Akinori Shibuya
-
Patent number: 10811404Abstract: Provided are a package structure and a method of manufacturing the same. The package structure includes a die, a passive device, and a package. The die has a front side and a backside opposite to each other. The package is disposed on the backside of the die. The passive device is disposed between the backside of the die and the package.Type: GrantFiled: December 13, 2018Date of Patent: October 20, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ya Huang, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang
-
Patent number: 10636689Abstract: An apparatus for control of a temperature of a substrate has a temperature-controlled base, a heater, a metal plate, a layer of dielectric material. The heater is thermally coupled to an underside of the metal plate while being electrically insulated from the metal plate. A first layer of adhesive material bonds the metal plate and the heater to the top surface of the temperature controlled base. This adhesive layer is mechanically flexible, and possesses physical properties designed to balance the thermal energy of the heaters and an external process to provide a desired temperature pattern on the surface of the apparatus. A second layer of adhesive material bonds the layer of dielectric material to a top surface of the metal plate. This second adhesive layer possesses physical properties designed to transfer the desired temperature pattern to the surface of the apparatus.Type: GrantFiled: July 24, 2014Date of Patent: April 28, 2020Assignee: LAM RESEARCH CORPORATIONInventors: Anthony J. Ricci, Keith Comendant, James Tappan
-
Patent number: 10546823Abstract: Described is an apparatus which comprises: a die having a first side and a second side opposite to the first side; a die backside film (DBF) or die attach film (DAF) disposed over the first side of the die; and a fluorocarbon layer disposed over the DBF or DAF. Described is a method which comprises: applying a die backside film (DBF) over a first side of a die, wherein the die has a second side which metal bumps; and applying a plasma polymerization process to treat the DBF with a fluorocarbon plasma.Type: GrantFiled: November 13, 2015Date of Patent: January 28, 2020Assignee: Intel CorporationInventors: Balu Pathangey, Mihir A. Oka, Andrew Proctor
-
Patent number: 10109810Abstract: A flexible display panel, a package method thereof and a display device are provided. The package method includes: bonding a barrier film provided with an adhesive layer on a surface of a side of a display motherboard away from a substrate of the display motherboard, the non-adhesive portion of the adhesive layer loses adhesivity and covers the bonding area; the adhesive portion at least covers the display area; cutting the display motherboard provided with the barrier film, so that the adhesive portion for covering the display area is separate from adjacent portions, and a portion to be retained and a portion to be removed in the barrier film are separate; and stripping off portions, except the adhesive portion for covering the display area, in the adhesive layer and the portion to be removed in the barrier film.Type: GrantFiled: September 7, 2016Date of Patent: October 23, 2018Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventor: Wei Wang
-
Patent number: 9206314Abstract: A polycarbonate resin composition which has a high biogenic matter content, is excellent in transparency, surface hardness and impact resistance and is useful as an industrial material having excellent moldability.Type: GrantFiled: July 31, 2013Date of Patent: December 8, 2015Assignees: TEIJIN LIMITED, KANEKA CORPORATIONInventors: Hiroshi Okamoto, Toyohisa Fujimoto
-
Patent number: 9190349Abstract: An integrated circuit packaging system and method of manufacture thereof including: providing an unplated leadframe having a contact protrusion; depositing a solder resist on the contact protrusion; forming a contact pad and traces by etching the unplated leadframe; applying a trace protection layer on the contact pad and the traces; removing the solder resist; forming a recess in the trace protection layer by etching a top surface of the contact pad to a recess distance below a top surface of the trace protection layer; and depositing an external connector directly on the top surface of the contact pad.Type: GrantFiled: June 28, 2013Date of Patent: November 17, 2015Assignee: STATS ChipPAC Ltd.Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua, Asri Yusof
-
Patent number: 9169353Abstract: In the invention, a sealing composition for a semiconductor is provided which includes a polymer that includes two or more cationic functional groups including at least one of a tertiary nitrogen atom or a quaternary nitrogen atom, that has a weight average molecular weight of from 2,000 to 1,000,000, and that has a branching degree of 48% or more, wherein a content of sodium and a content of potassium in the sealing composition are each 10 ppb by weight or less on an element basis.Type: GrantFiled: January 16, 2013Date of Patent: October 27, 2015Assignee: MITSUI CHEMICALS, INC.Inventors: Shoko Ono, Yasuhisa Kayaba, Hirofumi Tanaka, Kazuo Kohmura, Tsuneji Suzuki, Shigeru Mio
-
Patent number: 8969219Abstract: The present invention relates to a method for preparation of an ultraviolet (UV)-curable inorganic-organic hybrid resin containing about or less than 4% volatiles and less than 30% organic residues. The UV-curable inorganic-organic hybrid resin obtained according to this method can be UV-cured within a markedly very short time and enables, upon curing, the formation of a transparent shrink-and crack-free glass-like product having high optical quality, high thermal stability and good bonding properties. In view of these properties, this hybrid resin can be used in various applications such as electro-optic, microelectronic, stereolithography and biophotonic applications.Type: GrantFiled: December 3, 2009Date of Patent: March 3, 2015Assignee: Soreq Nuclear Research CenterInventor: Raz Gvishi
-
Publication number: 20150028497Abstract: The present invention provides an encapsulant with a base for use in semiconductor encapsulation, for collectively encapsulating a device mounting surface of a substrate on which semiconductor devices are mounted, or a device forming surface of a wafer on which semiconductor devices are formed, the encapsulant comprising the base, an encapsulating resin layer composed of an uncured or semi-cured thermosetting resin formed on one surface of the base, and a surface resin layer formed on the other surface of the base. The encapsulant enables a semiconductor apparatus having a good appearance and laser marking property to be manufactured.Type: ApplicationFiled: July 17, 2014Publication date: January 29, 2015Inventors: Tomoaki NAKAMURA, Toshio SHIOBARA, Hideki AKIBA, Susumu SEKIGUCHI
-
Patent number: 8912669Abstract: Provided are a sealing resin sheet, wherein a clean, smooth and flat ground surface is obtained by grinding after resin sealing, a method for producing an electronic component package using the same, and an electronic component package obtained by the production method. The present invention provides a sealing resin sheet, wherein a ground surface has a mean surface roughness Ra of 1 ?m or less when grinding is performed under conditions of a grind bite peripheral velocity of 1000 m/minute, a feed pitch of 100 ?m and a cut depth of 10 ?m after a heat curing treatment is performed at 180° C. for 1 hour; and a Shore D hardness at 100° C. after the heat curing treatment is 70 or more.Type: GrantFiled: July 3, 2013Date of Patent: December 16, 2014Assignee: Nitto Denko CorporationInventors: Eiji Toyoda, Yusaku Shimizu
-
Patent number: 8895357Abstract: Presented is an integrated circuit packaged at the wafer level wafer (also referred to as a wafer level chip scale package, WLCSP), and a method of manufacturing the same. The WLCSP comprises a die having an electrically conductive redistribution layer, RDL, formed above the upper surface of the die, the RDL defining a signal routing circuit. The method comprises the steps of: depositing the electrically conductive RDL so as to form an electrically conductive ring surrounding the signal routing circuit; and coating the side and lower surfaces of the die with an electrically conductive shielding material.Type: GrantFiled: April 4, 2013Date of Patent: November 25, 2014Assignee: NXP B.V.Inventors: Tonny Kamphuis, Leonardus Antonius Elisabeth van Gemert, Caroline Catharina Maria Beelen-Hendrikx
-
Publication number: 20140332865Abstract: A semiconductor device includes a substrate having an edge, a semiconductor layer provided on a substrate, an electrode pad provided on the semiconductor layer, an inorganic insulating film having a first opening through which an upper surface of the electrode pad is exposed, and a resin film provided on the inorganic insulating film, the resin film having a second opening and a third opening separated from each other, where the upper surface of the electrode pad is exposed through the second opening, where the third opening is located between the second opening and the edge of the substrate, and where a bottom of the third opening is constituted by the resin film or the inorganic insulating film.Type: ApplicationFiled: May 9, 2014Publication date: November 13, 2014Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Hitoshi Haematsu
-
Patent number: 8847415Abstract: Thermosetting resin compositions useful for liquid compression molding encapsulation of a silicon wafer are provided. The so-encapsulated silicon wafers offer improved resistance to warpage, compared to unencapsulated wafers or wafers encapsulated with known encapsulation materials.Type: GrantFiled: December 21, 2012Date of Patent: September 30, 2014Assignee: Henkel IP & Holding GmbHInventors: Jie Bai, Afranio Torres-Filho, Kathryn Bearden
-
Publication number: 20140284821Abstract: A method for densifying thermoplastics, particularly polyimides, for use in conjunction with electronic circuits while producing improved physical properties and a high degree of crystallinity, involves variable frequency microwave (VFM) processing at temperatures typically 100° C. below the glass transition temperature or lower, for times of about 50 to 100 minutes. It is particularly applicable to polymers based on BPDA-PPD, but may also be generally applied to other intentionally designed polyimide structures with the same features. The invention enables the creation of layered structures involving integrated circuits with small feature sizes and overcoatings of polymers with high Tg and other desirable properties.Type: ApplicationFiled: March 22, 2013Publication date: September 25, 2014Inventor: Robert L. Hubbard
-
Patent number: 8786181Abstract: The present invention relates to a blend comprising; a) at least one polymer or copolymer or a mixture of a plurality of polymers and/or copolymers which contain a main chain and a side chain, where at least one side chain contains a structural unit of the following formula (I), the symbols and indices used here are as defined below; b) at least one host molecule which has electron- or hole-transporting functionality, and c) at least one emitter molecule.Type: GrantFiled: October 14, 2011Date of Patent: July 22, 2014Assignees: Merck Patent GmbH, Fraunhofer-Gesellschaft Forschung E.V.Inventors: Thomas Eberle, Rémi Manouk Anémian, Manuel Thesen, Hartmut Krueger, Armin Wedel, Beatrice Salert, Stefanie Kreissl
-
Patent number: 8779607Abstract: A method of manufacturing a device includes forming a covering layer having affinity for a filler to be injected into a space between a first base and a second base, on at least one of the opposing surfaces of the first base and the second base, and then injecting the filler into the space between the first base and the second base.Type: GrantFiled: June 9, 2011Date of Patent: July 15, 2014Assignee: PS4 Luxco S.A.R.L.Inventor: Hiroyuki Ode
-
Patent number: 8749077Abstract: An embodiment 3DIC device includes a semiconductor chip, a die, and a polymer. The semiconductor chip includes a semiconductor substrate, wherein the semiconductor substrate comprises a first edge, and a low-k dielectric layer over the semiconductor substrate. The die is disposed over and bonded to the semiconductor chip. The polymer is molded onto the semiconductor chip and the die. The polymer includes a portion level with the low-k dielectric layer, wherein the portion of the polymer comprises a second edge vertically aligned to the first edge of the semiconductor substrate and a third edge contacting the low-k dielectric layer, wherein the second and the third edges are opposite edges of the portion of the polymer.Type: GrantFiled: July 23, 2013Date of Patent: June 10, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wei Wu, Szu Wei Lu, Jing-Cheng Lin, Shin-Puu Jeng, Chen-Hua Yu
-
Patent number: 8710682Abstract: The present invention provides polyimide polymer materials for passivating semiconductor wafers and methods for fabricating thereof. The present invention further provides a device that includes a semiconductor wafer and a passivating layer disposed on the surface of the wafer, wherein the passivating layer comprises such polyimide polymers.Type: GrantFiled: March 15, 2013Date of Patent: April 29, 2014Assignee: Designer Molecules Inc, Inc.Inventors: Stephen M Dershem, Farhad G Mizori, James T Huneke
-
Patent number: 8710653Abstract: A semiconductor device, includes: a wiring substrate, a stacked body mounted on the wiring substrate, an underfill layer filled into gaps between respective semiconductor chips of the stacked body; and a molding body made up of a molding resin covered and formed at outside of the stacked body and so on. The underfill layer is made up of a cured product of a resin material containing an amine-based curing agent, and the cured product has a Tg of 65° C. or more and 100° C. or less.Type: GrantFiled: February 15, 2012Date of Patent: April 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Masatoshi Fukuda, Hiroshi Watabe
-
Publication number: 20140110859Abstract: Systems and methods are provided for the embedding of thin chips. A well region is generated in a substrate that includes a conductive material disposed on a flexible polymer. The standoff well region can be generated by pattern the conductive material, where the thin chip is embedded in the standoff well region. A cavity can be generated in the polymer layer to form a polymer well region, where the thin chip is embedded in the polymer well region.Type: ApplicationFiled: March 15, 2013Publication date: April 24, 2014Applicant: MC10, Inc.Inventor: MC10, Inc.
-
Patent number: 8698262Abstract: The present invention provides a new type wireless chip that can be used without being fixed on a product. Specifically, a wireless chip can have a new function by a sealing step. One feature of a wireless chip according to the present invention is to have a structure in which an integrated circuit is sealed by films. In particular, the films sealing the integrated circuit have a hollow structure; therefore the wireless chip can have a new function.Type: GrantFiled: August 30, 2005Date of Patent: April 15, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takuya Tsurume, Koji Dairiki, Naoto Kusumoto
-
Patent number: 8643199Abstract: Dendrimer/hyperbranched materials are combined with polyimide to form a low CTE material for use as a dielectric substrate layer or an underfill. In the alternative, ruthenium carbene complexes are used to catalyze ROMP cross-linking reactions in polyimides to produce a class of cross-linkable, thermal and mechanical stable material for use as a dielectric substrate or underfill. In another alternative, dendrimers/hyperbranched materials are synthesized by different methods to produce low viscosity, high Tg, fast curing, mechanically and chemically stable materials for imprinting applications.Type: GrantFiled: January 28, 2009Date of Patent: February 4, 2014Assignee: Intel CorporationInventors: Stephen E. Lehman, Jr., James C. Matayabas, Jr., Saikumar Jayaraman
-
Publication number: 20140015149Abstract: A semiconductor encapsulation adhesive composition comprising (a) an epoxy resin, (b) a curing agent and (c) an antioxidant.Type: ApplicationFiled: July 2, 2013Publication date: January 16, 2014Inventors: Kazutaka Honda, Tetsuya Enomoto, Yuuki Nakamura
-
Publication number: 20140008821Abstract: Provided are a sealing resin sheet, wherein a clean, smooth and flat ground surface is obtained by grinding after resin sealing, a method for producing an electronic component package using the same, and an electronic component package obtained by the production method. The present invention provides a sealing resin sheet, wherein a ground surface has a mean surface roughness Ra of 1 ?m or less when grinding is performed under conditions of a grind bite peripheral velocity of 1000 m/minute, a feed pitch of 100 ?m and a cut depth of 10 ?m after a heat curing treatment is performed at 180° C. for 1 hour; and a Shore D hardness at 100° C. after the heat curing treatment is 70 or more.Type: ApplicationFiled: July 3, 2013Publication date: January 9, 2014Inventors: Eiji Toyoda, Yusaku Shimizu
-
Patent number: 8618674Abstract: A semiconductor device includes a carrier and a first chip attached to the carrier. The semiconductor device includes a sintered insulation material over at least a portion of the carrier and the first chip.Type: GrantFiled: September 25, 2008Date of Patent: December 31, 2013Assignee: Infineon Technologies AGInventors: Ivan Nikitin, Joachim Mahler
-
Patent number: 8587119Abstract: An embodiment of the disclosure includes a conductive feature on a semiconductor die. A substrate is provided. A bond pad is formed over the substrate. The bond pad has a first width. A polyimide layer is formed over the substrate and the bond pad. The polyimide layer has a first opening over the bond pad with a second width. A silicon-based protection layer overlies the polyimide layer. The silicon-based protection layer has a second opening over the bond pad with a third width. The first opening and the second opening form a combined opening having sidewalls to expose a portion of the bond pad. A UBM layer is formed over the sidewalls of combined opening to contact the exposed portion of the bond pad. A conductive feature overlies the UBM layer.Type: GrantFiled: April 16, 2010Date of Patent: November 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Ling Hwang, Yi-Wen Wu, Chung-Shi Liu
-
Publication number: 20130224653Abstract: A novel polyimide which retains the characteristics of polyimides, that is, excellent heat resistance, electrical insulation and chemical resistance, of which dielectric constant is lower than those of the known polyimides, as well as a composition containing the same and a process for producing the same, is disclosed. The polyimide of the present invention is a cross-linked polyimide having a dielectric constant of not more than 2.7, which was produced by polycondensing (a) tetramine(s), (a) tetracarboxylic dianhydride(s) and (an) aromatic diamine(s) in the presence of a catalyst.Type: ApplicationFiled: April 3, 2013Publication date: August 29, 2013Applicant: PI R&D Co., LtdInventor: PI R&D Co., Ltd
-
Publication number: 20130200502Abstract: A method of manufacturing a semiconductor device includes providing a transfer foil. A plurality of semiconductor chips is placed on and adhered to the transfer foil. The plurality of semiconductor chips adhered to the transfer foil is placed over a multi-device carrier. Heat is applied to laminate the transfer foil over the multi-device carrier, thereby accommodating the plurality of semiconductor chips between the laminated transfer foil and the multi-device carrier.Type: ApplicationFiled: February 8, 2012Publication date: August 8, 2013Applicant: INFINEON TECHNOLOGIES AGInventors: Ivan Nikitin, Stefan Landau, Joachim Mahler, Alexander Heinrich, Ralf Wombacher
-
Patent number: 8502401Abstract: A polymeric composition comprising a first polymer chosen from a poly(arylene ether) polymer including polymer repeat units of the following structure: —(O—Ar1—O—Ar2—O—)m—(—O—Ar3—O—Ar4—O)n- where Ar1, Ar2, Ar3, and Ar4 are identical or different aryl radicals, m is 0 to 1, n is 1 m; a polysulfone, a polyimide, a poly(etherketone), a polyurea, a polyurethane, and combinations thereof and a second polymer comprising a per(phenylethynyl) arene polymer derivative. Cured films containing the polymer can exhibit at least one of the following properties: Tg from 160° C. to 180° C., a dielectric constant below 2.7 with frequency independence, and a maximum moisture absorption of less than 0.17 wt %. Accordingly, the polymer is especially useful, for example, in interlayer dielectrics and in die-attach adhesives.Type: GrantFiled: August 10, 2009Date of Patent: August 6, 2013Assignee: Delsper LPInventors: William Franklin Burgoyne, Jr., Mark David Conner, Andrew Francis Nordquist, William Steven Collins
-
Patent number: 8461699Abstract: The positive tone photosensitive composition of the invention comprises an alkali-soluble resin having a phenolic hydroxyl group, a compound producing an acid by light, a thermal crosslinking agent and an acrylic resin. It is possible to provide a positive tone photosensitive composition that can be developed with an aqueous alkali solution, has sufficiently high sensitivity and resolution, and can form a resist pattern with excellent adhesiveness and thermal shock resistance.Type: GrantFiled: December 16, 2009Date of Patent: June 11, 2013Assignee: Hitachi Chemical Company, Ltd.Inventors: Hiroshi Matsutani, Takumi Ueno, Alexandre Nicolas, Yukihiko Yamashita, Ken Nanaumi, Akitoshi Tanimoto
-
Patent number: 8450856Abstract: In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern.Type: GrantFiled: September 22, 2011Date of Patent: May 28, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Un-Byoung Kang, Kwang-chul Choi, Jung-Hwan Kim, Tae Hong Min, Hojin Lee, Minseung Yoon
-
Patent number: 8450840Abstract: Parylene-coated, ultra ruggedized ball grid array electronic components include a substrate with electronic components attached to one surface, and solder balls attached to a second substrate surface through openings formed in the parylene coating.Type: GrantFiled: December 27, 2010Date of Patent: May 28, 2013Assignee: TeleCommunication Systems, Inc.Inventor: Thanh Tran
-
Patent number: 8415812Abstract: The present invention provides polyimide polymer materials for passivating semiconductor wafers and methods for fabricating thereof. The present invention further provides a device that includes a semiconductor wafer and a passivating layer disposed on the surface of the wafer, wherein the passivating layer comprises such polyimide polymers.Type: GrantFiled: September 2, 2010Date of Patent: April 9, 2013Assignee: Designer Molecules, Inc.Inventors: Stephen M Dershem, Farhad G Mizori, James T Huneke
-
Patent number: 8373287Abstract: A polymeric composition comprising a first polymer chosen from a poly(arylene ether) polymer including polymer repeat units of the following structure: —(O—Ar1—O—Ar2—O—)m—(—O—Ar3—O—Ar4—O)n- where Ar1, Ar2, Ar3, and Ar4 are identical or different aryl radicals, m is 0 to 1, n is 1 m; a polysulfone, a polyimide, a poly(etherketone), a polyurea, a polyurethane, and combinations thereof and a second polymer comprising a per(phenylethynyl) arene polymer derivative. Cured films containing the polymer can exhibit at least one of the following properties: Tg from 160° C. to 180° C., a dielectric constant below 2.7 with frequency independence, and a maximum moisture absorption of less than 0.17 wt %. Accordingly, the polymer is especially useful, for example, in interlayer dielectrics and in die-attach adhesives.Type: GrantFiled: August 10, 2009Date of Patent: February 12, 2013Assignee: Greene, Tweed IP, Inc.Inventors: William Franklin Burgoyne, Jr., Mark David Conner, Andrew Francis Nordquist, William Steven Collins
-
Patent number: 8330264Abstract: This invention discloses an electronic package for containing a vertical semiconductor chip that includes a laminated board having a via connector and conductive traces distributed on multiple layers of the laminated board connected to the via connector. The semiconductor chip having at least one electrode connected to the conductive traces for electrically connected to the conductive traces at a different layer on the laminated board and the via connector dissipating heat generated from the vertical semiconductor. A ball grid array (BGA) connected to the via connector functioning as contact at a bottom surface of the package for mounting on electrical terminals disposed on a printed circuit board (PCB) wherein the laminated board having a thermal expansion coefficient in substantially a same range the PCB whereby the BGA having a reliable electrical contact with the electrical terminals.Type: GrantFiled: April 24, 2012Date of Patent: December 11, 2012Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Ming Sun, Yueh Se Ho
-
Publication number: 20120299203Abstract: One aspect of the present invention provides a polymer having repeating units represented by the formulas (1-1), (1-2) and (1-3) and weight-average molecular weight of from 3,000 to 500,000, as determined by GPC using tetrahydrofuran as a solvent, reduced to polystyrene. Another aspect of the present invention provides an adhesive composition comprising (A) the polymer, (B) a thermosetting resin, and (C) a compound having flux activity. Further, the present invention provides an adhesive sheet having an adhesive layer made of the adhesive composition, a protective material for a semiconductor device, which has the adhesive layer, and a semiconductor device having a cured product obtained from the adhesive composition.Type: ApplicationFiled: May 11, 2012Publication date: November 29, 2012Applicant: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Michihiro SUGO, Kazunori KONDO
-
Patent number: 8310069Abstract: The symbolization of a semiconductor device (100) is incorporated in a thin sheet (130) attached to the top of the device, facing outwardly with its bare surface. The material of the sheet (about 1 to 10 ?m thick) includes regions of a first optical reflectivity and a first color, and regions (133) of a second optical reflectivity and a second color, which differ from, and contrast with, the first reflectivity and color. Preferred choices for the sheet material include the compound o-cresol novolac epoxy and the compound bisphenol-A, more preferably with the chemical imidazole added to the film material. A preferred embodiment of the invention is a packaged device with a semiconductor chip a (101) connected to a substrate (102); the connection is achieved by bonding wires (111) forming an arch with a top 111a. The chip, the wire arches, and the substrate are embedded in an encapsulation material (120), which borders on the attached top sheet so that the arch tops touch the border (131).Type: GrantFiled: September 16, 2008Date of Patent: November 13, 2012Assignee: Texas Instruements IncorporatedInventors: Kazuaki Ano, Wen Yu Lee
-
Patent number: 8304924Abstract: The invention provides a composition for sealing a semiconductor, the composition being able to form a thin resin layer, suppress the diffusion of a metal component to a porous interlayer dielectric layer, and exhibit superior adherence with respect to an interconnection material. The composition for sealing a semiconductor contains a resin having two or more cationic functional groups and a weight-average molecular weight of from 2,000 to 100,000; contains sodium and potassium each in an amount based on element content of not more than 10 ppb by weight; and has a volume average particle diameter, measured by a dynamic light scattering method, of not more than 10 nm.Type: GrantFiled: May 28, 2010Date of Patent: November 6, 2012Assignee: Mitsui Chemicals, Inc.Inventors: Shoko Ono, Kazuo Kohmura
-
Publication number: 20120228784Abstract: Disclosed is a semiconductor device configured by encapsulating a semiconductor element, partially or entirely covered with a polyimide, using an epoxy resin composition for encapsulating semiconductor device which contains an epoxy resin (A), a phenol resin (B), a curing accelerator (C), an inorganic filler (D), and a silane coupling agent (E) represented by the formula (1): (in the formula (1), each of R1, R2 and R3 represents a C1-4 hydrocarbon group, all of them may be the same or different from each other, and n represents an integer from 0 to 2), and/or a hydrolytic condensate thereof.Type: ApplicationFiled: November 11, 2010Publication date: September 13, 2012Inventor: Tatsu Suzuki
-
Patent number: 8203221Abstract: There is provided a semiconductor device which has been improved in adhesion between leads and a sealing resin (molding resin), and thus does not undergo peeling therebetween, and has high reliability.Type: GrantFiled: August 14, 2009Date of Patent: June 19, 2012Assignee: Hitachi, Ltd.Inventor: Tomio Iwasaki
-
Patent number: 8178972Abstract: A semiconductor device is obtained, in which excellent characteristics are achieved, the reliability is improved, and an SiC wafer can also be used for the fabrication. A plurality of Schottky-barrier-diode units 10 is formed on an SiC chip 9, and each of the units 10 has an external output electrode 4 independently of each other. Bumps 11 (the diameter is from several tens to several hundreds of ?m) are formed only on the external output electrodes 4 of non-defective units among the units 10 formed on the SiC chip 9, meanwhile bumps are not formed on the external output electrodes 4 of defective units in which the withstand voltage is too low, or the leakage current is too much.Type: GrantFiled: November 17, 2010Date of Patent: May 15, 2012Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Naoki Yutani
-
Patent number: 8154124Abstract: A semiconductor chip has a main surface, a back surface and a plurality of side surfaces. A plurality of electrodes is provided on the main surface of the semiconductor chip so as to be arranged in a plurality of lines. An insulating film is formed on the main surface of the semiconductor chip so as to expose at least one of the plurality of electrodes. A plurality of leads are formed on the insulating film, each of the plurality of leads having a first end and a second end, and the first end of the lead being connected to the one of the plurality of electrodes. A base resin film is formed on the insulting film and the plurality of leads, the base resin film having a plurality of electrodes holes exposing a part of the second end of each of the leads and a device hole in which the first end of the lead and the one of the plurality of electrodes are located.Type: GrantFiled: December 17, 2007Date of Patent: April 10, 2012Assignee: Oki Electric Industry Co., Ltd.Inventors: Yoshikazu Takahashi, Masami Suzuki, Masaru Kimura
-
Patent number: 8120153Abstract: A cost-effective, ultra-compact, hybrid power module packaging system and method for making allows device operation in conventional and high temperature ranges over 300° C. Double metal leadframes are directly bonded to the front- and backside of semiconductor chips, and injection-molded high temperature polymer materials encapsulate the module. The invention eliminates the use of unreliable metal wirebonds and solders joints, and expensive aluminum nitride ceramic substrates commonly used in conventional and high temperature hybrid power modules. Advantages of the new power modules include high current carrying capability, low package parasitic impedance, low thermo-mechanical stress under high temperature cycling, low package thermal resistance (double-side cooling), modularity for easy system-level integration, and low-cost manufacturing of devices compatible with current electronic packaging industry. A first embodiment uses molybdenum leadframes for operation in temperatures over 300° C.Type: GrantFiled: September 14, 2006Date of Patent: February 21, 2012Assignee: University of Central Florida Research Foundation, Inc.Inventor: Zheng John Shen
-
Publication number: 20120038067Abstract: The disclosure provides methods and materials suitable for use as encapsulation barriers in electronic devices. In one embodiment, for example, there is provided an electroluminescent device or other electronic device encapsulated by alternating layers of a silicon-containing bonding material and a ceramic material. The encapsulation methods provide, for example, electronic devices with increased stability and shelf-life. The invention is useful, for example, in the field of microelectronic devices.Type: ApplicationFiled: March 4, 2009Publication date: February 16, 2012Inventors: Yigal D. Blum, William Siu-Keung Chu, David Brent MacQueen, Yijian Shi
-
Publication number: 20110260343Abstract: A polymeric composition comprising a first polymer chosen from a poly(arylene ether) polymer including polymer repeat units of the following structure: —(O—Ar1—O—Ar2—O—)m—(—O—Ar3—O—Ar4—O)n- where Ar1, Ar2, Ar3, and Ar4 are identical or different aryl radicals, m is 0 to 1, n is 1 m; a polysulfone, a polyimide, a poly(etherketone), a polyurea, a polyurethane, and combinations thereof and a second polymer comprising a per(phenylethynyl) arene polymer derivative. Cured films containing the polymer can exhibit at least one of the following properties: Tg from 160° C. to 180° C., a dielectric constant below 2.7 with frequency independence, and a maximum moisture absorption of less than 0.17 wt %. Accordingly, the polymer is especially useful, for example, in interlayer dielectrics and in die-attach adhesives.Type: ApplicationFiled: August 10, 2009Publication date: October 27, 2011Applicant: AIR PRODUCTS AND CHEMICALS, INC.Inventors: William Franklin Burgoyne, JR., Mark David Conner, Andrew Francis Nordquist, William Steven Collins
-
Patent number: 8017245Abstract: A composition for preparing an organic insulator, the composition comprising (i) at least one organic-inorganic hybrid material; (ii) at least one organometallic compound and/or organic polymer; and (iii) at least one solvent for dissolving the above two components, so that an organic insulator using the same has a low threshold voltage and driving voltage, and high charge carrier mobility and Ion/Ioff ratio, thereby enhancing insulator characteristics. Further, the preparation of organic insulating film can be carried out by wet process, so that simplification of the process and cut of cost are achieved.Type: GrantFiled: May 13, 2005Date of Patent: September 13, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sang Yoon Lee, Jong Jin Park, Yi Yeol Lyu, Bon Won Koo, Young Hun Byun, Eun Mi Seo
-
Patent number: 8004078Abstract: Provided is an adhesive composition for a semiconductor device. For example, the adhesive composition comprises a binder resin and a silicon carbide filler. The silicon carbide filler has relatively high thermal conductivity and a relatively low coefficient of thermal expansion (CTE). Accordingly, the adhesive composition containing the silicon carbide filler exhibits improved heat dissipation performance and electrical performance due to high thermal conductivity and shows inhibition of delamination or cracking of semiconductor devices due to low CTE. The silicon carbide has high thermal conductivity, but is electrically non-conductive. Therefore, an electrically conductive adhesive can be obtained by additional incorporation of a silver (Ag) filler into the binder resin.Type: GrantFiled: March 17, 2009Date of Patent: August 23, 2011Assignee: Amkor Technology, Inc.Inventors: Jae Kyu Song, Bong Chan Kim, Min Yoo