Abstract: A semiconductor device comprises a semiconductor chip in which a multilayer interconnection structure having an interlayer insulation film with a low relative dielectric constant is formed on a silicon substrate and a sealing resin layer which coats the semiconductor chip. The sealing resin layer meets, in coefficient of linear expansion (?) at room temperature, Young's modulus (E) at room temperature and thickness (h) thereof, a relationship of the following formula (1) E<0.891/{(???s)2×h}??(1) where E represents the Young's modulus (GPa) of the sealing resin at room temperature; ? represents the coefficient of linear expansion (ppm) of the sealing resin at room temperature; ?s represents the coefficient of linear expansion (3.5 ppm) of the silicon substrate; and h represents the thickness (m) of the sealing resin on the device-formed surface of the semiconductor chip.

Abstract: A highly moisture-sensitive element and method of making such element includes an encapsulation enclosure encapsulating all of the highly moisture-sensitive electronic devices on a substrate and a sealing material positioned between the substrate and the encapsulation enclosure to form a complete seal between the substrate and the encapsulation enclosure around each highly moisture-sensitive electronic device or around groups of highly moisture-sensitive electronic devices.

Abstract: A system for chip packaging includes an adamantoid packaging composition. The adamantoid composition ameliorates the CTE mismatch that typically exists between a packaged die and a resin-impregnated fiberglass mounting substrate. In an embodiment, the system includes a packaging composition that alone exhibits a CTE that is characteristic of an inorganic-filled underfill composite previously known. An embodiment is also directed to the assembly of a chip package that uses an adamantoid packaging composition.

Abstract: There is disclosed a coating material formulation for layering a plurality of electrodes to provide a substrate for the electrochemical synthesis of organic oligomers. Specifically, there is disclosed a coating layer of from about 0.5 to about 100 microns thick and is composed of a mixture of controlled porosity glass (CPG) particles having an average particle size of from about 0.25 to about 25 microns, and a thickening agent.

Abstract: A liquid epoxy resin composition is provided comprising (A) a liquid epoxy resin, (B) an optional curing agent, (C) a curing accelerator, (D) an inorganic filler, and (E) acrylic submicron particles of core-shell structure formed of polymers or copolymers comprising an alkyl acrylate and/or alkyl methacrylate as a monomeric component, the core having a Tg of up to ?10° C., the shell having a Tg of 80-150° C. The composition is adherent to surfaces of silicon chips, especially polyimide resins and nitride film and useful as sealant for flip chip type semiconductor devices.

Abstract: A substrate and an organic electroluminescence device employing the substrate are provided. The substrate has at least one non-continuous photo-resist coating layer formed on at least one surface of a supporting substrate and the non-continuous photo-resist coating has a plurality of continuous portions. The continuous portions may have high surface energy areas and low surface energy areas. A second photo-resist coating layer is used to at least temporarily overlap the continuous portion which corresponds to the high surface energy area in order to form the low surface energy area.

Abstract: The invention relates to a wiring board comprising a board having an electrode and being coated with an insulation layer with a hole for exposing the electrode; a wiring comprising a Cr or Ti layer, which is connected to the electrode and closely contacts with the insulation layer, and of a Cu layer which is closely contacts with the Cr or Ti layer; a protective film which covers the wiring and is provided with another hole for soldering; and a solder for the outer connection which is mounted in the both holes and brought to diffuse into the Cu layer to produce an alloy, and brought to reach the Cr or Ti layer thereby connecting the solder to the Cr or Ti layer.

Abstract: Disclosed are a semiconductor package device and a method for fabricating the semiconductor package device. The semiconductor package has a semiconductor chip including a plurality of bonding pads having a microscopic size and aligned at a minute interval, a planar layer formed on the semiconductor chip so as to expose the bonding pads, metal patterns formed on the planar layer and having a size larger than a size of the bonding pads in such a manner that at least some parts of the metal patterns are connected to the bonding pads and a seed metal layer interposed between the planar layer and the metal patterns. When the bonding pads have microscopic size and aligned at a minute interval, a wire-bonding process is carried out by using the metal patterns having the size larger than the size of the bonding pads and covering the bonding pad region, as a connection part to the bonding pads. Thus, the bonding pad region is reduced by 50 to 80% so that the number of chips in the semiconductor chip is increased.

Abstract: A method for underfilling and encapsulating flip-chip-configured semiconductor devices mounted on a carrier substrate using stereolithography (STL) to form, in situ, at least semisolid dam structures of photopolymeric material about the devices to entrap liquid, unpolymerized resin between the devices and substrate is disclosed. Prior to the STL process, the carrier substrate and mounted devices are immersed in the liquid polymeric resin, optionally with vibratory energy, to purge contaminants from between the device and substrate, and to fill spaces between the semiconductor devices and carrier substrate with the liquid resin.

Abstract: A solid-state image pickup apparatus includes a solid-state image pickup device having a layer of microlenses above a color filter. The solid-state image pickup device is mounted on a side of a flexible printed circuit board by flip-chip bonding, opposite the opening. An adhesive in a gap between the solid-state image pickup device and the flexible printed circuit board strengthens the apparatus. The distance between the edge of the microlens layer and the edge of the flexible printed circuit board defining the opening and nearest to the microlens layer is 2.5 to 10 times wider than the gap between the solid-state image pickup device and the flexible printed circuit board.

Abstract: A semiconductor device includes a semiconductor chip generating heat, a pair of heat sinks, which face each other, to conduct heat from both surfaces of the chip, a pair of compressible insulating sheets, and a mold resin covering the chip, the heat sinks, and the sheets such that the sheets are exposed from the surface of the resin. The mold resin is prevented from covering the outer surfaces of the heat sinks, which are pressed by mold parts, and breakage of the chip is avoided during molding. The plates are insulated by the sheets, so no dedicated insulating sheets for the heat sinks are needed after the device is completed.

Abstract: A flexible skin formed of silicon islands encapsulated in a polyimide film. The silicon islands preferably include a MEMS device and are connected together by a polyimide film (preferably about 1–100 ?m thick). To create the silicon islands, silicon wafers are etched to a desirable thickness (preferably about 10–500 ?m) by Si wet etching and then patterned from the back side by reactive ion etching (RIE).

Abstract: A semiconductor device includes a semiconductor chip generating heat, a pair of heat sinks, which face each other, to conduct heat from both surfaces of the chip, a pair of compressible insulating sheets, and a mold resin covering the chip, the heat sinks, and the sheets such that the sheets are exposed from the surface of the resin. The mold resin is prevented from covering the outer surfaces of the heat sinks, which are pressed by mold parts, and breakage of the chip is avoided during molding. The plates are insulated by the sheets, so no dedicated insulating sheets for the heat sinks are needed after the device is completed.

Abstract: A method and apparatus for an electronic component package of a passive component using wafer level processing;is provided. Posts are formed on the active side of the substrate of an electronic component. A conductive layer leads the contact areas of the electronic component to the tops of the posts. The conductive layer on the top of the posts acting as leads, attaching to traces on a printed circuit board.

Abstract: Apparatus and methods are provided wherein the reflowable electrically conductive interconnect material coupling the interconnects and/or land-side components of a microelectronic package is protected from elevated temperatures, such as those associated with reflow processes and environments which exceed the melting temperature of the interconnect material. One embodiment of the method provides covering the interconnect material about the interconnects and/or land-side components with heat-resistant curable material which protects the interconnect material from the elevated temperature and provides structural support to the interconnects and/or land-side components at the elevated temperature.

Abstract: In accordance with the present invention, a chip scale package (CSP) is manufactured at wafer-level. The CSP includes a chip, a conductor layer for redistribution of the chip pads of the chip, one or two insulation layers and multiple bumps, which are interconnected to respective chip pads by the conductor layer and are the terminals of the CSP. In addition, in order to improve the reliability of the CSP, a reinforcing layer, an edge protection layer and a chip protection layer are provided. The reinforcing layer absorbs stress applied to the bumps when the CSP is mounted on a circuit board and used for an extended period, and extends the life of the bumps, and thus, the life of the CSP. The edge protection layer and the chip protection layer prevent external force from damaging the CSP. After forming all elements constituting the CSP on the semiconductor wafer, the semiconductor wafer is sawed to produce individual CSPs.

Abstract: A semiconductor device having bump electrodes electrically connected to connection pads formed on a semiconductor chip of the semiconductor device, tips of the bump electrodes exposing at a surface of a sealing resin film formed on a surface of the semiconductor chip, wherein the sealing resin film is comprised of a low-elastic resin layer formed on the surface of the semiconductor chip and a high-elastic resin layer formed on a surface of the low-elastic resin layer and having an elastic coefficient higher than that of the low-elastic resin layer, a thickness of the high-elastic resin layer being between 5 ?m and 45 ?m.

Abstract: The electronic component has a semiconductor chip embedded in a plastic compound. The electronic component is produced by first producing a number of electronic components on a panel and subsequent dicing into single electronic components. The semiconductor chip of this component is disposed on a substrate the includes or is entirely formed of plastic and it is embedded in a plastic package molding compound. The plastic of the substrate has a glass transition temperature range which is lower than the glass transition temperature range of the plastic package molding compound.

Abstract: An apparatus for enclosing logic chips includes a substrate upon which a logic chip is mounted and a mold cap disposed upon the substrate and covering the logic chip. The mold cap includes at least one extension of sufficient size and shape to provide structural support to a corner section of the substrate.

Abstract: In an optoelectronic component assembly and a method for the production thereof, the optoelectronic component assembly includes an optoelectronic component arranged on a support element, which is surrounded by a closed dam. An encapsulation is arranged in an inner area of the dam, which encapsulates the optoelectronic component and includes two sealing materials. The inner area of the dam may be filled with a first sealing material up to the top edge of the optoelectronic component. The inner area of the dam located above the optoelectronic component is filled with a second transparent sealing material at least in one area of the window.

Abstract: The present invention provides a resin-encapsulated semiconductor apparatus comprising a semiconductor device having a ferroelectric film and a surface-protective film, and an encapsulant member comprising a resin; the surface-protective film being formed of a polyimide. The present invention also provides a process for fabricating a resin-encapsulated semiconductor apparatus, comprising the steps of forming a film of a polyimide precursor composition on the surface of a semiconductor device having a ferroelectric film; heat-curing the polyimide precursor composition film to form a surface-protective film formed of a polyimide; and encapsulating, with an encapsulant resin, the semiconductor device on which the surface-protective film has been formed. The polyimide may preferably have a glass transition temperature of from 240° C. to 400° C. and a Young's modulus of from 2,600 MPa to 6 GPa. The curing may preferably be carried out at a temperature of from 230° C. to 300° C.

Abstract: A method for underfilling and encapsulating flip-chip configured semiconductor devices mounted on a carrier substrate using stereolithography (STL) to form, in situ, at least semisolid dam structures of photopolymeric material about the devices to entrap liquid, unpolymerized resin between the devices and substrate is disclosed. Prior to the STL process, the carrier substrate and mounted devices are immersed in the liquid polymeric resin, optionally with vibratory energy, to purge contaminants from between the device and substrate, and to fill spaces between the semiconductor devices and carrier substrate with the liquid resin.

Abstract: An extended length light emitting diode suitable for auto-insertion including an extended LED body region serving as a standoff or spacer to provide supported spacing from a circuit board to extend the LED die through a faceplate for suitable viewing and to serve as a structure through and about which the lower body portion of the LED and the LED leads can be stabilized and sealed to a printed circuit board. An alternative embodiment includes structure for sealing an LED to a faceplate.

Abstract: A microelectronic device package and method for manufacture. In one embodiment, the device package can include a support member having a first surface, a second surface facing opposite the first surface and a cavity extending through the support member from the first surface to the second surface. A microelectronic device is disposed in the cavity and is supported in the cavity with a removable retention member. The microelectronic device is electrically coupled to the support member and is partially surrounded with an encapsulating material. The removable retention member is then removed to expose a surface of the microelectronic device. Accordingly, the package can have a low profile because the encapsulating material does not surround one of the microelectronic device surfaces. In one embodiment, a heat conductive material can be engaged with the exposed surface of the microelectronic device to increase the rate at which heat is transferred away from the microelectronic device.

Abstract: A low elasticity layer (20) having an opening in an electrode arranging area where element electrodes are disposed is provided on a main surface of a semiconductor substrate (10). On the low elasticity layer (20), lands (32) serving as external electrodes are disposed, and pads (30) on the element electrodes, the lands (32) and metal wires (31) for connecting them are integrally formed as a metal wiring pattern (33). A solder resist film (50) having an opening for exposing a part of each land (32) is formed, and a metal ball (40) is provided on the land (32) in the opening. The low elasticity layer (20) absorbs thermal stress and the like caused in heating or cooling the semiconductor device, so as to prevent disconnection of the metal wires (31).

Abstract: A semiconductor device comprises a semiconductor element, a heat sink soldered to one surface of the semiconductor element, and a heat sink soldered to an opposite surface of the semiconductor element. The semiconductor element is provided with a wiring layer. The wiring layer is covered with an insulating protective film. The protective film is an organic film. The thickness of the wiring layer and that of the protective film are assumed to be t1 and t2, respectively. The wiring layer and the protective film are formed so as to establish a relationship of t1<t2. An elastic modulus of the protective film at room temperature is adjusted to 1.0-5.0 GPa and a thermal expansion coefficient of the protective film is adjusted to 35-65×10−6/° C. Even under a thermal stress the semiconductor device can diminish a short-circuit defect of the wiring layer.

Abstract: A semiconductor device has a semiconductor wafer having sensing portions exposed on a surface thereof and an adhesive sheet attached to the semiconductor wafer as a protective cap to cover the sensing portions. The adhesive sheet is composed of a flat adhesive sheet and adhesive disposed generally on an entire surface of the adhesive sheet. Adhesion of the adhesive is selectively reduced by UV irradiation to have adhesion reduced regions, and the adhesion reduced regions face the sensing portions. The protective cap can be produced with high productivity, and securely protect the sensing portions when the semiconductor wafer is diced and is transported.

Abstract: Die attach adhesives and methods for their use, along with the devices that are obtained by the use of the methods. Using semiconductor chips as an example, the adhesives and the method for using them provides an interface between a chip (die) and the chip support. The method includes creating a space between the chip and the chip support of a given sized opening by using inorganic insulator particles having an average particle size of 1 &mgr;m to 1000 &mgr;m and a major axis to minor axis ratio of about 1.0 to 1.5.

Abstract: A light-emitting element is mounted in a cup-like portion formed on a substrate and a case. The cup-like portion is filled with a sealing member made of a light-transmissible resin. A layer made of a material having a refractive index lower than that of the sealing member is provided between the sealing member and a surface of the case.

Abstract: A substrate for semiconductor device which is formed of a material that can be cut into separate pieces and has mounting regions for a plurality of semiconductor chips, and at least one hole is formed therein at a position of intersection between a plurality of cutting lines for cutting the substrate into a plurality of individual products.

Abstract: A solid-state image pickup device in which no warp occurs in a solid-state image pickup element chip is provided. A solid-state image pickup device, including a solid-state image pickup element chip on which a plurality of solid-state image pickup elements are mounted, a wiring substrate electrically connected to the solid-state image pickup element chip and adapted to transmit signals from each one of a plurality of solid-state image pickup elements, and a protection cap provided on a light incident side of the solid-state image pickup element chip and adapted to protect the solid-state image pickup element chip, is characterized in that the solid-state image pickup element chip is formed on a substrate with a thermal expansion coefficient equal to that of the protection cap, and the substrate and the protection cap are sealed with a sealing resin.

Abstract: A semiconductor device includes a semiconductor structure including a semiconductor substrate having an integrated circuit portion, and a plurality of connecting pads connected to the integrated circuit portion. A plurality of distributing lines are formed on the semiconductor structure, connected to the connecting pads, and have connecting pad portions. An encapsulating layer made of a resin is formed on the semiconductor structure and upper surface of the distributing lines. A copper oxide layer is formed on at least a surface of each of the distributing lines except for the connecting pad portion.

Abstract: Provided is an encapsulant resin for a semiconductor that effectively functions even with a relatively small amount of an additive. The encapsulant resin for a semiconductor is characterized in that the additive has a concentration gradient in the direction of thickness of the encapsulant resin. Specifically, the concentration gradient of the additive is established in the direction of thickness of the encapsulant resin by stacking at least two types of organic polymer resins containing different contents of the additive to form the encapsulant resin or by applying an electric field to the encapsulant resin to effect electrophoresis of the polar additive in the encapsulant resin.

Abstract: A flexible monolithic integrated circuit which is essentially formed from flexible circuit elements, connecting elements between the flexible circuit elements, and a flexible coating which comprises at least one layer of a coating material comprising a polymer, is suitable as a small and convenient integrated circuit for electronic devices on flexible data carriers for the logistic tracking of objects and persons. The invention also relates to a method of manufacturing a flexible integrated monolithic circuit whereby integrated monolithic circuit elements and connecting elements are formed in and on a semiconductor substrate, the main surface of the integrated circuit elements facing away from the semiconductor substrate are coated with a polymer resin, and the semiconductor substrate is removed. The method is based on conventional process steps in semiconductor technology and leads to a flexible integrated monolithic circuit in a small number of process steps.

Abstract: There are provided a high density and low manufacturing cost wiring board with high reliability in connection, a semiconductor device and a producing method therefor. The invention relates to a wiring board comprising a board having an electrode and being coated with an insulation layer with a hole for exposing the electrode; a wiring consisting of a Cr or Ti layer, which is connected to the electrode and closely contacts with the insulation layer, and of a Cu layer which is closely contacts with the Cr or Ti layer; a protective film which covers the wiring and is provided with another hole for soldering; and a solder for the outer connection which is mounted in the both holes and brought to diffuse into the Cu layer to produce an alloy, and brought to reach the Cr or Ti layer thereby connecting the solder to the Cr or Ti layer.

Abstract: Stiffeners for tapes, films, or other connective structures that are configured to be secured to a semiconductor device component, such as a semiconductor die or substrate, by tape-automated bonding processes. The stiffeners are fabricated by stereolithographic processes and may include one layer or two or more superimposed, contiguous, mutually adhered layers. The stiffeners are configured to prevent torsional flexion or bending of the connective structure to which they are to be secured. The stiffeners may include apertures through which intermediate conductive elements or other structures secured to the connective structure may be exposed or protrude. Stiffeners that reinforce sprocket or indexing holes in a connective structures are also disclosed.

Abstract: Electronic devices of improved reliability having a substrate of electrically insulating material, further an integrated circuit chip with a periphery and a surface. Using a layer of polymeric material, the chip surface is mounted on the substrate surface. The polymeric material protrudes beyond the chip periphery and spreads some distance along the substrate surface. A metal layer is on the substrate surface, this layer is shaped as a band around the chip periphery; the band has an inner edge near the chip periphery, and an outer edge near the contour of the polymer protrusion. This metal band serves as a guard ring to stop any nascent crack propagating in the polymer protrusion.

Abstract: The present invention provides a resin-encapsulated semiconductor apparatus comprising a semiconductor device having a ferroelectric film and a surface-protective film, and an encapsulant member comprising a resin; the surface-protective film being formed of a polyimide. The present invention also provides a process for fabricating a resin-encapsulated semiconductor apparatus, comprising the steps of forming a film of a polyimide precursor composition on the surface of a semiconductor device having a ferroelectric film; heat-curing the polyimide precursor composition film to form a surface-protective film formed of a polyimide; and encapsulating, with an encapsulant resin, the semiconductor device on which the surface-protective film has been formed. The polyimide may preferably have a glass transition temperature of from 240° C. to 400° C. and a Young's modulus of from 2,600 MPa to 6 GPa. The curing may preferably be carried out at a temperature of from 230° C. to 300° C.

Abstract: Devices and method of fabrication thereof are disclosed. A representative device includes one or more lead packages. The lead packages include a substrate including a plurality of die pads, an overcoat polymer layer, a plurality of sacrificial polymer layers disposed between the substrate and the overcoat polymer layer, and a plurality of leads. Each lead is disposed upon the overcoat polymer layer having a first portion disposed upon a die pad. The sacrificial polymer layer can be removed to form one or more air-gaps.

Abstract: A surface acoustic wave device includes a SAW element that is mounted on a substrate. Grooves are provided in the substrate at the outer periphery of the SAW element, and a flexible resin layer is provided at the inner portion of the grooves so as to cover the SAW element. An outer resin layer that is harder than the flexible resin layer is provided at the exterior of the flexible resin layer. This configuration facilitates reduction in size and profile of the surface acoustic wave device, contributes to reduction in cost, and exhibits high environmental resistance.

Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a conductive structure that couples a first substrate to a second substrate. The first substrate may include a chip or a module. The second substrate may include a chip carrier or a circuit card. Thus, the present invention encompasses such coupling as chip to chip carrier, chip to circuit card, and module to circuit card. The conductive structure includes a first conductive body and a second conductive body. The first conductive body is attached to the first substrate and the second conductive body is attached to the second substrate. The first conductive body may include a solder bump, while the second conductive body may include a eutectic alloy, such as a eutectic alloy lead and tin. Alternatively, the second conductive body may include a non-eutectic alloy whose melting point is below the melting point of the first conductive body.

Abstract: A semiconductor device which does not require solder resist to be applied to the surface. Leads 54 are formed on one surface of a polyimide film 10, external connection terminals 11 are formed on the leads 54 to project from the other surface of the polyimide film 10 through via holes 30, and an IC chip 15 is adhered to the first surface, so that the leads 54 are covered by the IC chip 15, and the application of a solder resist can be omitted.

Abstract: A semiconductor device including a substrate, a mesa post overlying the substrate and having a substantially cylindrical shape, a resin member surrounding the mesa post and a stress moderating member received in the mesa post for moderating stress between the mesa post and the resin member. The stress applied to the mesa post is reduced because the entire volume of the resin member is divided by the stress moderating member and each of the divided resin members reduces the stress.

Abstract: A composition for sealing a semiconductor device contains polyphenylene sulfide wherein a line expansion coefficient at 150° C. to 200° C. is 4.75×10−5 [1/° C.] or less, a line thermal expansion coefficient at 80 to 130° C. is 6.0×10−5 [1/° C.] or less, and a line expansion coefficient ratio between the flow direction and a normal direction of the flow direction is 0.55 or more.

Abstract: A solventless non-filler underfill material for COF mounting comprising an organic material, which is used to fill the gap between an FPC having a polyimide film substrate and a copper circuit layer having a thickness of 9 &mgr;m or smaller and an IC chip mounted on the FPC, exhibits such adhesion as to destroy a silicon wafer in a polyimide film/silicon wafer adhesion test, and provides a cured film having a tensile modulus of 150 kg/mm2 or less.

Abstract: An abrasion-proof and static-erasing coating is formed on the contact surface of a contact image sensor. The coating comprises a first film having a high hardness and a low conductivity, a second film formed on the first film and having a low hardness and a high conductivity, and a third film having a high hardness and a high resistivity providing an abrasion-proof insulating external surface.

Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.

Abstract: An encapsulant molding technique used in chip-on-board encapsulation wherein an oxidizable metal layer is patterned on a substrate and the oxidizable metal layer is oxidized to facilitate removal of unwanted encapsulant material. The oxidizable metal layer which adheres to the substrate is applied over a specific portion of the substrate. The oxidizable metal layer is oxidized to form a metal oxide layer which does not adhere to encapsulant materials.

Abstract: Microelectronic assemblies are encapsulated using disposable frames. The microelectronic assemblies are disposed within an aperture defined by a frame. The aperture is covered by top and bottom sealing layers so that the frame and sealing layers define an enclosed space encompassing the assemblies. The encapsulant is injected into this closed space. The frame is then separated from the encapsulation fixture and held in a curing oven. After cure, the frame is cut apart and the individual assemblies are severed from one another. Because the frame need not be held in the encapsulation fixture during curing, the process achieves a high throughput.

Abstract: A semiconductor device thinner than the past and improved in reliability of electrical connection between semiconductor chips and an interconnection substrate including a polyimide film (insulating plastic film) formed with stud bump through holes, an interconnection pattern formed on one surface of the polyimide film and covering openings of the stud bump through holes at least at that one surface, a first semiconductor chip flip-chip bonded to the interconnection pattern, a second semiconductor chip flip-chip bonded to the other surface of the polyimide film so as to be electrically connected with the interconnection pattern through the stud bump through holes, and solder bumps (external connection terminals) and a method for production of the same by fewer steps than in the past.