Abstract: A semiconductor. device comprises a semiconductor chip on which a plurality of grooves are defined, thus acting as a resisting member, the effect of which is to prevent the semiconductor chip from bending. Consequently, the thickness of the lower portion of the plastic layer becomes greater, thereby preventing cracks from occurring on the semiconductor chip.

Abstract: A tape having implantable conductive lands, which realizes a new structure in which an organic rigid substrate is removed from a semiconductor package in a semiconductor packaging process, and a method for manufacturing the tape are provided. The tape includes a tape film, which can be detached from a semiconductor package after an encapsulation process and serves as a general rigid substrate until the encapsulation process is completed, and implantable conductive lands adhering to the tape film.

Abstract: A simplified process for flip-chip attachment of a chip to a substrate is provided by pre-coating the chip with an encapsulant underfill material having separate discrete solder columns therein to eliminate the conventional capillary flow underfill process. Such a structure permits incorporation of remeltable layers for rework, test, or repair. It also allows incorporation of electrical redistribution layers. In one aspect, the chip and pre-coated encapsulant are placed at an angle to the substrate and brought into contact with the pre-coated substrate, then the chip and pre-coated encapsulant are pivoted about the first point of contact, expelling any gas therebetween until the solder bumps on the chip are fully in contact with the substrate. There is also provided a flip-chip configuration having a complaint solder/flexible encapsulant understructure that deforms generally laterally with the substrate as the substrate undergoes expansion or contraction.

Abstract: There are provided a high density and low manufacturing cost wiring board with high reliability in connection, a semiconductor device and a producing method therefor.The invention relates to a wiring board comprising a board having an electrode and being coated with an insulation layer with a hole for exposing the electrode; a wiring consisting of a Cr or Ti layer, which is connected to the electrode and closely contacts with the insulation layer, and of a Cu layer which is closely contacts with the Cr or Ti layer; a protective film which covers the wiring and is provided with another hole for soldering; and a solder for the outer connection which is mounted in the both holes and brought to diffuse into the Cu layer to produce an alloy, and brought to reach the Cr or Ti layer thereby connecting the solder to the Cr or Ti layer.

Abstract: A packaged solid state device having a package, a chip, and an encapsulate having an epoxy resin, a boron containing catalyst that is essentially free of halogen. A LED device having a package, a LED chip, a encapsulate having a cycloaliphatic epoxy resin and a boroxine catalyst essentially free of halogen. A method of encapsulating a solid state device whereby a solid state device is placed into a package, and an encapsulant comprising an epoxy resin, and a boron containing catalyst that is essentially free of halogen, are provided.

Abstract: An integrated circuit chip package wherein the chip is encapsulated prior to mechanical bonding to a packaging substrate. The package provides a continuous adhesive interface between the encapsulated chip and surrounding encapsulant, and the substrate. This structure eliminates discontinuities in flatness and their associated stress states resulting in more reliable package contacts.

Abstract: A semiconductor package includes: a semiconductor chip having circuits formed on a surface, and having a thickness of 0.5 &mgr;m or more and 100 &mgr;m or less; and an adhesive resin layer provided so as to cover the surface of the semiconductor chip on which the circuits are provided.

Abstract: The present invention provides a resin-encapsulated semiconductor apparatus comprising a semiconductor device having a ferroelectric film and a surface-protective film, and an encapsulant member comprising a resin; the surface-protective film being formed of a polyimide. The present invention also provides a process for fabricating a resin-encapsulated semiconductor apparatus, comprising the steps of forming a film of a polyimide precursor composition on the surface of a semiconductor device having a ferroelectric film; heat-curing the polyimide precursor composition film to form a surface-protective film formed of a polyimide; and encapsulating, with an encapsulant resin, the semiconductor device on which the surface-protective film has been formed. The polyimide may preferably have a glass transition temperature of from 240° C. to 400° C. and a Young's modulus of from 2,600 MPa to 6 GPa. The curing may preferably be carried out at a temperature of from 230° C. to 300° C.

Abstract: The present invention provides a resin-encapsulated semiconductor apparatus comprising a semiconductor device having a ferroelectric film and a surface-protective film, and an encapsulant member comprising a resin; the surface-protective film being formed of a polyimide. The present invention also provides a process for fabricating a resin-encapsulated semiconductor apparatus, comprising the steps of forming a film of a polyimide precursor composition on the surface of a semiconductor device having a ferroelectric film; heat-curing the polyimide precursor composition film to form a surface-protective film formed of a polyimide; and encapsulating, with an encapsulant resin, the semiconductor device on which the surface-protective film has been formed. The polyimide may preferably have a glass transition temperature of from 240° C. to 400° C. and a Young's modulus of from 2,600 MPa to 6 GPa. The curing may preferably be carried out at a temperature of from 230° C. to 300° C.

Abstract: In producing an electronic device such as an overcurrent-protection element, a large substrate 21 is prepared with a plurality of element mounting sections 50. Electrodes 25 and 26 are formed on the surface of the substrate 21 in each of the element mounting sections 50. A fine metal wire 27 is connected between the electrodes 25 and 26 to form a fuse element. A framework portion 41 surrounds each element mounting section 50, forming a depression 24. The depression 24 houses the fine metal wire 27. A cover member 31 is placed over the top of the framework 41, hermetically sealing the depressions 24. Subsequently, the cover member 31 and substrate 21 are cut together, separating each of the element mounting sections 50 to obtain individual electronic devices.

Abstract: A method is provided of making a semiconductor package with a heat spreader in which a chip carrier module plate consisting of a plurality of array-arranged chip carriers is mounted with at least one chip on each of the chip carriers. A heat spreader module plate is attached to the chips, with an interface layer formed on a top surface of the heat spreader module plate. The chip carrier module plate, the chips and the heat spreader module plate are encapsulated. Adhesion force between the interface layer and the encapsulant is larger than that between the interface layer and the heat spreader module plate, and adhesion force between the interface layer and the heat spreader module plate is smaller than that between the heat spreader module plate and the encapsulant.

Abstract: Plural semiconductor chips such as acceleration sensor chips formed on the first surface of a substrate are separated into individual pieces by dicing the substrate from the second surface thereof. A groove surrounding each sensor chip, along which the sensor chip is diced out, is formed at the same time the sensor chip is formed on the first surface. Before dicing, a protecting sheet covering the first surface is pasted along the sidewalls and the bottom wall of the groove. The groove is made sufficiently wide to ensure that the protecting sheet is bent along the walls of the groove without leaving a space between the groove and the protecting sheet. Thus, dicing dusts generated in the dicing process are prevented from being scattered and entering the sensor chip.

Abstract: The present invention provides a resin-encapsulated semiconductor apparatus comprising a semiconductor device having a ferroelectric film and a surface-protective film, and an encapsulant member comprising a resin; the surface-protective film being formed of a polyimide. The present invention also provides a process for fabricating a resin-encapsulated semiconductor apparatus, comprising the steps of forming a film of a polyimide precursor composition on the surface of a semiconductor device having a ferroelectric film; heat-curing the polyimide precursor composition film to form a surface-protective film formed of a polyimide; and encapsulating, with an encapsulant resin, the semiconductor device on which the surface-protective film has been formed. The polyimide may preferably have a glass transition temperature of from 240° C. to 400° C. and a Young's modulus of from 2,600 MPa to 6 GPa. The curing may preferably be carried out at a temperature of from 230° C. to 300° C.

Abstract: A semiconductor package and a manufacturing method prevent electrical shorts that otherwise result from bonding wires contacting the edge of a semiconductor chip. An insulating region at the edge of a semiconductor chip prevents the shorts. One method for forming the insulating region leaves a polyimide layer on the scribe area of a wafer and cuts through the polyimide layer. To avoid chipping, the cutting uses a fine grit blade and a slow cutting rate. An alternative process removes the polyimide from the scribe area and forms the insulating region on the edge of the semiconductor chip. A potting method can deposit the insulating region on a semiconductor chip after cutting a wafer and after attaching a separated chip to a substrate. Alternatively, plotting or printing can apply insulating material on the wafer. A cutting process then cuts through the insulating material and the wafer and leaves insulating regions on each separated chip.

Abstract: A technique for post-processing a conventionally completed semiconductor device having a final passivation layer and bond pads exposed through the final passivation layer. The technique includes forming a protective film over the final passivation layer and exposed bond pads of the semiconductor device, and thereafter performing post-processing of the completed semiconductor device. Post-process structures, such as charge-coupled devices, can be formed above the protective film during this post-processing. Subsequent to the post-processing, the protective film is selectively etched to again expose the bond pads.

Abstract: A semiconductor chip assembly with a compliant layer overlying the chip and a flexible dielectric layer overlying the compliant layer. Connecting terminals are provided on the dielectric layer for connection to a larger substrate. The connecting terminals are moveable in vertical directions toward the chip. Bonding terminals, electrically connected to the connecting terminals, are also provided on the top layer. A reinforcing element resists vertical movement of the bonding terminals, and thereby facilitates connection of leads between the bonding terminals and the chip.

Abstract: A sealed semiconductor chip having a surface film of a sealed resin composition, wherein the resin composition has a linear expansion coefficient of 60×10−6/K or less at a temperature equal to or less than its glass transition point and 140×10−6/K or less at a temperature equal to or higher than its glass transition point; a semiconductor-sealing resin composition for sealing a semiconductor chip, which has a linear expansion coefficient of 60×10−6/K or less at a temperature equal to or less than its glass transition point and 140×10−6/K or less at a temperature equal to or higher than its glass transition point; the sealed semiconductor chip is chip size and has high reliability; the semiconductor-sealing resin composition creates a good seal on chip wafers and has high reliability; and the chip wafers sealed with a surface film of the resin composition warp little.

Abstract: There is provided a resin composition having high flame retardancy, which improves high temperature storage of an epoxy resin composition comprising an epoxy resin having biphenyl structure without a halogenated flame retardant and an antimony compound as a conventional flame retardant. High temperature storage was improved, a glass transition temperature (Tg) became not less than 150° C. and V-0 class in flame retardance standard (UL94) was accomplished by employing (1) an epoxy resin having biphenyl structure mainly as an epoxy resin, (2) a phenolic aralkyl resin mainly as a curing agent, (3) 0.5 to 30 parts by weight of a polyimide resin as an additive based on total 100 parts by weight of the epoxy resin and the curing agent, (4) a polysiloxane compound modified with polyether containing an amino group as a flame retardant, (5) not less than 87% by weight of a fused silica as an inorganic filler based on the total composition.

Abstract: AS conductive patterns 11A to 11D are formed burying in a insulating resin 10 and a conductive foil 20 is formed being half-etched, thickness of the device is made thin. As an electrode for radiation 11D is provided, a semiconductor device superior in radiation is provided. Thickness of an electric connection means SD is substantially made definite as the electric connection means SD does not flow to a conductive path 11B by using a flow-prevention film DM.

Abstract: The present invention provides a resin-encapsulated semiconductor apparatus comprising a semiconductor device having a ferroelectric film and a surface-protective film, and an encapsulant member comprising a resin; the surface-protective film being formed of a polyimide. The present invention also provides a process for fabricating a resin-encapsulated semiconductor apparatus, comprising the steps of forming a film of a polyimide precursor composition on the surface of a semiconductor device having a ferroelectric film; heat-curing the polyimide precursor composition film to form a surface-protective film formed of a polyimide; and encapsulating, with an encapsulant resin, the semiconductor device on which the surface-protective film has been formed. The polyimide may preferably have a glass transition temperature of from 240° C. to 400° C. and a Young's modulus of from 2,600 MPa to 6 GPa. The curing may preferably be carried out at a temperature of from 230° C. to 300° C.

Abstract: A flip-chip device and process for fabricating the device employs a multilayer encapsulant that includes a first portion encapsulant having a coefficient of thermal expansion of at most 30 ppm/° C. and an elastic modulus of 2-20 GPa and a second portion comprising a polymer flux having a coefficient of thermal expansion that may exceed 30 ppm/° C.

Abstract: A method of encapsulating a semiconductor device comprising the steps of providing a mold having top and bottom halves each with cavities for holding semiconductor devices, and further having gates and runners for feeding encapsulation material into said cavities; lining said cavities with protective plastic films; providing a plurality of semiconductor integrated circuit chips, each having an outline; providing an electrically insulating interposer; assembling said chip and said interposer, loading said assembly into said mold and introducing into said mold a low-viscosity, high adhesion encapsulation material; at least partially curing said encapsulation material, thereby forming a flat, high-luster surface; opening said mold and removing said interposer together with said encapsulated chips from said mold; attaching an array of solder balls to the exposed surface of said interposer; and singulating said encapsulated semiconductor devices, thereby forming devices having an outline substantially the same as

Abstract: The present invention provides a semiconductor package, the package comprising: a base substrate having a perforation formed therein, the perforation including a bottom and the base substrate including a backface; an electrode portion secured to the backface of the base substrate and disposed on the bottom of the perforation; a semiconductor device electrically connected to the electrode portion and disposed on the backface of the base substrate; a sheet elastic body interposed between the semiconductor device and the electrode portion; and leveling means between the sheet elastic body and the electrode portion for eliminating gaps along the electrode portion. In the semiconductor package neither deformation nor cracks of the package will be produced even if heat history is applied during packaging and the package density can be improved. The present invention further provides a process for the production of the semiconductor package.

Abstract: A low elasticity layer (20) having an opening in an electrode arranging area where element electrodes are disposed is provided on a main surface of a semiconductor substrate (10). On the low elasticity layer (20), lands (32) serving as external electrodes are disposed, and pads (30) on the element electrodes, the lands (32) and metal wires (31) for connecting them are integrally formed as a metal wiring pattern (33). A solder resist film (50) having an opening for exposing a part of each land (32) is formed, and a metal ball (40) is provided on the land (32) in the opening. The low elasticity layer (20) absorbs thermal stress and the like caused in heating or cooling the semiconductor device, so as to prevent disconnection of the metal wires (31).

Abstract: Patterns for a routable interface of the signal lines of a integrated circuit device include several groups of terminals distributed about the pattern center, each group clustered along a corresponding curvilinear reference segment extending outward from the pattern center to its perimeter. Routability zones are created between each successive pair of groups. For higher terminal density, in at least one of the terminal groups of the pattern, either the offset of the terminals from the reference line segment is not uniform, or the distance of the terminals from the pattern center does not increase uniformly. A portion, preferably at least about 50% of the terminals in a group of the pattern are not collinear with, but offset from, the reference segment. A portion, preferably at least about 90% of the terminals in a given terminal group are each closer to the reference line segment of that terminal group than they are to the reference segment of another terminal group.

Abstract: A low elasticity layer (20) having an opening in an electrode arranging area where element electrodes are disposed is provided on a main surface of a semiconductor substrate (10). On the low elasticity layer (20), lands (32) serving as external electrodes are disposed, and pads (30) on the element electrodes, the lands (32) and metal wires (31) for connecting them are integrally formed as a metal wiring pattern (33). A solder resist film (50) having an opening for exposing a part of each land (32) is formed, and a metal ball (40) is provided on the land (32) in the opening. The low elasticity layer (20) absorbs thermal stress and the like caused in heating or cooling the semiconductor device, so as to prevent disconnection of the metal wires (31).

Abstract: An optical semiconductor component includes a semiconductor substrate (120) and a packaging material (140) located over the semiconductor substrate. The packaging material includes an optically transparent cycloaliphatic polymer (142, 242, 400, 600). A method of manufacturing the component includes nixing a monomer (300, 500) of the polymer with a catalyst to form the packaging material, filtering the packaging material, applying the packaging material, and curing the packaging material.

Abstract: A structure and method for forming a hermetically sealed semiconductor chip having an active and a passive surface and four edge sides, each edge side having only a single plane; said active surface having an integrated circuit including multiple deposited layers and a plurality of contact pads, said contact pads having bondable and non-corrodible surface; said deposited layers having exposed portions at said side edges; a protective overcoat impermeable to moisture overlying said integrated circuit; and a continuous sealant layer impermeable to moisture overlying all area of said four side edges, whereby said edge sides are sealed and said chip is rendered hermetic.

Abstract: Microelectronic assemblies are encapsulated using disposable frames. The microelectronic assemblies are disposed within an aperture defined by a frame. The aperture is covered by top and bottom sealing layers so that the frame and sealing layers define an enclosed space encompassing the assemblies. The encapsulant is injected into this closed space. The frame is then separated from the encapsulation fixture and held in a curing oven. After cure, the frame is cut apart and the individual assemblies are severed from one another. Because the frame need not be held in the encapsulation fixture during curing, the process achieves a high throughput.

Abstract: An optical module including a substrate, an optical waveguide formed on the substrate, and an optical element mounted on the substrate so as to be optically coupled to an end of the optical waveguide, for performing conversion between light and electricity. The optical module further includes a transparent resin for covering at least an optical coupling portion between the optical waveguide and the optical element, and a thermoplastic resin for covering only the optical element and its periphery including the transparent resin to seal the optical element.

Abstract: A ceramic column grid array package suitable for mounting application specific integrated circuits or microprocessor chips onto a printed circuit board employing polymer reinforced columns on the substrate module is described. The polymer enhancement is formed by coating a thin conformal film of a polymer, such as, a polyimide onto the substrate module after the formation of the ceramic column grids to mechanically enhance the column to substrate attachment of the column to the substrate prior to mounting on a printed circuit card. Upon curing of the polymer film at a temperature below the melting point of the solder bond attaching the column grid to the substrate, the columns will be mechanically reinforced in their attachment to the substrate. Upon removal of the substrate module from a printed circuit card during rework, the columns of the grid array will remain with the substrate module, leaving no columns on the printed circuit card.

Abstract: A heat resisting resin sheet is bonded to a semiconductor chip as a protective cap for protecting a beam structure provided on the semiconductor chip, through a heat resisting adhesive. The heat resisting resin sheet is composed of a polyimide base member and the heat resisting adhesive is composed of silicone adhesive. The heat resisting resin sheet is not deformed during a manufacturing process of the semiconductor chip. In addition, grinding water does not invade into the semiconductor chip during dicing-cut.

Abstract: This invention relates to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface. The semiconductor device has a semiconductor chip, a lead member having a lead portion and an outer connecting terminal connected integrally to the lead portion, the lead portion electrically connected to the semiconductor chip, the lead portion extending outwardly from the semiconductor chip, the outer connecting terminal extending downwardly from the lead portion, a sealing resin sealing the semiconductor chip and the lead portion, a bottom face of the semiconductor chip and a bottom face of the lead portion being exposed from the sealing resin, and an insulating member covering the bottom face of the semiconductor chip and the bottom face of the lead portion.

Abstract: An integrated circuit package includes at least one integrated circuit element coupled to a polymer film; a window frame coupled to the polymer film and surrounding the at least one integrated circuit element; and encapsulant material positioned between the at least one integrated circuit element and the window frame.

Abstract: A wafer frame for fixing and handling 200 mm wafers is produced with a significantly reduced weight as compared to a metal wafer frame, while maintaining mechanical and thermal material properties. This is accomplished by producing the wafer frame from a plastic with a glass fiber content of from 1 to 40% by weight.

Abstract: A card-type semiconductor device including a thin (e.g., 30 to 70 &mgr;m) semiconductor chip which is thinner than an insulating resin film embedded in a device hole of a wiring film. The wiring film includes a copper wiring layer and inner leads arranged on one main face of the insulating resin film. Electrode pads are bonded to the inner leads by heating and pressing. A sealing resin layer is formed on the exterior of the bonded portion as required, and a polyester resin film is integrally laminated on the upper and lower faces of the wiring film. The card-type semiconductor device with the above construction has sufficient strength against bending, etc., and is suitable for integrated circuit (IC) card applications.

Abstract: A semiconductor device includes a wiring substrate having wiring and a solder resist for protecting the wiring, which are provided on an insulating substrate, a semiconductor chip which is mounted via the wiring protective film on the wiring substrate on a surface on the other side of the surface on which a circuit is provided to face a side of the wiring substrate on which the wiring is formed, and a wire for electrically connecting the circuit provided on the surface of the semiconductor chip and the wiring of the wiring substrate, and the surface of the solder resist and the semiconductor chip are firmly adhered to each other. In this semiconductor device, because the solder resist and the semiconductor chip are firmly adhered to each other, there arise no bubbles due to a spacing at a portion where the solder resist and the semiconductor chip are bonded with each other.

Abstract: The invention is an encapsulated circuit assembly including a chip; a substrate; at least one solder joint which spans between the chip and the substrate forming an electrically conductive connection between the chip and the substrate; and an encapsulant formed adjacent the solder joint, wherein the encapsulant comprises a thermoplastic polymer formed by ring opening polymerization of a cyclic oligomer.

Abstract: A novel method for coating a semiconductor die/leadframe assembly prior to encapsulation. The method of the invention comprises coating the exposed surfaces of the die and the inner lead fingers in a die/leadframe assembly with an adhesion promoting material, typically a polyimide. A solution of the adhesion promoting material is dispensed from a spray nozzle to coat the die and the inner lead fingers. Preferably, all exposed surfaces of the die, the inner lead fingers and the bond wires are coated prior to encapsulation. The invention also provides an improved semiconductor package that includes a semiconductor die/leadframe assembly and a layer of adhesion promoting material coating the exposed surfaces of the die and the inner lead fingers. The die/leadframe assembly is encapsulated in a molded plastic package.

Abstract: A semiconductor package uses no thermosetting adhesive for mounting a heat slug thereon, which adhesive requires a strict control during the storage and the production thereof. A semiconductor package comprises a circuit board having respective surfaces and an opening; a conductive layer formed on one of the surfaces of the circuit board so that the conductive layers are retracted from a peripheral edge of the opening by a certain distance; a heat slug attached to the one surface of the circuit board by means of solder so that the opening is closed at the one surface and opened at the other surface to form a cavity within which a semiconductor element mounting area is defined.

Abstract: A semiconductor flip chip package is provided having a semiconductor flip chip integrated circuit device and a laminated substrate. The laminated substrate has a conductive core and at least one lamina formed on the core layer. Each lamina has a dielectric layer and a conductive layer. The dielectric layer is formed at least in part from a fluoropolymer material having disposed therein an inorganic filler material. At least one via extends through the at least one lamina. The via has an entrance aperature of <75 microns and an aspect ratio of between 3:1 and 25;1. The laminated substrate includes a plurality of individual pads to which the individual solder ball connections of the semiconductor flip chip integrated circuit device are connected.

Abstract: A method of forming a resin film pattern, comprising the steps of (A) producing a resin film layer soluble in an organic solvent, on a substrate such as silicon wafer, even engineering plastics being usable as a resin of the resin film layer; (B) forming a resist image of desired pattern on the organic solvent-soluble resin film layer; (C) etching each of those parts of the organic solvent-soluble resin film layer which are not covered with the resist image, using the organic solvent; and (D) removing the resist image from the resulting, organic solvent-soluble resin film layer using a resist image remover which contains 0.01-10.0 parts-by-weight of arylsulfonic acid with respect to 100 parts-by-weight of solvent having a solubility parameter of 5.0-11.0. The step (D) may well be followed by the step (E) of processing the substrate which includes the resin film layer, with alcohol.

Abstract: A resin-mold type semiconductor device includes a semiconductor chip, a die pad for supporting and fixing the semiconductor chip, a plurality of inner leads whose distal ends face the semiconductor chip, a plurality of outer leads integrally connected to the corresponding inner leads, bonding wires for electrically connecting distal end portions of the inner leads to terminal electrodes of the semiconductor chip, a resin-mold package for molding the die pad, the semiconductor chip, the inner leads and the bonding wires, and a highly water-absorbent insulating film made of highly water-absorbent polymer formed at least one portion of the surface of the resin-mold package.

Abstract: A multilayer substrate which is fabricated by laminating a plurality of substrates, each comprising an insulation film, a plurality of via holes which pass through the upper surface to the lower surface of the insulation film, a wiring which is provided on the upper surface of the insulation film and the upper surface of the via holes and electrically connected with the via holes, a bonding member which is provided on the lower surfaces of the via holes and electrically connected with the via holes, and a bonding layer which is provided on the upper surface of the insulation film where the wiring is formed and the method of fabrication thereof whereby large costs reduction and high density effect can be obtained.

Abstract: A semiconductor device in which the surface of the semiconductor element is coated with a cured silicone in which there is dispersed filler having an average particle diameter of 0.01 to 500 micrometers and a specific gravity of 0.01 to 0.95 characterized in that the concentration of said filler is higher in the layer of said cured material remote from the element than in the layer of said cured material adjoining the element. The method for fabricating such a device comprises coating the surface of a semiconductor element with a curable silicone composition in which there is dispersed a filler having an average particle diameter of 0.01 to 500 micrometers and a specific gravity of 0.01 to 0.95 and thereafter curing said composition after the elapse of sufficient time for the filler in the layer of the composition adjoining the element to migrate into the layer of said composition remote from the element.

Abstract: A semiconductor chip is mounted on a die pad of a lead-frame, and the semiconductor chip mounted on the die pad is sealed in a plastic package; a side surface of the semiconductor chip and an exposed upper surface and a side surface of the die pad are covered with an organic stress relaxation layer so as to reduce a thermal stress due to the difference in thermal expansion coefficient between the semiconductor chip and the die pad, thereby presenting the plastic package from a crack.

Abstract: A semiconductor device includes an interconnection plate, a semiconductor chip having electrodes formed on one surface thereof and bonded to the interconnection plate with the other surface thereof, wires respectively connecting the electrodes of the semiconductor chip and the internal connection regions of the interconnection plate, and a resin sealer sealing therein the semiconductor chip and the wires on the interconnection plate, wherein the internal connection regions are provided in a peripheral area of the interconnection plate surrounding the semiconductor chip, and major portions of the interconnection patterns and the external connection terminals are provided in an area inward from the internal connection regions under the semiconductor chip.

Abstract: An adhesive composition including: a main component comprising a resin material, a solvent for dissolving said main component, and a filler added to said main component, wherein said filler has a particle size so as to make a concavo-convex depth of a surface of said adhesive composition equal to or less than 15 .mu.m after said adhesive composition is applied to an adherend and dried in order to evaporate said solvent before a thermocompression process. The present invention also discloses a semiconductor device using the adhesive composition, an adhering method using the adhesive composition and a method for producing a semiconductor device using the adhesive composition.

Abstract: A semiconductor device capable of preventing the occurrence of defect of electroconductivity, wherein a semiconductor chip 1 equipped with electrodes 11 is mounted on an auxiliary wiring plate 2 in the state of facing the surface of the electrode 11 side, leading conductors 23 are disposed in the inside of the auxiliary wiring plate 2, one end of each leading conductor 23 forms an internal electrode 21 projecting from the surface of the auxiliary wiring plate 2 at the side of mounting the semiconductor chip 1, the other end of the leading conductor 23 forms an external electrode 22 projecting from the surface of the auxiliary wiring plate opposite to the side of mounting the semiconductor chip 1, and each of the internal electrodes 21 is connected to each of the electrodes 11 of the semiconductor chip 1, at least a gap between the semiconductor chip 1 and the auxiliary wiring plate 2 is encapsulated with a heat-welding polyimide resin layer.

Abstract: A tape carrier comprises an insulating film and a pattern formed of a metal foil on at least one side surface of said film, said tape carrier being characterized in that an adhesive resin overcoat is applied to the pattern surface portion around a portion to be coated with an IC sealing resin, and a polyimide resin-based overcoat is applied to the remaining pattern surface portion.