With Heterojunction Patents (Class 257/85)
  • Patent number: 10439099
    Abstract: A method of fabricating an ultraviolet (UV) light emitting device includes receiving a UV transmissive substrate, forming a first UV transmissive layer comprising aluminum nitride upon the UV transmissive substrate using a first deposition technique at a temperature less than about 800 degrees Celsius or greater than about 1200 degrees Celsius, forming a second UV transmissive layer comprising aluminum nitride upon the first UV transmissive layer comprising aluminum nitride using a second deposition technique that is different from the first deposition technique, at a temperature within a range of about 800 degrees Celsius to about 1200 degrees Celsius, forming an n-type layer comprising aluminum gallium nitride layer upon the second UV transmissive layer, forming one or more quantum well structures comprising aluminum gallium nitride upon the n-type layer, and forming a p-type nitride layer upon the one or more quantum well structures.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: October 8, 2019
    Assignee: Rayvio Corporation
    Inventors: Yitao Liao, Robert Walker, Doug Collins
  • Patent number: 10348059
    Abstract: A light emitting element array includes plural semiconductor stacking structures and a light screening portion. The plural semiconductor stacking structures each include a light emitting portion and a light receiving portion that receives light propagated in a lateral direction via a semiconductor layer from the light emitting portion. The light screening portion is provided between the plural semiconductor stacking structures to screen light directed from the light emitting portion of one of the semiconductor stacking structures to the light receiving portion of another semiconductor stacking structure.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: July 9, 2019
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Junichiro Hayakawa, Akemi Murakami, Takashi Kondo, Naoki Jogan, Jun Sakurai
  • Patent number: 10090363
    Abstract: To provide a novel light-emitting device, a light-emitting device that emits light of a plurality of colors includes a first light-emitting element and a second light-emitting element. The first light-emitting element includes a first lower electrode, a first light-emitting layer over the first lower electrode, a second light-emitting layer over the first light-emitting layer, and an upper electrode over the second light-emitting layer. The second light-emitting element includes a second lower electrode, the first light-emitting layer over the second lower electrode, the second light-emitting layer over the first light-emitting layer, and the upper electrode over the second light-emitting layer. An emission spectrum of the first light-emitting layer peaks at a longer wavelength than an emission spectrum of the second light-emitting layer.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: October 2, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Seo, Toshiki Sasaki
  • Patent number: 9911896
    Abstract: In accordance with embodiments of the invention, at least partial strain relief in a light emitting layer of a III-nitride light emitting device is provided by configuring the surface on which at least one layer of the device grows such that the layer expands laterally and thus at least partially relaxes. This layer is referred to as the strain-relieved layer. In some embodiments, the light emitting layer itself is the strain-relieved layer, meaning that the light emitting layer is grown on a surface that allows the light emitting layer to expand laterally to relieve strain. In some embodiments, a layer grown before the light emitting layer is the strain-relieved layer. In a first group of embodiments, the strain-relieved layer is grown on a textured surface.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: March 6, 2018
    Assignees: Koninklijke Phillips N.V., Lumileds LLC
    Inventors: Sungsoo Yi, Nathan F. Gardner, Michael R. Krames, Linda T. Romano
  • Patent number: 9627564
    Abstract: An optoelectronic device comprising: a first conductive layer, a second conductive layer, an active layer between the first conductive layer and the second conductive layer, wherein the active layer comprises a submicrometer size structure of hexagonal type crystals of an element or alloy of elements selected from the carbon group.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: April 18, 2017
    Assignees: Electricite de France, Centre National de la Recherche Scientifique (CNRS), University of Houston
    Inventors: Jean-Francois Guillemoles, Par Olsson, Julien Vidal, Alexandre Freundlich
  • Patent number: 9570599
    Abstract: A portion of an AlN spacer layer of a high electron mobility transistor (GaN HEMI) having a nitride semiconductor used therein is removed only in a region directly below a gate electrode and in a vicinity of the region, and a length of a portion where the AlN spacer layer is not present is sufficiently smaller than a distance between a source electrode and a drain electrode.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: February 14, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yutaro Yamaguchi, Toshiyuki Oishi, Hiroshi Otsuka, Koji Yamanaka
  • Patent number: 9548355
    Abstract: A semiconductor device includes a wafer having a bulk layer and a III-V buffer layer on an upper surface of the bulk layer. The semiconductor device further includes at least one semiconductor fin on the III-V buffer layer. The semiconductor fin includes a III-V channel portion. Either the wafer or the semiconductor fin includes an oxidized III-V portion interposed between the III-V channel portion and the III-V buffer layer to prevent current leakage to the bulk layer.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: January 17, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Szu-Lin Cheng, Isaac Lauer, Kuen-Ting Shiu, Jeng-Bang Yau
  • Patent number: 9379280
    Abstract: A method for fabricating LED devices. The method includes providing a gallium and nitrogen containing substrate member (e.g., GaN) comprising a backside surface and a front side surface. The method includes subjecting the backside surface to a polishing process, causing a backside surface to be characterized by a surface roughness, subjecting the backside surface to an anisotropic etching process exposing various crystal planes to form a plurality of pyramid-like structures distributed spatially in a non-periodic manner on the backside surface, treating the backside surface comprising the plurality of pyramid-like structures, to a plasma species, and subjecting the backside surface to a surface treatment. The method further includes forming a contact material comprising an aluminum bearing species or a titanium bearing species overlying the surface-treated backside to form a plurality of LED devices with the contact material.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: June 28, 2016
    Assignee: SORAA, Inc.
    Inventors: Michael J. Cich, Kenneth John Thomson
  • Patent number: 9257605
    Abstract: A method of manufacturing a light emitting device having a plurality of nano-light emitting structures is provided. The method comprises depositing a first conductivity-type semiconductor material on a substrate to form a base layer. A mask having a plurality of openings is formed on the base layer. The first conductivity-type nitride semiconductor material is deposited in the openings of the mask to form a plurality of nanocores having a main portion bounded by the mask and an exposed tip portion. A current blocking layer is deposited on the tip portion of the nanocores. A portion of the mask is removed to expose the main portion of the nanocore. An active material layer is deposited on the plurality of nanocores. A second conductivity-type nitride semiconductor layer is deposited on the active material layer.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: February 9, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yeon Woo Seo, Jung-Sub Kim, Young Jin Choi, Denis Sannikov, Han Kyu Seong, Dae Myung Chun, Jae Hyeok Heo
  • Patent number: 9252325
    Abstract: The present invention provides a method for producing a Group III nitride semiconductor light-emitting device wherein in the formation of a light-emitting layer by forming a well layer, a capping layer and a barrier layer, the well layer having superior flatness and crystallinity is formed while suppressing the occurrence of damage to the well layer. In formation of the light-emitting layer, pits are provided in the light-emitting layer so that a pit diameter D falls within a range of 120 nm to 250 nm. The light-emitting layer formation step comprises the steps of forming the barrier layer, forming the well layer, and forming the capping layer. The growth temperature of the barrier layer is higher by any temperature in a range of 65° C. to 135° C. than that of the well layer.
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: February 2, 2016
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Misato Mukono, Ryo Nakamura
  • Patent number: 9207851
    Abstract: A matrix of light emitting diodes is positioned behind a liquid crystal layer of a display device. The light emitting diodes operate in both light emitting and light detecting modes. Consequently, the display device is able to sense objects or fingers approaching or in contact with a front display surface of the display device based on changes in incident light on the matrix that are observed by one or more of the light emitting diodes operating in the light detecting mode.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: December 8, 2015
    Assignee: PERCEPTIVE PIXEL, INC.
    Inventor: Jefferson Y. Han
  • Patent number: 9091812
    Abstract: An energy-efficient transparent solar film is presented. The solar film has a first film layer with metal nanostructures. The metal nanostructures have plasmon resonances in wavelength bands greater than, or both less than and greater than visible wavelengths, depending on size and shape. The metal nanostructures have no plasmon resonance at visible wavelengths. In another aspect, metal oxide nanocrystals are formed with the first film layer. The metal oxide nanocrystals have absorption in a band of wavelengths less than visible wavelengths, and absorption in a band of wavelengths greater than visible wavelengths. Also provided is a solar film window and fabricating method.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: July 28, 2015
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Akinori Hashimura, Douglas Tweet, Gary Hinch, Alexey Koposov
  • Patent number: 9076744
    Abstract: The invention relates to an organic-based electronic component, especially a component with reduced pixel crosstalk. According to the invention, the crosstalk is reduced by a grid electrode.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: July 7, 2015
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Jens Fürst, Debora Henseler, Hagen Klausmann
  • Patent number: 9018646
    Abstract: A photoconductor comprising a layer stack with a semiconductor layer photoconductive for a predetermined wavelength range between two semiconductor boundary layers with a larger band gap than the photoconductive semiconductor layer on a substrate, wherein the semiconductor boundary layers comprise deep impurities for trapping and recombining free charge carriers from the photoconductive semiconductor layer, and two electrodes connected to the photoconductive semiconductor layer, for lateral current flow between the electrodes through the photoconductive semiconductor layer.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: April 28, 2015
    Assignee: Fraunhofer-Gesellschaft zur Foederung der angewandten Forschung e.V.
    Inventors: Bernd Sartorius, Harald Kuenzel, Helmut Roehle, Klaus Biermann
  • Patent number: 9012886
    Abstract: According to one embodiment, a semiconductor light emitting device includes: a first semiconductor layer; a second semiconductor layer; and a light emitting layer provided between the first and the second semiconductor layers. The first semiconductor layer includes a nitride semiconductor, and is of an n-type. The second semiconductor layer includes a nitride semiconductor, and is of a p-type. The light emitting layer includes: a first well layer; a second well layer provided between the first well layer and the second semiconductor layer; a first barrier layer provided between the first and the second well layers; and a first Al containing layer contacting the second well layer between the first barrier layer and the second well layer and containing layer containing Alx1Ga1-x1N (0.1?x1?0.35).
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jongil Hwang, Shinji Saito, Rei Hashimoto, Shinya Nunoue
  • Patent number: 9006709
    Abstract: According to one embodiment, a semiconductor light emitting element includes a first semiconductor layer of an n-type, a second semiconductor layer of a p-type, and a light emitting unit. The first semiconductor layer includes a nitride semiconductor. The second semiconductor layer includes a nitride semiconductor. The light emitting unit is provided between the first semiconductor layer and the second semiconductor layer. The light emitting unit includes a plurality of well layers stacked alternately with a plurality of barrier layers. The well layers include a first p-side well layer most proximal to the second semiconductor layer, and a second p-side well layer second most proximal to the second semiconductor layer. A localization energy of excitons of the first p-side well layer is smaller than a localization energy of excitons of the second p-side well layer.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeya Kimura, Hajime Nago, Shinya Nunoue
  • Patent number: 8980657
    Abstract: The present invention is a method for producing a light-emitting device whose p contact layer has a p-type conduction and a reduced contact resistance with an electrode. On a p cladding layer, by MOCVD, a first p contact layer of GaN doped with Mg is formed. Subsequently, after lowering the temperature to a growth temperature of a second p contact layer being formed in the subsequent process, which is 700° C., the supply of ammonia is stopped and the carrier gas is switched from hydrogen to nitrogen. Thereby, Mg is activated in the first p contact layer, and the first p contact layer has a p-type conduction. Next, the second p contact layer of InGaN doped with Mg is formed on the first p contact layer by MOCVD using nitrogen as a carrier gas while maintaining the temperature at 700° C. which is the temperature of the previous process.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: March 17, 2015
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Shinya Boyama, Yasuhisa Ushida
  • Patent number: 8981339
    Abstract: A white-light emitting lighting device comprising one or more light emitting light sources (preferably solid state semiconductor light emitting diodes) that emit off-white light during operation, wherein the off-white light includes a spectral output including at least one spectral component in a first spectral region from about 360 nm to about 475 nm, at least one spectral component in a second spectral region from about 475 nm to about 575 nm, and at least one deficiency in at least one other spectral region, and an optical component comprising an optical material for converting at least a portion of the off-white light to one or more predetermined wavelengths, such that light emitted by the lighting device comprises white light, wherein the optical material comprises quantum confined semiconductor nanoparticles. Also disclosed is an optical component, lighting fixture, a cover plate for a lighting fixture, and methods.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: March 17, 2015
    Assignee: QD Vision, Inc.
    Inventors: John R. Linton, Emily M. Squires, Rohit Modi
  • Patent number: 8963167
    Abstract: An improved diode energy converter for chemical kinetic electron energy transfer is formed using nanostructures and includes identifiable regions associated with chemical reactions isolated chemically from other regions in the converter, a region associated with an area that forms energy barriers of the desired height, a region associated with tailoring the boundary between semiconductor material and metal materials so that the junction does not tear apart, and a region associated with removing heat from the semiconductor.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: February 24, 2015
    Assignee: Neokismet, LLC
    Inventors: Jawahar M. Gidwani, Anthony C. Zuppero
  • Patent number: 8957402
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first nitride semiconductor layer, a nitride semiconductor light emitting layer, a second nitride semiconductor layer, a p-side electrode, and an n-side electrode. The nitride semiconductor light emitting layer is provided on the p-side region of the second face of the first nitride semiconductor layer. The second nitride semiconductor layer is provided on the nitride semiconductor light emitting layer. The p-side electrode is provided on the second nitride semiconductor layer. The n-side electrode is provided on the n-side region of the second face of the first nitride semiconductor layer. The nitride semiconductor light emitting layer has a first concave-convex face in a side of the first nitride semiconductor layer, and a second concave-convex face in a side of the second nitride semiconductor layer.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Kojima, Hideto Furuyama, Miyoko Shimada, Yosuke Akimoto
  • Publication number: 20140374778
    Abstract: An optical assembly configured to emit electromagnetic radiation comprises first and second electroluminescent semiconductor components positioned adjacent to each other. The first electroluminescent semiconductor component is transparent to electromagnetic radiation generated by the second electroluminescent semiconductor component, and the second electroluminescent semiconductor component is transparent to electromagnetic radiation generated by the first electroluminescent semiconductor component. The first electroluminescent semiconductor component and the second electroluminescent semiconductor component are configured to actuate independently of each other.
    Type: Application
    Filed: June 20, 2014
    Publication date: December 25, 2014
    Inventors: Richard Fix, Patrick Sonstroem
  • Patent number: 8916857
    Abstract: A light-emitting element disclosed in the present invention includes a light-emitting layer and a first layer between a first electrode and a second electrode, in which the first layer is provided between the light-emitting layer and the first electrode. The present invention is characterized by the device structure in which the first layer comprising a hole-transporting material is doped with a hole-blocking material or an organic compound having a large dipole moment. This structure allows the formation of a high performance light-emitting element with high luminous efficiency and long lifetime. The device structure of the present invention facilitates the control of the rate of the carrier transport, and thus, leads to the formation of a light-emitting element with a well-controlled carrier balance, which contributes to the excellent characteristics of the light-emitting element of the present invention.
    Type: Grant
    Filed: November 24, 2012
    Date of Patent: December 23, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoko Shitagaki, Satoshi Seo, Ryoji Nomura
  • Patent number: 8901612
    Abstract: Embodiments of a thin-film heterostructure thermoelectric material and methods of fabrication thereof are disclosed. In general, the thermoelectric material is formed in a Group IIa and IV-VI materials system. The thermoelectric material includes an epitaxial heterostructure and exhibits high heat pumping and figure-of-merit performance in terms of Seebeck coefficient, electrical conductivity, and thermal conductivity over broad temperature ranges through appropriate engineering and judicious optimization of the epitaxial heterostructure.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: December 2, 2014
    Assignees: Phononic Devices, Inc., The Board of Regents of the University of Oklahoma
    Inventors: Allen L. Gray, Robert Joseph Therrien, Patrick John McCann
  • Patent number: 8877652
    Abstract: A substrate structure and method of manufacturing the same are disclosed. The substrate structure may includes a substrate on which a plurality of protrusions are formed on one surface thereof and a plurality of buffer layers formed according to a predetermined pattern and formed spaced apart from each other on the plurality of protrusions.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youn Kim, Su-hee Chae, Hyun-gi Hong, Young-jo Tak
  • Patent number: 8853713
    Abstract: Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the oxide material formed in the opening.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: October 7, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Eugene P. Marsh, Jun Liu
  • Patent number: 8853735
    Abstract: Provided is an epitaxial substrate for a semiconductor device, which has excellent schottky contact characteristics that are stable over time. The epitaxial substrate for a semiconductor device includes a base substrate, a channel layer formed of a first group III nitride containing at least Ga and having a composition of Inx1Aly1Gaz1N (x1+y1+z1=1), and a barrier layer formed of a second group III nitride containing at least In and Al and having a composition of Inx2Aly2Gaz2N (x2+y2+z2=1), wherein the barrier layer has tensile strains in an in-plane direction, and pits are formed on a surface of the barrier layer at a surface density of 5×107/cm2 or more and 1×109/cm2 or less.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: October 7, 2014
    Assignee: NGK Insulators, Ltd.
    Inventors: Makoto Miyoshi, Mikiya Ichimura, Tomohiko Sugiyama, Mitsuhiro Tanaka
  • Patent number: 8847244
    Abstract: A photpcoupler includes: a light emitting element; a first photodiode array; a second photodiode array; a third photo diode array; an enhancement-mode MOSFET; a first depletion-mode MOSFET; and a second depletion mode MOSFET. The light emitting element converts the input electrical signal into the optical signal. A drain current of the enhancement-mode MOSFET is supplied to the external load when the optical signal is ON. A drain current of the first depletion-mode MOSFET is supplied to the external load when the optical signal is OFF and a voltage passing through the second depletion-mode MOSFET switched to the ON state is supplied to the gate of the first depletion-mode MOSFET. And the drain current of the first depletion-mode MOSFET is larger than a drain current of the first depletion-mode MOSFET when a gate voltage of the first depletion-mode MOSFET is zero.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: September 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoichiro Ito
  • Publication number: 20140252379
    Abstract: A photoconductive antenna that generates and detects a terahertz wave has a substrate, a buffer layer, a first semiconductor layer, a second semiconductor layer, and an electrode in this order. The substrate is made of Si, the buffer layer contains Ge, and the first and second semiconductor layers both contain Ga and As. The element ratio Ga/As of the second semiconductor layer is smaller than the element ratio Ga/As of the first semiconductor layer.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 11, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Takahiro Sato
  • Patent number: 8803165
    Abstract: A nitride semiconductor light emitting device includes an n-type GaN substrate (101) that is a nitride semiconductor substrate, a nitride semiconductor layer including a p-type nitride semiconductor layer formed on the n-type GaN substrate (101). The p-type nitride semiconductor layer includes a p-type AlGaInN contact layer (108), a p-type AlGaInN cladding layer (107) under the p-type AlGaInN contact layer (108), and a p-type AlGaInN layer (106). A protection film (113) made of a silicon nitride film is formed above a current injection region formed in the p-type nitride semiconductor layer.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: August 12, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Takeshi Kamikawa
  • Patent number: 8766391
    Abstract: Photodetector arrays, image sensors, and other apparatus are disclosed. In one aspect, an apparatus may include a surface to receive light, a plurality of photosensitive regions disposed within a substrate, and a material coupled between the surface and the plurality of photosensitive regions. The material may receive the light. At least some of the light may free electrons in the material. The apparatus may also include a plurality of discrete electron repulsive elements. The discrete electron repulsive elements may be coupled between the surface and the material. Each of the discrete electron repulsive elements may correspond to a different photosensitive region. Each of the discrete electron repulsive elements may repel electrons in the material toward a corresponding photosensitive region. Other apparatus are also disclosed, as are methods of use, methods of fabrication, and systems incorporating such apparatus.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: July 1, 2014
    Assignee: OmniVision Technologies, Inc.
    Inventor: Hidetoshi Nozaki
  • Patent number: 8748904
    Abstract: Low loss optical apertures are provided. A silicon intermediate layer sandwiched between a metal aperture layer and a dielectric layer has been found to offer a good combination of low optical loss combined with superior mechanical properties.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: June 10, 2014
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Sonny Vo, James S. Harris, Jr.
  • Patent number: 8748911
    Abstract: Light emitting systems are disclosed. The light emitting system emits an output light that has a first color. The light emitting system includes a first electroluminescent device that emits light at a first wavelength in response to a first signal. The first wavelength is substantially independent of the first signal. The intensity of the emitted first wavelength light is substantially proportional to the first signal. The light emitting system further includes a first luminescent element that includes a second electroluminescent device and a first light converting layer. The second electroluminescent device emits light at a second wavelength in response to a second signal. The first light converting layer includes a semiconductor potential well and converts at least a portion of light at the second wavelength to light at a third wavelength that is longer than the second wavelength.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: June 10, 2014
    Assignee: 3M Innovative Properties Company
    Inventors: Michael A. Haase, James A. Thielen, Catherine A. Leatherdale, Billy L. Weaver, Terry L. Smith
  • Patent number: 8723336
    Abstract: According to an embodiment, a semiconductor light emitting device includes a light emitting body including a semiconductor light emitting layer, a support substrate supporting the light emitting body, and a bonding layer provided between the light emitting body and the support substrate, the bonding layer bonding the light emitting body and the support substrate together. The device also includes a first barrier metal layer provided between the light emitting body and the bonding layer, and an electrode provided between the light emitting body and the first barrier metal layer. The first barrier layer includes a first layer made of nickel and a second layer made of a metal having a smaller linear expansion coefficient than nickel, and the first layer and the second layer are alternately disposed in a multiple-layer structure. The electrode is electrically connected to the light emitting body.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: May 13, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasuharu Sugawara
  • Patent number: 8698189
    Abstract: An OLED device includes a thin film transistor including an active layer, a gate bottom electrode, a gate top electrode, an insulating layer covering the gate electrode, and a source electrode and a drain electrode on the insulating layer contacting the active layer; an organic light-emitting device electrically connected to the thin film transistor and including a sequentially stacked pixel electrode, on the same layer as the gate bottom electrode, emissive layer, and, opposite electrode, a pad bottom electrode on the same layer as the gate bottom electrode and a pad top electrode pattern on the same layer as the gate top electrode, the pad top electrode pattern including openings exposing the pad bottom electrode, and an insulation pattern covering the upper surface of the pad top electrode pattern on the same layer as the insulating layer, on an upper surface of the pad bottom electrode.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: April 15, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sun Park, Jong-Hyun Park, Yul-Kyu Lee, Kyung-Hoon Park, Sang-Ho Moon
  • Patent number: 8692276
    Abstract: A silicon-on-insulator wafer is provided. The silicon-on-insulator wafer includes a silicon substrate having optical vias formed therein. In addition, an optically transparent oxide layer is disposed on the silicon substrate and the optically transparent oxide layer is in contact with the optical vias. Then, a complementary metal-oxide-semiconductor layer is formed over the optically transparent oxide layer.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: April 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Fuad E. Doany, Christopher V. Jahnes, Clint L. Schow, Mehmet Soyuer, Alexander V. Rylyakov
  • Patent number: 8686571
    Abstract: A structure comprises a first semiconductor substrate, a first bonding layer deposited on a bonding side the first semiconductor substrate, a second semiconductor substrate stacked on top of the first semiconductor substrate and a second bonding layer deposited on a bonding side of the second semiconductor substrate, wherein the first bonding layer is of a horizontal length greater than a horizontal length of the second semiconductor substrate, and wherein there is a gap between an edge of the second bonding layer and a corresponding edge of the second semiconductor substrate.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: April 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Ting Huang, Jung-Huei Peng, Shang-Ying Tsai, Li-Min Hung, Yao-Te Huang, Yi-Chuan Teng, Chin-Yi Cho
  • Patent number: 8674381
    Abstract: A nitride semiconductor light emitting device is provided with a substrate, an n-type nitride semiconductor layer, a p-type nitride semiconductor layer, an n-side pad electrode, a translucent electrode and a p-side pad electrode, wherein the translucent electrode is formed from an electrically conductive oxide, the n-side pad electrode adjoins the periphery of the translucent electrode and the p-side pad electrode is disposed so as to satisfy the following relationships: 0.3L?X?0.5L and 0.2L?Y?0.5L where X is the distance between ends of the p-side pad electrode and the n-side pad electrode, Y is the distance between the end of the p-side pad electrode and the periphery of the translucent electrode, L is the length of the translucent electrode on the line connecting the centroids of the p-side pad electrode and the n-side pad electrode minus the outer diameter d of the p-side pad electrode.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: March 18, 2014
    Assignee: Nichia Corporation
    Inventors: Takahiko Sakamoto, Yasutaka Hamaguchi
  • Patent number: 8643059
    Abstract: A substrate structure and method of manufacturing the same are disclosed. The substrate structure may includes a substrate on which a plurality of protrusions are formed on one surface thereof and a plurality of buffer layers formed according to a predetermined pattern and formed spaced apart from each other on the plurality of protrusions.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: February 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youn Kim, Su-hee Chae, Hyun-gi Hong, Young-jo Tak
  • Patent number: 8629468
    Abstract: A method for manufacturing a light emitting device, includes: preparing a first substrate by slicing a single crystal ingot pulled in a pulling direction tilted with respect to a first plane orientation, the slicing being in a direction substantially perpendicular to the pulling direction; preparing a second substrate including a major surface having a plane orientation substantially parallel to a plane orientation of a major surface of the first substrate; growing a stacked unit as a crystal on the major surface of the second substrate, the stacked unit including a light emitting layer; and removing the second substrate after bonding the stacked unit and the major surface of the first substrate by heating them in a joined state.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: January 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Isomoto, Chisato Furukawa
  • Patent number: 8629461
    Abstract: A light emitting device includes: a light emitting unit and a light receiving unit which are provided on a same substrate, wherein the light emitting unit includes an active layer sandwiched between a first clad layer and a second clad layer, a first electrode electrically connected to the first clad layer, and a second electrode electrically connected to the second clad layer.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: January 14, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Yasutaka Imai
  • Patent number: 8598547
    Abstract: Glitches during ion implantation of a workpiece, such as a solar cell, can be compensated for. In one instance, a workpiece is implanted during a first pass at a first speed. This first pass results in a region of uneven dose in the workpiece. The workpiece is then implanted during a second pass at a second speed. This second speed is different from the first speed. The second speed may correspond to the entire workpiece or just the region of uneven dose in the workpiece.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: December 3, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Russell J. Low, Atul Gupta, William T. Weaver
  • Patent number: 8581296
    Abstract: A compound semiconductor device having reduced contact resistance to an electrode is provided. The compound semiconductor device includes an n-substrate 3 comprising a hexagonal compound semiconductor GaN and having surfaces S1 and S2; an n-electrode 13 formed on the surface S1 of the n-substrate 3; a layered product having an n-cladding layer 5, an active layer 7, a p-cladding layer 9, and a contact layer 11 formed on the surface S2 of the n-substrate 3; and a p-electrode 15 formed on the p-cladding layer 9. The number of N atoms contained on the surface S1 of the n-substrate 3 is more than the number of Ga atoms contained on the surface S1. The electrode formed on the surface S1 is an n-electrode 13. The surface S1 has an oxygen concentration of not more than 5 atomic percent. The number of Ga atoms contained on the surface S3 of the contact layer 11 is more than the number of N atoms contained on the surface S3. The electrode formed on the surface S3 is a p-electrode 15.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: November 12, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masahiro Adachi, Shinji Tokuyama, Koji Katayama
  • Patent number: 8563991
    Abstract: An optical semiconductor device has a semiconductor substrate, an optical semiconductor region and a heater. The optical semiconductor region is provided on the semiconductor substrate and has a width smaller than that of the semiconductor substrate. The heater is provided on the optical semiconductor region. The optical semiconductor region has a cladding region, an optical waveguide layer and a low thermal conductivity layer. The optical waveguide layer is provided in the cladding region and has a refractive index higher than that of the cladding region. The low thermal conductivity layer is provided between the optical waveguide layer and the semiconductor substrate and has a thermal conductivity lower than that of the cladding region.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: October 22, 2013
    Assignee: Eudyna Devices Inc.
    Inventor: Tsutomu Ishikawa
  • Patent number: 8552447
    Abstract: A semiconductor light-emitting element includes a semiconductor laminated structure including a light-emitting layer sandwiched between first and second conductivity type layers for extracting an emitted light from the light-emitting layer on a side of the second conductivity type layer, a transparent electrode in ohmic contact with the second conductivity type layer, an insulation layer formed on the transparent electrode, an upper electrode for wire bonding formed on the insulation layer, a lower electrode that penetrates the insulation layer, is in ohmic contact with the transparent electrode and the electrode for wire bonding, and has an area smaller than that of the upper electrode in top view, and a reflective portion for reflecting at least a portion of light transmitted through a region of the transparent electrode not in contact with the lower electrode.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: October 8, 2013
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Kosuke Yahata, Takashi Mizobuchi, Takahiro Mori, Masashi Deguchi, Shingo Totani
  • Patent number: 8536610
    Abstract: A silicon-on-insulator wafer is provided. The silicon-on-insulator wafer includes a silicon substrate having optical vias formed therein. In addition, an optically transparent oxide layer is disposed on the silicon substrate and the optically transparent oxide layer is in contact with the optical vias. Then, a complementary metal-oxide-semiconductor layer is formed over the optically transparent oxide layer.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Fuad E. Doany, Christopher V. Jahnes, Clint L. Schow, Mehmet Soyuer, Alexander V. Rylyakov
  • Patent number: 8530923
    Abstract: A light-emitting diode chip (1) with a semiconductor layer sequence (2) is described, which is contacted electrically by contacts (5) via a current spreading layer (3). The contacts (5) cover around 1%-8% of the surface of the semiconductor layer sequence (2). The contacts (5) consist for example of separate contact points (51), which are arranged at the nodes of a regular grid (52) with a grid constant of 12 ?m. The current spreading layer (3) contains for example indium-tin oxide, indium-zinc oxide or zinc oxide and has a thickness in the range from 15 nm to 60 nm.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: September 10, 2013
    Assignee: OSRAM Opto Semiconductor GmbH
    Inventors: Matthias Sabathil, Lutz Hoeppel, Andreas Weimar, Karl Engl, Johannes Baur
  • Patent number: 8524517
    Abstract: Implementations and techniques for semiconductor light-emitting devices including one or more copper blend I-VII compound semiconductor material barrier layers are generally disclosed.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: September 3, 2013
    Assignee: University of Seoul Industry Cooperation Foundation
    Inventor: Doyeol Ahn
  • Patent number: 8525191
    Abstract: An optoelectronic device assembly can include: a coated element and an optoelectronic device on the coated element. The coated element can include a thermoplastic substrate and a protective weathering layer. The thermoplastic substrate can include a bisphenol-A polycarbonate homopolymer and a polycarbonate copolymer, and wherein the polycarbonate copolymer is selected from a copolymer of tetrabromobisphenol A carbonate and BPA carbonate; a copolymer of 2-phenyl-3,3-bis(4-hydroxyphenyl)phthalimidine carbonate and BPA carbonate; a copolymer of 4,4?-(1-phenylethylidene) biphenol carbonate and BPA carbonate; a copolymer of 4,4?-(1-methylethylidene) bis[2,6-dimethyl-phenol]carbonate and BPA carbonate; and combinations comprising at least one of the foregoing. The protective weathering layer can include resorcinol polyarylate and polycarbonate.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: September 3, 2013
    Assignee: Sabic Innovative Plastics IP B.V.
    Inventors: Jian Zhou, James Edward Pickett, Shreyas Chakravarti
  • Patent number: 8513683
    Abstract: An optical integrated semiconductor light emitting device with improved light emitting efficiency is provided by preventing leak current from flowing through a high defect region of the substrate. The optical integrated semiconductor light emitting device includes: a substrate, in which in a low defect region made of crystal having a first average dislocation density, one or more high defect regions having a second average dislocation density higher than the first average dislocation density are included; and a Group III-V nitride semiconductor layer which is formed on the substrate, has a plurality of light emitting device structures, and has a groove in the region including the region corresponding to the high defect region (high defect region).
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: August 20, 2013
    Assignee: Sony Corporation
    Inventors: Osamu Maeda, Tsuyoshi Fujimoto, Motonobu Takeya, Toshihiro Hashidu, Masaki Shiozaki, Yoshio Oofuji
  • Patent number: RE47188
    Abstract: The present invention provides a semiconductor device realizing reduced occurrence of a defect such as a crack at the time of adhering elements to each other. The semiconductor device includes a first element and a second element adhered to each other. At least one of the first and second elements has a pressure relaxation layer on the side facing the other of the first and second elements, and the pressure relaxation layer includes a semiconductor part having a projection/recess part including a projection projected toward the other element, and a resin part filled in a recess in the projection/recess part.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: January 1, 2019
    Assignee: Sony Corporation
    Inventors: Rintaro Koda, Takahiro Arakida, Yuji Masui, Tomoyuki Oki