With Heterojunction Patents (Class 257/85)
  • Patent number: 6835959
    Abstract: The present invention provides a semiconductor device including an element that is considered to have less environmental problem (for example iron), and a method for manufacturing the same. More specifically, in a semiconductor device having multiple layers, at least one of the layers includes iron silicide. At least part of the layer including iron silicide is subjected to oxidation processing.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: December 28, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventor: Toshihiko Ouchi
  • Patent number: 6835956
    Abstract: A nitride semiconductor device includes a GaN substrate having a single-crystal GaN layer at least on its surface and plurality of device-forming layers made of nitride semiconductor. The device-forming layer contacting the GaN substrate has a coefficient of thermal expansion smaller than that of GaN, so that a compressive strain is applied to the device-forming layer. This result in prevention of crack forming in the device-forming layers, and a lifetime characteristics of the nitride semiconductor device is improved.
    Type: Grant
    Filed: February 8, 2000
    Date of Patent: December 28, 2004
    Assignee: Nichia Corporation
    Inventors: Shinichi Nagahama, Shuji Nakamura
  • Patent number: 6831304
    Abstract: A pn-junction-type semiconductor light-emitting device having a single-crystal silicon (Si) substrate of first conduction type; a first boron-phosphide-based semiconductor layer of first conduction type provided on the substrate; a light-emitting layer formed of a Group III-V semiconductor layer of first or second conduction type which is doped with an element belonging to Group IV of the periodic table provided on the first boron-phosphide-based semiconductor layer; and second boron-phosphide-based semiconductor layer of second conduction type formed of a boron-phosphide-based semiconductor layer of second conduction type containing a Group IV element provided on the light-emitting layer. The first boron-phosphide-based semiconductor layer, the light-emitting layer, and the second boron-phosphide-based semiconductor layer form a pn-junction-type hetero structure. In addition, the second conduction type is opposite the first conduction type. Also, disclosed is a method for producing the device.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: December 14, 2004
    Assignee: Showa Denko Kabushiki Kaisha
    Inventor: Takashi Udagawa
  • Patent number: 6828589
    Abstract: An optical semiconductor device comprising a plurality of semiconductor lasers formed on a single substrate is provided, in which each of said semiconductor lasers emits a laser lights having designed different oscillating wavelength. This optical semiconductor device is provided by maintaining the coupling coefficient of each of said semiconductor lasers at a constant value by adjusting the composition of an optical guide layer or the mask width for the MOVPE growth.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: December 7, 2004
    Assignee: NEC Compound Conductor Devices, Ltd.
    Inventor: Yasutaka Sakata
  • Patent number: 6828594
    Abstract: A simple and low cost semiconductor light emission element exerting high performance and a process for producing the same are provided. The semiconductor light emission element contains a nitride semiconductor layer containing at least one or more element selected from Group IIIA elements and one or more element selected from Group VA element, a dissimilar semiconductor having a polarity different from the nitride semiconductor layer, and a light emission layer provided between the dissimilar semiconductor and the nitride semiconductor, in which electrons or positive holes are injected from semiconductors of the dissimilar semiconductor and the nitride semiconductor layer to the light emission layer to carry out light emission.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: December 7, 2004
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Shigeru Yagi
  • Patent number: 6818975
    Abstract: The present invention provides a bump forming apparatus (101, 501) which can prevent charge appearance semiconductor substrates (201, 202) from pyroelectric breakdown and physical failures, a method carried out by the bump forming apparatus for removing charge of charge appearance semiconductor substrates, a charge removing unit for charge appearance semiconductor substrates, and a charge appearance semiconductor substrate. At least when the wafer is cooled after the bump bonding is connected on the wafer, electric charge accumulated on the wafer (202) because of the cooling is removed through direct contact with a post-forming bumps heating device (170), or the charge is removed by a decrease in temperature control so that charge can be removed in a noncontact state. Therefore, an amount of charge of the wafer can be reduced in comparison with the conventional art, so that the wafer is prevented from pyroelectric breakdown and damage such as a break or the like to the wafer itself.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: November 16, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shoriki Narita, Yasutaka Tsuboi, Masahiko Ikeya, Takaharu Mae, Shinji Kanayama
  • Patent number: 6815730
    Abstract: A nitride-based semiconductor light-emitting device includes a GaN-based substrate and a semiconductor stacked-layer structure including a plurality of nitride-based semiconductor layers grown on the GaN-based substrate by vapor deposition. The GaN-based substrate has an interface region contacting the semiconductor stacked-layer structure and the interface region contains oxygen atoms of concentration n in the range of 2×1016≦n≦1022 cm−3.
    Type: Grant
    Filed: January 28, 2002
    Date of Patent: November 9, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Eiji Yamada
  • Publication number: 20040206967
    Abstract: A porous substrate for epitaxial growth includes an underlying layer made of III-nitride semiconductor which is grown on a sapphire substrate, a void-formation preventive layer which is grown on the underlying layer, a porous III-nitride semiconductor layer and a porous metallic layer on the porous III-nitride semiconductor layer.
    Type: Application
    Filed: April 12, 2004
    Publication date: October 21, 2004
    Applicant: HITACHI CABLE, LTD.
    Inventors: Yuichi Oshima, Masatomo Shibata
  • Publication number: 20040206965
    Abstract: A light emitting device may include a light emitting layer such as an organic semiconductor material, one or more feedback structures, and a coupling structure. The one or more feedback structures may cause light emitted by the light emitting layer to be fed back through it along an axis in the plane of the device, thereby promoting the stimulated emission of light in the light emitting layer. The coupling structure couples some fraction of the feedback light out of the device. The coupled light may be emitted along an axis substantially normal to the plane of the device or at predetermined angles. The coupling and feedback structures may have a corrugated structure, a continuous variation of refractive index along an axis in the device plane, a period refractive index, or any combination thereof. The coupling and feedback structures may be separate, share common portion or combined together.
    Type: Application
    Filed: April 16, 2003
    Publication date: October 21, 2004
    Inventor: Allan Kenneth Evans
  • Publication number: 20040206966
    Abstract: A group-III nitride semiconductor stack comprises a single-crystal substrate, a first group-III nitride layer formed on a principal surface of the single-crystal substrate, a graded low-temperature deposited layer formed on the group-III nitride layer and made of nitride in which group-III element composition is continuously changed, and a second group-III nitride layer formed on the graded low-temperature deposited layer.
    Type: Application
    Filed: March 23, 2004
    Publication date: October 21, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideto Sugawara, Tsunenori Hiratsuka
  • Patent number: 6806508
    Abstract: A photodetector comprising a gallium nitride substrate, at least one active layer disposed on the substrate, and a conductive contact structure affixed to the active layer and, in some embodiments, the substrate. The invention includes photodetectors having metal-semiconductor-metal structures, P-i-N structures, and Schottky-barrier structures. The active layers may comprise Ga1−x−yAlxInyN1−z−wPzAsw, or, preferably, Ga1−xAlxN. The gallium nitride substrate comprises a single crystal gallium nitride wafer and has a dislocation density of less than about 105 cm−2. A method of making the photodetector is also disclosed.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: October 19, 2004
    Assignee: General Electic Company
    Inventors: Mark Philip D'Evelyn, Nicole Andrea Evers, Kanin Chu
  • Patent number: 6803603
    Abstract: Part of light emitted downward by an active layer is reflected by an electrode functioning as a reflective layer, and travels upward to radiate outside. Since the electrode is made of a metal, it reflects almost all light regardless of its incident angle, and light can be efficiently extracted.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: October 12, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Nitta, Haruhiko Okazaki, Yukio Watanabe, Chisato Furukawa
  • Patent number: 6791150
    Abstract: A thermoelectric semiconductor has a P-type semiconductor and an N-type semiconductor disposed in parallel. A heat absorbing side of the thermoelectric semiconductor and a substrate that has an optical element mounted on its upper surface are disposed on the same plane. A heat radiation side of the thermoelectric semiconductor is disposed such that a direction from the heat absorbing side to the heat radiation side of the thermoelectric semiconductor is parallel with the upper surface of the substrate. Based on this arrangement, it is possible to set the environmental temperature of an optical module to the same level as the operation temperature of a laser diode.
    Type: Grant
    Filed: December 24, 2002
    Date of Patent: September 14, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Shinichi Takagi
  • Patent number: 6787383
    Abstract: The light-emitting device 100 has an ITO electrode layer 8 for applying drive voltage for light emission to a light emitting layer section 24, where the light from the light emitting layer section 24 is extracted as being passed through the ITO electrode layer 8. Between the light emitting layer section 24 and the ITO electrode layer 8, an electrode contact layer 7 composed of In-containing GaAs is located so as to contact with such ITO electrode layer 8, where occupied areas and unoccupied areas for the electrode contact layer 7 are arranged in a mixed manner on the contact interface with the transparent electrode layer 8. The electrode contact layer 7 can be obtained by annealing a stack 13, which comprises a GaAs layer 7″ formed on the light emitting layer section 24 and the ITO electrode layer 8 formed so as to contact with the GaAs layer 7″, to thereby allow In to diffuse from the ITO electrode layer to the GaAs layer 7″.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: September 7, 2004
    Assignees: Shin-Etsu Hanotai Co., Ltd., Nanoteco Corporation
    Inventors: Shunichi Ikeda, Masato Yamada, Nobuhiko Noto, Shinji Nozaki, Kazuo Uchida, Hiroshi Morisaki
  • Patent number: 6784074
    Abstract: A method for fabrication of defect-free epitaxial layers on top of a surface of a first defect-containing solid state material includes the steps of selective deposition of a second material, having a high temperature stability, on defect-free regions of the first solid state material, followed by subsequent evaporation of the regions in the vicinity of the defects, and subsequent overgrowth by a third material forming a defect-free layer.
    Type: Grant
    Filed: June 6, 2003
    Date of Patent: August 31, 2004
    Assignee: NSC-Nanosemiconductor GmbH
    Inventors: Vitaly Shchukin, Nikolai Ledentsov
  • Patent number: 6780750
    Abstract: Disclosed is a photodiode having a p-type electrode of a mushroom shape. The p-type electrode is formed in a mushroom shape, so that the contact area faced by the spreading region of a dopant for the photodiode and the electrode can be minimized and the capacitance of the photodiode can be reduced. Further, the p-type electrode is configured to have a broader width in its upper end, thus allowing the wire bonding to be performed easily.
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: August 24, 2004
    Assignee: Samsung Electronics Co. Ltd.
    Inventor: Seung-Kee Yang
  • Publication number: 20040135157
    Abstract: A combined semiconductor apparatus includes a semiconductor substrate having an integrated circuit, a planarized region formed in a surface of the semiconductor substrate, and a semiconductor thin film including at least one semiconductor device and bonded on the planarized region. A surface of the semiconductor thin film, in which the semiconductor device is formed, is disposed on a side of the planarized region. The apparatus may further include a planarized film disposed between the planarized region and the semiconductor thin film.
    Type: Application
    Filed: December 23, 2003
    Publication date: July 15, 2004
    Inventors: Mitsuhiko Ogihara, Hiroyuki Fujiwara, Masaaki Sakuta, Ichimatsu Abiko
  • Publication number: 20040135158
    Abstract: Disclosed are a vertical GaN based light-emitting device (LED) structure and the manufacturing method thereof. In the structure and the corresponding method, a substrate unit having a mask is used to form a multi-layer epitaxial structure and the substrate and the multi-layer epitaxial structure are separated at the mask. After the multi-layer epitaxial structure is extracted, a metal reflector may be disposed thereunder. Next, a conductive substrate is bonded to the metal reflector. Next, an upper surface of the multi-layer structure is disposed with a p-electrode and a bottom side of the conductive substrate with an n-electrode whereby an vertical LED structure is formed.
    Type: Application
    Filed: December 29, 2003
    Publication date: July 15, 2004
    Applicant: Supernova Optoelectronics Corp.
    Inventor: Schang-Jing Hon
  • Patent number: 6759686
    Abstract: A light emitting diode (LED), and a method for producing the same. The LED includes a substrate that may be made of silicon, a first conductive layer on one side, and a porous insulating layer on the opposite side. The insulating layer defines microcavities therein, the microcavities having sharp tips on their inner surfaces. The microcavities have gas inside. A second conductive layer is disposed over the insulating layer. When an electrical potential is applied between the conductive layers, the gas-filled microcavities act as plasma discharge lamps, emitting light. The light may be in the ultraviolet portion of the spectrum. The method includes etching a substrate to produce a porous insulating layer on one side, depositing a first conductive layer on the opposite side, and depositing a second conductive layer over the insulating layer. The microcavities in the insulating layer are then filled with gas.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: July 6, 2004
    Inventors: Kok Wai Cheah, Wai Kwok Wong, Hoi Lam Tam
  • Patent number: 6759139
    Abstract: A nitride-based semiconductor element enabling formation of a nitride-based semiconductor layer having low dislocation density, consisting of a material different from that of an underlayer, on the underlayer with a small thickness is obtained. This nitride-based semiconductor element comprises a plurality of mask layers formed at a prescribed interval to be in contact with the upper surface of the underlayer while partially exposing the underlayer and the nitride-based semiconductor layer, formed on the upper surface of the underlayer and the mask layers, consisting of the material different from that of the underlayer. The minimum distance between adjacent mask layers is smaller than the width of an exposed part of the underlayer located between the adjacent mask layers.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: July 6, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tatsuya Kunisato, Nobuhiko Hayashi, Hiroki Ohbo, Masayuki Hata, Tsutomu Yamaguchi
  • Publication number: 20040124427
    Abstract: An apparatus includes a crystalline substrate having a top surface, a crystalline semiconductor layer located on the top surface, and a plurality of dielectric regions. The crystalline semiconductor layer includes group III-nitride and has first and second surfaces. The first surface is in contact with the top surface. The second surface is separated from the top surface by semiconductor of the crystalline semiconductor layer. The dielectric regions are located on the second surface. Each dielectric region is distant from the other dielectric regions and covers an end of an associated lattice defect. Each lattice defect threads the crystalline semiconductor layer.
    Type: Application
    Filed: December 12, 2003
    Publication date: July 1, 2004
    Inventors: Julia Wan-Ping Hsu, Michael James Manfra, Nils Guenter Weimann
  • Publication number: 20040119080
    Abstract: A semiconductor light-emitting device 1 comprises a first semiconductor layer 3, an active layer 5, a second semiconductor layer 7, a third semiconductor layer 9, and a current block semiconductor layer 11. The first semiconductor layer 3 is provided on the surface of GaAs semiconductor. The active layer 5 is provided on the first semiconductor layer 3. The second semiconductor layer 7 is provided on the active layer 5. The third semiconductor layer 9 is provided on the second semiconductor layer 7, and has a pair of side faces 9a, 9b. The current block semiconductor layer 11 is provided on the second semiconductor layer 7 and a pair of side faces 9a, 9b of the third semiconductor layer 9. The third semiconductor layer of a stripe form 9 extends along a predetermined axis. The current block semiconductor layer 11 has a conductivity type different from the third semiconductor layer 9. The active layer 5 is formed of III-V compound semiconductor including at least nitrogen as a V group member.
    Type: Application
    Filed: August 12, 2003
    Publication date: June 24, 2004
    Inventors: Jun-ichi Hashimoto, Tsukuru Katsuyama
  • Publication number: 20040119081
    Abstract: The semiconductor laser device includes an active layer, a p-type cladding layer, and a p-type cap layer. The layers are sequentially stacked so that the semiconductor laser device is provided. The p-type cap layer includes both a p-type dopant and an n-type dopant. In another aspect, the p-type cap layer includes a first layer including a first p-type dopant and a second layer including a second p-type dopant having a diffusion coefficient smaller than that of the first p-type dopant. The first layer is far from the active layer, and the second layer is close to the active layer. In further aspect, the p-type cap layer includes carbon (C) as a p-type dopant. According to these configuration, the p-type dopant can be prevented from being diffused in the active layer and the p-type cladding layer.
    Type: Application
    Filed: December 11, 2003
    Publication date: June 24, 2004
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masayoshi Takemi, Kenichi Ono, Yoshihiko Hanamaki, Chikara Watatani, Tetsuya Yagi, Harumi Nishiguchi, Motoko Sasaki, Shinji Abe, Yasuaki Yoshida
  • Patent number: 6753214
    Abstract: A PIN photodetector includes reduced parasitic capacitance and is suitable for high-speed applications. Metal interconnect leads are coupled to the photodetector and extend over electrically insulating regions which reduce or eliminate parasitic capacitance. The electrically insulating regions may be formed by a deep proton implantation process which introduces impurities into the N-type layer, P-type layer and intrinsic layer in portions of the inactive area according to one embodiment. In another embodiment, the electrically insulating regions may be formed by removing parts of the film stack that includes N-type layer, P-type layer and intrinsic layer, from portions of the inactive area, introducing impurities and optionally adding a dielectric material. The PIN photodetector may take on the shape of a mesa to provide contact to each of the upper and lower electrodes.
    Type: Grant
    Filed: February 15, 2002
    Date of Patent: June 22, 2004
    Assignee: Optical Communication Products, Inc.
    Inventors: David Brinkmann, John Lindemann, Jeffrey Scott
  • Patent number: 6750486
    Abstract: A semiconductor device with p-channel and n-channel field effect devices formed on a common substrate, where the drain and source regions of the n-channel field effect device are formed within a silicon epitaxial layer formed on a silicon layer germanium relax which is formed on a silicon germanium buffer layer with a graduated germanium concentration. Additionally, drain and source regions of the p-channel field effect device are formed within a silicon-germanium compound layer formed on the substrate and the silicon epitaxial cap layer formed on the silicon-germanium compound layer.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: June 15, 2004
    Assignee: Sony Corporation
    Inventors: Minoru Sugawara, Takashi Noguchi
  • Publication number: 20040104396
    Abstract: A light-emitting diode includes: a semiconductor substrate; and a layered structure, made of an AlGaInP type compound semiconductor material and provided on the semiconductor substrate. The layered structure includes: a light-emitting structure composed of a pair of cladding layers and an active layer for emitting light provided between the pair of cladding layers; and a current diffusion layer which is lattice-mismatched with the light-emitting structure.
    Type: Application
    Filed: November 7, 2003
    Publication date: June 3, 2004
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Nakatsu, Osamu Yamamoto
  • Patent number: 6744072
    Abstract: Substrates having increased thermal conductivity are provided, comprising a body having opposed surfaces and a cavity that opens on at least one surface, the cavity containing at least one material having a greater thermal conductivity than the body. Devices are provided comprising a substrate and a semiconductor over a surface of the substrate. Methods of forming devices according to the invention are also provided.
    Type: Grant
    Filed: October 2, 2001
    Date of Patent: June 1, 2004
    Assignee: Xerox Corporation
    Inventors: Linda T. Romano, Michael A. Kneissl, John E. Northrup
  • Publication number: 20040099871
    Abstract: There is provided a monocrystalline gallium nitride localized substrate suitable for manufacturing electronic-optical united devices in which electronic devices and optical devices are mixedly mounted on the same silicon substrate.
    Type: Application
    Filed: November 4, 2003
    Publication date: May 27, 2004
    Applicants: OSAKA PREFECTURE, HOSIDEN CORPORATION
    Inventors: Katsutoshi Izumi, Motoi Nakao, Yoshiaki Ohbayashi, Keiji Mine, Seisaku Hirai, Fumihiko Jobe, Tomoyuki Tanaka
  • Patent number: 6737678
    Abstract: In a wafer having an LD structure 251 formed on a GaN-based substrate 250, cleavage guide grooves 252 are formed in its surface by scribing from above the LD structure 251 with a diamond needle. The cleavage guide grooves 252 are formed one along each of stripe-shaped waveguides 253 formed parallel to the <1-100>direction of the wafer, and are formed in the shape of broken lines in the <11-20>direction of the wafer.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: May 18, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Toshiyuki Kawakami, Yukio Yamasaki, Shigetoshi Ito, Susumu Omi
  • Publication number: 20040089869
    Abstract: A III group nitride system compound semiconductor light emitting element has: a transparent substrate that is of a material except for III group nitride system compound semiconductor; a convex light trapping member that is formed directly or through a buffer layer on the surface of the transparent substrate; and a III group nitride system compound semiconductor layer that is formed on the surface of the transparent substrate. The light trapping member has a refractive index substantially equal to that of the transparent substrate or closer to that of the transparent substrate than that of the III group nitride system compound semiconductor layer.
    Type: Application
    Filed: October 29, 2003
    Publication date: May 13, 2004
    Applicant: Toyoda Gosei Co., Ltd.
    Inventor: Toshiya Uemura
  • Patent number: 6734464
    Abstract: A laser diode comprises a first cladding layer having a first conductivity, a second cladding layer having a second conductivity, an active layer located between the first cladding layer and the second cladding layer and extending from one end surface to the other end surface, a first electrode configured to inject a carrier with a first polarity into the active layer via the first cladding layer, and a second electrode configured to inject a carrier with a second polarity into the active layer via the second cladding layer. The active layer comprises a first active region and a second active region, which are arranged alternately and periodically from one end surface to the other end surface in the direction of light propagation, and the first active region and the second active region define type-II hetero junction between them.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: May 11, 2004
    Assignee: Fujitsu Limited
    Inventor: Norihiko Sekine
  • Publication number: 20040079949
    Abstract: In the present invention, (Ti1−xAx)N [in which A is at least one kind of metal selected from the group consisting of Al, Ga, and In] is used as a metal nitride layer, so that a Group III nitride compound semiconductor layer is formed on the metal nitride layer. When a Ti layer is formed between the metal nitride layer having a sufficient thickness and a substrate and the titanium layer is removed, a Group III nitride compound semiconductor device using metal nitride as a substrate can be obtained.
    Type: Application
    Filed: July 14, 2003
    Publication date: April 29, 2004
    Inventors: Toshiaki Chiyo, Jun Ito, Naoki Shibata
  • Patent number: 6727112
    Abstract: A method of manufacturing a semiconductor optical device comprising the steps of: providing a substrate having an active layer thereon; providing an aluminium-bearing layer, the aluminium bearing layer being adjacent the active layer; and oxidising the aluminium-bearing layer substantially entirely.
    Type: Grant
    Filed: August 16, 2001
    Date of Patent: April 27, 2004
    Assignee: Agency for Science, Technology and Research
    Inventors: Zhi-Jie Wang, Soo-Jin Chua, Fan Zhou, Wei Wang
  • Patent number: 6724012
    Abstract: A semiconductor device in which a reduction in size and thinness are realized is provided. The semiconductor device of the present invention can realize a reduction in size by forming light emitting elements as a light source, and photodiodes as photoelectric conversion elements on the same substrate. Further, it becomes possible to control two signal lines by using one driver circuit with using an output switching circuit. As a result, it becomes possible to reduce the area occupied by the driver circuits of the semiconductor device, and the semiconductor device can be made smaller.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: April 20, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Publication number: 20040048406
    Abstract: An EA-DFB module including a DFB laser diode and an EA modulator formed on an InP first-conductivity-type substrate has a mesa stripe, a current blocking structure formed on both side surfaces of the mesa strip and a second InP cladding layer formed on top of the mesa stripe and the current blocking structure. The current blocking structure includes a Fe-doped semi-insulating film, a first conductivity-type buried layer and a carrier-depleted layer. The carrier-depleted layer reduces the parasitic capacitance at the boundary between the first-conductivity-type buried layer and the second InP cladding layer.
    Type: Application
    Filed: July 14, 2003
    Publication date: March 11, 2004
    Applicant: THE FURUKAWA ELECTRIC CO., LTD.
    Inventors: Nariaki Ikeda, Takeharu Yamaguchi, Satoshi Arakawa, Nobumitsu Yamanaka, Akihiko Kasukawa, Ryusuke Nakasaki
  • Patent number: 6686611
    Abstract: In a nitride semiconductor of BpAlqGarInsN (0≦p≦1, 0≦q≦1, 0≦r≦1, 0≦s≦1, p+q+r+s=1), in particular a p-type nitride compound semiconductor, a point defect concentration of the p-type semiconductors is set to 1×1019 cm−3 or more. This makes it possible to obtain a high carrier concentration at room temperature.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: February 3, 2004
    Assignee: Sony Corporation
    Inventors: Hiroyuki Okuyama, Hiroshi Nakajima, Fumihiko Nakamura
  • Publication number: 20030234401
    Abstract: A wafer having heterostructure therein is formed using a substrate with recesses formed within a dielectric layer. A magnetized magnetic layer or a polarized electret material is formed at the bottom of each recess. The magnetized magnetic layer or a polarized electret material provides a predetermined magnetic or electrical field pattern. A plurality of heterostructures is formed from on an epitaxial wafer wherein each heterostructure has formed thereon a non-magnetized magnetic layer that is attracted to the magnetized magnetic layer formed at the bottom of each recess or dielectric layer that is attracted to the polarized electret material formed at the bottom of each recess. The plurality of heterostructures is etched from the epitaxial wafer to form a plurality of heterostructure pills.
    Type: Application
    Filed: January 24, 2003
    Publication date: December 25, 2003
    Inventors: Clifton G. Fonstad, Markus Zahn
  • Patent number: 6661027
    Abstract: For manufacturing a semiconductor device, such as thin-film solar battery, comprising a base body made of an organic high polymer material, an oxide electrode film and semiconductor thin film each containing at least one kind of group IV elements on the oxide electrode film, one of the semiconductor thin films in contact with the oxide electrode film is stacked by sputtering in a non-reducing atmosphere such as atmosphere not containing hydrogen gas, for example. Thereby, it is ensured that granular products as large as and beyond 3 nm are not contained substantially at the interface between the oxide electrode film and that semiconductor thin film. Therefore, a semiconductor thin film such as amorphous semiconductor thin film can be stacked with enhanced adherence on a plastic substrate having an oxide electrode film like ITO film on its surface.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: December 9, 2003
    Assignee: Sony Corporation
    Inventors: Akio Machida, Dharam Pal Gosain, Takashi Noguchi, Setsuo Usui
  • Publication number: 20030222265
    Abstract: The present invention relates to a photoreceiver and method of manufacturing the same. For the purpose of a selective detection of a specific wavelength, if a waveguide type photodetector using a multiple quantum-well layer having a quantum confined stark effect as an optical absorption layer, the wavelength that is absorbed by the stark effect by which the transition energy edge of the optical absorption band is varied depending on the intensity of an electric field applied to the multiple quantum-well layer is varied. Thus, a wavelength selective detection characteristic can be varied simply implemented. The waveguide type photodetector of this structure is integrated on a semi-insulating InP substrate with a heterogeneous bipolar transistor having an n+InP/p+InGaAs/n−InGaAs/n+InGaAsP high-gain amplification characteristic.
    Type: Application
    Filed: July 30, 2002
    Publication date: December 4, 2003
    Inventors: Eun Soo Nam, Heacheon Kim
  • Patent number: 6653166
    Abstract: The method produces coherent dislocation-free regions from initially dislocated and/or defect-rich lattice mismatched layer grown on top of the substrate having a different lattice constant, which does not contain any processing steps before of after the lattice-mismatched layer growth. The process preferably uses in situ formation of a cap layer on top of a dislocated layer. The cap layer preferably has a lattice parameter close to that in the underlying substrate, and different from that in the lattice mismatched layer in no strain state. Under these conditions, the cap layer undergoes elastic repulsion from the regions in the vicinity of the dislocations, where the lattice parameter is the most different from that in the substrate. The cap layer is absent in these regions.
    Type: Grant
    Filed: May 9, 2001
    Date of Patent: November 25, 2003
    Assignee: NSC-Nanosemiconductor GmbH
    Inventor: Nikolai Ledentsov
  • Publication number: 20030213964
    Abstract: A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer of improved epitaxial quality deposited on a III-V nitride material substrate, e.g., of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V/III ratio in a range of from about 1 to about 105, nitrogen source material partial pressure in a range of from about 1 to about 103 torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0.1 to about 102 microns per hour.
    Type: Application
    Filed: December 6, 2002
    Publication date: November 20, 2003
    Inventors: Jeffrey S. Flynn, George R. Brandes, Robert P. Vaudo, David M. Keogh, Xueping Xu, Barbara E. Landini
  • Publication number: 20030205713
    Abstract: A light emitting semiconductor device, which includes a Ga0.9In0.1As0.97 active layer disposed between lower n-Ga0.5In0.5P and upper p-Ga0.5In0.5P cladding layers, being provided with lower and upper GaAs spacing layers each intermediate the active layer and the cladding layer. The active layer is approximately lattice-matched to a GaAs substrate and has a thickness of about 0.1 &mgr;m with a photoluminescence peak wavelength of approximately 1.3 &mgr;m, and the GaAs spacing layers each have a thickness of about 2 nm.
    Type: Application
    Filed: March 31, 2003
    Publication date: November 6, 2003
    Inventor: Shunichi Sato
  • Publication number: 20030201449
    Abstract: A semiconductor light-emitting device, including a first substrate of a first conductivity type, a first bonding layer provided on the first substrate and consisting essentially of a GaP material of the first conductivity type, a second bonding layer provided on the first bonding layer, coincident with the first bonding layer in the planar direction of the crystal, having the first conductivity type, and consisting essentially of a material represented by a formula InxGayP, where 0≦x, y≦1, and x+y=1, and a light-emitting layer comprising a first cladding layer, an active layer, and a second cladding layer, which are successively provided on the second bonding layer, each of the active layer and first and second cladding layers consisting essentially of a material represented by a formula InxGayAlzP, where x+y+z=1, and 0≦x, y, z≦1.
    Type: Application
    Filed: May 5, 2003
    Publication date: October 30, 2003
    Inventors: Ryo Saeki, Hideto Sugawara, Yukio Watanabe, Tamotsu Jitosho
  • Patent number: 6633056
    Abstract: A method, structure and article of manufacture related to hetero-integration of dissimilar semiconductor materials. A mask is created on a semiconductor substrate, wherein the mask includes one or more openings, and each of the openings includes one or more overhangs. The overhangs cover a hetero-epitaxial interface region between a film expitaxially grown on the substrate and the substrate itself, thereby preventing a “line-of-sight” view along a surface norm of the substrate in the hetero-epitaxial interface region between the epitaxial film and the substrate. There is only one hetero-epitaxial interface region for each of the openings, which results in only one epitaxial growth front coalescence per opening, thereby reducing the number of highly defective regions from epitaxial growth front coalescence by a factor of two.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: October 14, 2003
    Assignee: The Regents of the University of California
    Inventor: Ya-Hong Xie
  • Publication number: 20030173571
    Abstract: An active semiconductor device, such as, buried heterostructure semiconductor lasers, LEDs, modulators, photodiodes, heterojunction bipolar transistors, field effect transistors or other active devices, comprise a plurality of semiconductor layers formed on a substrate with one of the layers being an active region. A current channel is formed through this active region defined by current blocking layers formed on adjacent sides of a designated active region channel where the blocking layers substantially confine the current through the channel. The blocking layers are characterized by being an aluminum-containing Group III-V compound, i.e., an Al-III-V layer, intentionally doped with oxygen from an oxide source. Also, wet oxide process or a deposited oxide source may be used to laterally form a native oxide of the Al-III-V layer. An example of a material system for this invention useful at optical telecommunication wavelengths is InGaAsP/InP where the Al-III-V layer comprises InAlAs:O or InAlAs:O:Fe.
    Type: Application
    Filed: December 16, 2002
    Publication date: September 18, 2003
    Inventors: Fred A. Kish, Sheila K. Mathis, Charles H. Joyner, Richard P. Schneider
  • Publication number: 20030164507
    Abstract: The present invention is a semiconductor structure for light emitting devices that can emit in the red to ultraviolet portion of the electromagnetic spectrum. The semiconductor structure includes a first cladding layer of a Group III nitride, a second cladding layer of a Group III nitride, and an active layer of a Group III nitride that is positioned between the first and second cladding layers, and whose bandgap is smaller than the respective bandgaps of the first and second cladding layers. The semiconductor structure is characterized by the absence of gallium in one or more of these structural layers.
    Type: Application
    Filed: March 1, 2003
    Publication date: September 4, 2003
    Inventors: John Adam Edmond, Kathleen Marie Doverspike, Hua-Shuang Kong, Michael John Bergmann
  • Publication number: 20030160253
    Abstract: A pn-junction-type boron-phosphide-based semiconductor light-emitting device having a single-crystal silicon (Si) substrate of first conduction type; a first boron-phosphide-based semiconductor layer of first conduction type provided on the substrate; a light-emitting layer formed of a Group III-V semiconductor layer of first or second conduction type which is doped with an element belonging to Group IV of the periodic table provided on the first boron-phosphide-based semiconductor layer; and second boron-phosphide-based semiconductor layer of second conduction type formed of a boron-phosphide-based semiconductor layer of second conduction type containing a Group IV element provided on the light-emitting layer. The first boron-phosphide-based semiconductor layer, the light-emitting layer, and the second boron-phosphide-based semiconductor layer form a pn-junction-type hetero structure. In addition, the second conduction type is opposite the first conduction type.
    Type: Application
    Filed: February 24, 2003
    Publication date: August 28, 2003
    Applicant: SHOWA DENKO K.K.
    Inventor: Takashi Udagawa
  • Publication number: 20030160232
    Abstract: A nitride semiconductor substrate including (a) a supporting substrate, (b) a first nitride semiconductor layer having a periodical T-shaped cross-section, having grown from periodically arranged stripe-like, grid-like or island-like portions on the supporting substrate, and (c) a second nitride semiconductor substrate covering said supporting substrate, having grown from the top and side surfaces of said first nitride semiconductor layer, wherein a cavity is formed under the second nitride semiconductor layer.
    Type: Application
    Filed: March 18, 2003
    Publication date: August 28, 2003
    Applicant: Nichia Corporation
    Inventors: Tokuya Kozaki, Hiroyuki Kiyoku, Kazuyuki Chocho, Hitoshi Maegawa
  • Patent number: 6610995
    Abstract: A gallium nitride-based III-V Group compound semi-conductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: August 26, 2003
    Assignee: Nichia Corporation
    Inventors: Shuji Nakamura, Takao Yamada, Masayuki Senoh, Motokazu Yamada, Kanji Bando
  • Publication number: 20030146444
    Abstract: An AlGaInP layer is formed on a substrate made of GaAs, and an AlGaAs layer is formed on the AlGaInP layer via a buffer layer therebetween. The buffer layer has a thickness of about 1.1 nm and is made of AlGaInP whose Ga content is smaller than that of the AlGaInP layer. The buffer layer may alternatively be made of AlGaAs whose Al content is smaller than that of the AlGaAs layer.
    Type: Application
    Filed: January 15, 2003
    Publication date: August 7, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Toshikazu Onishi