With Heterojunction Patents (Class 257/94)
  • Patent number: 8927961
    Abstract: Disclosed is a semiconductor light emitting device including a first conductive semiconductor layer including an n-type dopant, an active layer, and a second to sixth conductive semiconductor layers including a p-type dopant. The third to sixth conductive semiconductor layers includes an AlGaN-based semiconductor on the active layer, and the second conductive semiconductor layer includes a GaN-based semiconductor layer on the sixth conductive semiconductor layer. The active layer includes plurality of quantum barrier layers and plurality of quantum well layers and includes a cycle of 2 to 10. The plurality of quantum well layers include an InGaN semiconductor and at least one of the plurality of quantum barrier layers includes a GaN-based semiconductor. The sixth conductive semiconductor layer has a thickness of about 5 nm to about 100 nm.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: January 6, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: Kyong Jun Kim
  • Patent number: 8928015
    Abstract: A light emitting device including a first conductive type semiconductor layer, an active layer on the first conductive type semiconductor layer, a second conductive type semiconductor layer on the active layer, an electrode layer on the second conductive type semiconductor layer, a first electrode on the first conductive type semiconductor layer, and a second electrode on the second conductive type semiconductor layer and in an opening, the opening being in the electrode layer, wherein the second electrode has a first portion in the opening and a second portion extending from the first portion and overlapping at least a portion of the first electrode.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: January 6, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventors: Woo Sik Lim, Sung Ho Choo
  • Patent number: 8921887
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The device also includes a first electrode layer having electrical continuity with the first semiconductor layer and a second electrode layer provided on the second semiconductor layer, the second electrode layer including a metal portion having a thickness not less than 10 nanometers and not more than 100 nanometers along a direction from the first semiconductor layer to the second semiconductor layer.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: December 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kumi Masunaga, Ryota Kitagawa, Akira Fujimoto, Koji Asakawa, Takanobu Kamakura, Shinji Nunotani
  • Publication number: 20140374784
    Abstract: A light emitting device includes a light emitting structure below a substrate, in which at least one first contact area and at least one second contact area are defined. A plurality of layers having mutually different refractive indexes is provided below the light emitting structure.
    Type: Application
    Filed: June 23, 2014
    Publication date: December 25, 2014
    Applicant: LG INNOTEK CO., LTD.
    Inventor: Young Hoon KIM
  • Patent number: 8916857
    Abstract: A light-emitting element disclosed in the present invention includes a light-emitting layer and a first layer between a first electrode and a second electrode, in which the first layer is provided between the light-emitting layer and the first electrode. The present invention is characterized by the device structure in which the first layer comprising a hole-transporting material is doped with a hole-blocking material or an organic compound having a large dipole moment. This structure allows the formation of a high performance light-emitting element with high luminous efficiency and long lifetime. The device structure of the present invention facilitates the control of the rate of the carrier transport, and thus, leads to the formation of a light-emitting element with a well-controlled carrier balance, which contributes to the excellent characteristics of the light-emitting element of the present invention.
    Type: Grant
    Filed: November 24, 2012
    Date of Patent: December 23, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoko Shitagaki, Satoshi Seo, Ryoji Nomura
  • Patent number: 8916883
    Abstract: A light emitting device includes a light emitting structure comprising a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer; a reflective layer formed under the light emitting structure; and a transparent supporting layer formed between the light emitting structure and the reflective layer, to emit a light generated from the active layer; and a conductive layer formed under the reflective layer, to surround the reflective layer.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: December 23, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Hwan Hee Jeong, Sang Youl Lee
  • Publication number: 20140367715
    Abstract: Disclosed are a light emitting device, a method of fabricating the light emitting device, a light emitting device package, and a lighting system. The light emitting device includes a first conductive semiconductor layer (130), an AlGaInP-based active layer (140) on the first conductive semiconductor layer (130), a second conductive clad layer (150) on the AlGaInP-based active layer (140), a second conductive GaP layer (162) having first concentration on the second conductive clad layer (150), and a second conductive GaP layer (164) having second concentration higher than the first concentration on the second conductive GaP layer (162) having the first concentration.
    Type: Application
    Filed: June 17, 2014
    Publication date: December 18, 2014
    Applicant: LG INNOTEK CO., LTD.
    Inventor: Ki Yong HONG
  • Patent number: 8912556
    Abstract: A light emitting device and a method of manufacturing the same are disclosed. The light emitting device includes a buffer layer formed on a substrate, a nitride semiconductor layer including a first semiconductor layer, an active layer, and a second semiconductor layer, which are sequentially stacked on the buffer layer, a portion of the first semiconductor layer being exposed to the outside by performing mesa etching from the second semiconductor layer to the portion of the first semiconductor layer, and at least one nanocone formed on the second semiconductor layer.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: December 16, 2014
    Assignees: LG Electronics Inc., LG Innotek Co., Ltd.
    Inventors: Jong Wook Kim, Hyun Kyong Cho, Gyu Chul Yi, Sung Jin An, Jin Kyoung Yoo, Young Joon Hong
  • Patent number: 8908733
    Abstract: In at least one embodiment of the optoelectronic semiconductor chip (1), the latter is based on a nitride material system and comprises at least one active quantum well (2). The at least one active quantum well (2) is designed to generate electromagnetic radiation when in operation. Furthermore, the at least one active quantum well (2) comprises N successive zones (A) in a direction parallel to a growth direction z of the semiconductor chip (1), N being a natural number greater than or equal to 2. At least two of the zones (A) of the active quantum well (2) have mutually different average indium contents c. Furthermore the at least one active quantum well (2) fulfills the condition: 40??c(z)dz?2.5N?1.5?dz?80.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: December 9, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Adrian Avramescu, Désirée Queren, Christoph Eichler, Matthias Sabathil, Stephan Lutgen, Uwe Strauss
  • Publication number: 20140353699
    Abstract: Provided is a nitride semiconductor light-emitting diode having a higher light extraction efficiency and a higher polarization degree. A nitride semiconductor light-emitting diode according to the present invention comprises an active layer generating a polarized light, a first side surface, a second side surface, a third side surface, and a fourth side surface. The first and second side surfaces consist only of a plane including the Z-axis and the Y-axis. The third and fourth side surfaces are perpendicular to the first and second side surfaces and include the X-axis. The third and fourth side surfaces include an inclined surface.
    Type: Application
    Filed: June 2, 2014
    Publication date: December 4, 2014
    Applicant: Panasonic Corporation
    Inventors: TOSHIYUKI FUJITA, TOSHIYA YOKOGAWA, AKIRA INOUE
  • Publication number: 20140353698
    Abstract: A method for forming a light emitting device includes forming a monocrystalline III-V emissive layer on a monocrystalline substrate and forming a first doped layer on the emissive layer. A first contact is deposited on the first doped layer. The monocrystalline substrate is removed from the emissive layer by a mechanical process. A second doped layer is formed on the emissive layer on a side from which the substrate has been removed. The second doped layer has a dopant conductivity opposite that of the first doped layer. A second contact is deposited on the second doped layer.
    Type: Application
    Filed: July 3, 2013
    Publication date: December 4, 2014
    Inventors: Tze-Chiang Chen, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8901575
    Abstract: The present invention relates to an AC light emitting diode. An object of the present invention is to provide an AC light emitting diode wherein various designs for enhancement of the intensity of light, prevention of flickering of light or the like become possible, while coming out of a unified method of always using only one metal wire with respect to one electrode when electrodes of adjacent light emitting cells are connected through metal wires. To this end, the present invention provides an AC light emitting diode comprising a substrate; bonding pads positioned on the substrate; a plurality of light emitting cells arranged in a matrix form on the substrate; and a wiring means electrically connecting the bonding pads and the plurality of light emitting cells, wherein the wiring means includes a plurality of metal wires connecting an electrode of one of the light emitting cells with electrodes of other electrodes adjacent to the one of the light emitting cells.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: December 2, 2014
    Assignee: Seoul Viosys Co., Ltd.
    Inventor: Jae Ho Lee
  • Patent number: 8901598
    Abstract: A light emitting device (LED) includes a stress control layer having a compressive stress on a substrate, a bonding layer on the stress control layer, a semiconductor layer on the bonding layer and including an active region for emitting light on the bonding layer, a first electrode on a lower surface of the substrate, and a second electrode on the semiconductor layer. The compressive stress of the stress control layer is between about 1 and about 20 GPa.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: December 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-sik Hwang, Jun-youn Kim, Su-hee Chae
  • Patent number: 8901584
    Abstract: A light emitting diode including a compound semiconductor layer having at least a pn junction-type light emitting unit and a strain adjustment layer stacked on the light emitting unit, wherein the light emitting unit has a stacked structure containing a strained light emitting layer having a composition formula of (AlXGa1-X)YIn1-YP (wherein X and Y are numerical values that satisfy 0?X?0.1 and 0.39?Y?0.45 respectively) and a barrier layer, and the strain adjustment layer is transparent to the emission wavelength and has a lattice constant that is smaller than the lattice constants of the strained light emitting layer and the barrier layer. The light emitting diode has an emission wavelength of not less than 655 nm, exhibits excellent monochromaticity, high output and/or high efficiency, and has a fast response speed.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: December 2, 2014
    Assignee: Showa Denko K.K.
    Inventors: Noriyoshi Seo, Atsushi Matsumura, Ryouichi Takeuchi
  • Patent number: 8901612
    Abstract: Embodiments of a thin-film heterostructure thermoelectric material and methods of fabrication thereof are disclosed. In general, the thermoelectric material is formed in a Group IIa and IV-VI materials system. The thermoelectric material includes an epitaxial heterostructure and exhibits high heat pumping and figure-of-merit performance in terms of Seebeck coefficient, electrical conductivity, and thermal conductivity over broad temperature ranges through appropriate engineering and judicious optimization of the epitaxial heterostructure.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: December 2, 2014
    Assignees: Phononic Devices, Inc., The Board of Regents of the University of Oklahoma
    Inventors: Allen L. Gray, Robert Joseph Therrien, Patrick John McCann
  • Publication number: 20140346540
    Abstract: A light emitting diode (LED) die includes a first semiconductor layer, a second semiconductor layer, an active layer interposed between the first and second semiconductor layers, a transparent electrically conductive layer formed on the second semiconductor layer, and a passivation layer formed on the transparent electrically conductive layer. A first electrode is electrically connected with the first semiconductor layer, and a second electrode is is electrically connected with the second semiconductor layer. The transparent electrically conductive layer is made of tin doped indium oxide. The passivation layer is made of silicon nitride having a refractive index close to that of the transparent electrically conductive layer.
    Type: Application
    Filed: May 15, 2014
    Publication date: November 27, 2014
    Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: Tzu-Chien HUNG, Chia-Hui SHEN, Chien-Chung PENG
  • Patent number: 8895959
    Abstract: A superlattice layer including a plurality of periods, each of which is formed from a plurality of sub-layers is provided. Each sub-layer comprises a different composition than the adjacent sub-layer(s) and comprises a polarization that is opposite a polarization of the adjacent sub-layer(s). In this manner, the polarizations of the respective adjacent sub-layers compensate for one another. Furthermore, the superlattice layer can be configured to be at least partially transparent to radiation, such as ultraviolet radiation.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: November 25, 2014
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Remigijus Gaska, Jinwei Yang
  • Patent number: 8895955
    Abstract: Provided may be a display apparatus that uses oxide diodes having a nano rod structure, for example, nano-rod diodes formed of a ZnO group material. The display apparatus may include a substrate, a thin film transistor layer on the substrate, and a light emitting layer on the thin film transistor layer, wherein the light emitting layer may include a plug metal layer on the thin film transistor layer, a plurality of nano-rod diodes vertically formed on the plug metal layer, and a transparent electrode on the nano-rod diodes.
    Type: Grant
    Filed: October 6, 2008
    Date of Patent: November 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoungkook Kim, Youngsoo Park, Jaechul Park
  • Patent number: 8895958
    Abstract: Disclosed is a light emitting element, which emits light with small power consumption and high luminance. The light emitting element has: a IV semiconductor substrate; two or more core multi-shell nanowires disposed on the IV semiconductor substrate; a first electrode connected to the IV semiconductor substrate; and a second electrode, which covers the side surfaces of the core multi-shell nanowires, and which is connected to the side surfaces of the core multi-shell nanowires. Each of the core multi-shell nanowires has: a center nanowire composed of a first conductivity type III-V compound semiconductor; a first barrier layer composed of the first conductivity type III-V compound semiconductor; a quantum well layer composed of a III-V compound semiconductor; a second barrier layer composed of a second conductivity type III-V compound semiconductor; and a capping layer composed of a second conductivity type III-V compound semiconductor.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: November 25, 2014
    Assignees: National University Corporation Hokkaido University, Sharp Kabushiki Kaisha
    Inventors: Takashi Fukui, Katsuhiro Tomioka
  • Patent number: 8896002
    Abstract: A method for producing a semiconductor laser having an edge window structure includes the steps of forming masks of insulating films on a nitride-based III-V compound semiconductor substrate including first regions and second regions periodically arranged in parallel therebetween; and growing a nitride-based III-V compound semiconductor layer in a region not covered by the masks. The first region between each two adjacent second regions has two or more positions, symmetrical with respect to a center line thereof, where laser stripes are to be formed. The masks are formed on one or both sides of each of the positions where the laser stripes are to be formed at least near a position where edge window structures are to be formed such that the masks are symmetrical with respect to the center line. The nitride-based III-V compound semiconductor layer includes an active layer containing at least indium and gallium.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: November 25, 2014
    Assignee: Sony Corporation
    Inventors: Rintaro Koda, Masaru Kuramoto, Eiji Nakayama, Tsuyoshi Fujimoto
  • Publication number: 20140339581
    Abstract: A semiconductor light emitting device package is provided having a light transmissive substrate, and a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer sequentially laminated on the light transmissive substrate. The light emitting structure comprises a first surface and a second opposing surface facing the light transmissive substrate. The semiconductor light emitting device package comprises a via penetrating the second conductivity-type semiconductor layer and the active layer, and exposing the first conductivity-type semiconductor layer. A first electrode has a first portion disposed on the first surface, and a second portion extending into the via and contacting the first conductivity-type semiconductor layer. An insulating layer is disposed between the first electrode, and each of the second conductivity type semiconductor layer, the active layer, and the first surface.
    Type: Application
    Filed: May 9, 2014
    Publication date: November 20, 2014
    Inventors: Yong Min KWON, Hak Hwan KIM, Min Young SON, Sung Jun IM
  • Publication number: 20140339498
    Abstract: A radiation-emitting semiconductor chip includes a semiconductor body with a semiconductor layer sequence, wherein the semiconductor body with the semiconductor layer sequence extends in a vertical direction between a first major face and a second major face; the semiconductor layer sequence includes an active region that generates radiation, a first region of a first conduction type and a second region of a second conduction type differing from the first conduction type; the first region extends in a vertical direction between the first major face and the active region; the second region extends in a vertical direction between the second major face and the active region; at least one layer of the active region is based on an arsenide compound semiconductor material; and relative to its respective extent in the vertical direction, the first region or the second region is based in a proportion of at least half on a phosphide compound semiconductor material.
    Type: Application
    Filed: July 30, 2012
    Publication date: November 20, 2014
    Inventors: Martin R. Behringer, Christoph Klemp, Ivar Tångring, Peter Heidborn
  • Patent number: 8890177
    Abstract: An electronic or optoelectronic device fabricated from a crystalline material in which a parameter of a bandgap characteristic of said crystalline material has been modified locally by introducing distortions on an atomic scale in the lattice structure of said crystalline material and the electronic and/or optoelectronic parameters of said device are dependent on the modification of said bandgap is exemplified by a radiation emissive optoelectronic semiconductor device which comprises a junction (10) formed from a p-type layer (11) and an n-type layer (12), both formed from indirect bandgap semiconductor material. The p-type layer (11) contains a array of dislocation loops which create a strain field to confine spatially and promote radiative recombination of the charge carriers.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: November 18, 2014
    Assignee: University of Surrey
    Inventors: Kevin Peter Homewood, Russell Mark Gwilliam, Guosheng Shao
  • Patent number: 8890175
    Abstract: A nitride-based semiconductor element according to an embodiment of the present disclosure includes: a p-type contact layer, of which the growing plane is an m plane; and an electrode which is arranged on the growing plane of the p-type contact layer. The p-type contact layer is a GaN-based semiconductor layer which has a thickness of 26 nm to 60 nm and which includes oxygen at a concentration that is equal to or higher than Mg concentration of the p-type contact layer. In the p-type contact layer, the number of Ga vacancies is larger than the number of N vacancies.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 18, 2014
    Assignee: Panasonic Corporation
    Inventors: Toshiya Yokogawa, Naomi Anzue, Akira Inoue, Ryou Kato
  • Patent number: 8890212
    Abstract: According to example embodiments, a normally-off high electron mobility transistor (HEMT) includes: a channel layer having a first nitride semiconductor, a channel supply layer on the channel layer, a source electrode and a drain electrode at sides of the channel supply layer, a depletion-forming layer on the channel supply layer, a gate insulating layer on the depletion-forming layer, and a gate electrode on the gate insulation layer. The channel supply layer includes a second nitride semiconductor and is configured to induce a two-dimensional electron gas (2DEG) in the channel layer. The depletion-forming layer is configured has at least two thicknesses and is configured to form a depletion region in at least a partial region of the 2DEG. The gate electrode contacts the depletion-forming layer.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: November 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-chul Jeon, Young-hwan Park, Jae-joon Oh, Kyoung-yeon Kim, Joon-yong Kim, Ki-yeol Park, Jai-kwang Shin, Sun-kyu Hwang
  • Patent number: 8890184
    Abstract: A nanostructured light-emitting device including: a first type semiconductor layer; a plurality of nanostructures each including a first type semiconductor nano-core grown in a three-dimensional (3D) shape on the first type semiconductor layer, an active layer formed to surround a surface of the first type semiconductor nano-core, and a second type semiconductor layer formed to surround a surface of the active layer and including indium (In); and at least one flat structure layer including a flat-active layer and a flat-second type semiconductor layer that are sequentially formed on the first type semiconductor layer parallel to the first type semiconductor layer.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: November 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-sung Kim, Taek Kim, Moon-seung Yang
  • Patent number: 8890183
    Abstract: A light emitter includes a first mirror that is an epitaxially grown metal mirror, a second mirror, and an active region that is epitaxially grown such that the active region is positioned at or close to, at least, one antinode between the first mirror and the second mirror.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: November 18, 2014
    Assignee: Lightwave Photonics, Inc.
    Inventor: Robbie J. Jorgenson
  • Patent number: 8890196
    Abstract: A solid-state light source has light emitting diodes embedded in a thermally conductive translucent luminescent element. The thermally conductive translucent luminescent element has optically translucent thermal filler and at least one luminescent element in a matrix material. A leadframe is electrically connected to the light emitting diodes. The leadframe distributes heat from the light emitting diodes to the thermally conductive translucent luminescent element. The thermally conductive translucent luminescent element distributes heat from light emitting diodes and the thermally conductive translucent luminescent element.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 18, 2014
    Assignee: Goldeneye, Inc.
    Inventors: Scott M. Zimmerman, William R. Livesay, Richard L. Ross, Eduardo DeAnda
  • Publication number: 20140332820
    Abstract: A method of fabricating a light emitting diode device comprises depositing conductive material to cover a portion of surface of a conductive and reflective layer to form a first contact pad, and surfaces between adjacent first trenches to form a second contact pad; and depositing a first passivation layer over uncovered portion of surface of the conductive and reflective layer to form a first planar passivation contact surface between the first contact pad and the second trench and depositing bonding material to cover a portion of surface of the first contact pad, a portion of the second contact pad and a portion of the first planar passivation contact to form a first light emitting diode bonding pad on the first contact pad, a second light emitting diode bonding pad on the second contact pad, and a third light emitting diode bonding pad on the first planar passivation contact.
    Type: Application
    Filed: April 14, 2014
    Publication date: November 13, 2014
    Applicant: STARLITE LED INC
    Inventors: Chang Han, Pao Chen
  • Patent number: 8882935
    Abstract: A method for the fabrication of nonpolar indium gallium nitride (InGaN) films as well as nonpolar InGaN-containing device structures using metalorganic chemical vapor deposition (MOVCD). The method is used to fabricate nonpolar InGaN/GaN violet and near-ultraviolet light emitting diodes and laser diodes.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: November 11, 2014
    Assignees: The Regents of the University of California, The Japan Science and Technology Agency
    Inventors: Arpan Chakraborty, Benjamin A. Haskell, Stacia Keller, James S. Speck, Steven P. DenBaars, Shuji Nakamura, Umesh K. Mishra
  • Patent number: 8884268
    Abstract: The present disclosure is directed to an integrated circuit and its formation. In some embodiments, the integrated circuit includes a diffusion barrier layer. The diffusion barrier layer can be arranged to prevent diffusion of the Si and O2 from a Si substrate into a Group III nitride layer. The diffusion barrier layer can comprise Al2O3. In some embodiments, the integrated circuit further comprises a lattice-matching structure disposed between the silicon substrate and a Group III nitride layer.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Ming Chen, Han-Chin Chiu, Chung-Yi Yu, Chia-Shiung Tsai
  • Patent number: 8878345
    Abstract: A structural body includes a sapphire underlying substrate; and a semiconductor layer of a group III nitride semiconductor disposed on the underlying substrate. An upper surface of the underlying substrate is a crystal surface tilted at an angle of 0.5° or larger and 4° or smaller with respect to a normal line of an a-plane which is orthogonal to an m-plane and belongs to a {11-20} plane group, from the m-plane which belongs to a {1-100} plane group.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: November 4, 2014
    Assignee: AETech Corporation
    Inventors: Takafumi Yao, Hyun-Jae Lee, Katsushi Fujii
  • Patent number: 8878232
    Abstract: An MQW-structure light-emitting layer is formed by alternately stacking InGaN well layers and AlGaN barrier layers. Each well layer and each barrier layer are formed so as to satisfy the following relations: 12.9??2.8x+100y?37 and 0.65?y?0.86, or to satisfy the following relations: 162.9?7.1x+10z?216.1 and 3.1?z?9.2, here x represents the Al compositional ratio (mol %) of the barrier layer, and y represents the difference in bandgap energy (eV) between the barrier layer and the well layer, and z represents the In compositional ratio (mol %) of the well layer.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: November 4, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Ryo Nakamura
  • Patent number: 8878160
    Abstract: A device includes a semiconductor structure comprising a III-phosphide light emitting layer disposed between an n-type region and a p-type region. A transparent, conductive oxide is disposed in direct contact with the n-type region. In some embodiments, a total thickness of semiconductor material between the light emitting layer and the transparent, conductive oxide is less than one micron.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: November 4, 2014
    Assignee: Koninklijke Philips N.V.
    Inventors: Frédéric Georges Michel Dupont, John Edward Epler
  • Patent number: 8878209
    Abstract: A high efficiency Group III nitride light emitting diode is disclosed. The diode includes a Group III nitride-based light emitting region including a plurality of Group III nitride-based layers. A lenticular surface directly contacts one of the Group III nitride-based layers of the light emitting region. The lenticular surface includes a transparent material that is different from the Group III nitride-based layer of the light emitting region that the lenticular surface directly contacts.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: November 4, 2014
    Assignee: Cree, Inc.
    Inventors: John Adam Edmond, David B. Slater, Jr., Jayesh Bharathan, Matthew Donofrio
  • Publication number: 20140319557
    Abstract: A method for manufacturing a vertically structured Group III nitride semiconductor LED chip includes a first step of forming a light emitting structure laminate; a second step of forming a plurality of separate light emitting structures by partially removing the light emitting structure laminate to partially expose the growth substrate; a third step of forming a conductive support, which conductive support integrally supporting the light emitting structures; a fourth step of separating the growth substrate by removing the lift-off layer; and a fifth step of dividing the conductive support between the light emitting structures thereby singulating a plurality of LED chips each having the light emitting structure. A first through-hole is formed to open in a central region of each of the light emitting structures such that at least the lift-off layer is exposed, and an etchant is supplied from the first through-hole in the fourth step.
    Type: Application
    Filed: May 12, 2011
    Publication date: October 30, 2014
    Applicants: DOWA ELECTRONICS MATERIALS CO., LTD., WAVESQUARE INC.
    Inventors: Meoung Whan Cho, Seog Woo Lee, Pil Guk Jang, Ryuichi Toba, Yoshitaka Kadowaki
  • Publication number: 20140319558
    Abstract: This disclosure discloses a light-emitting device. The light-emitting device comprise a light-emitting stack having a first-type semiconductor layer, a second-type semiconductor layer, and an active formed between the first-type semiconductor layer and the second-type semiconductor layer and emitting a light; and a reflective structure formed on the first-type semiconductor layer and having a first interface and a second interface; wherein the critical angle of the light at the first interface is larger than that at the second interface; and wherein the reflective structure ohmically contacts the first-type semiconductor layer at the first interface.
    Type: Application
    Filed: April 24, 2014
    Publication date: October 30, 2014
    Applicant: EPISTAR CORPORATION
    Inventors: Yi-Ming CHEN, Hao-Min KU, Chih-Chiang LU, Tzu-Chieh HSU
  • Patent number: 8872157
    Abstract: A nitride semiconductor structure and a semiconductor light emitting device including the same are revealed. The nitride semiconductor structure includes a light emitting layer disposed between a n-type semiconductor layer and a p-type semiconductor layer, and a hole supply layer disposed between the light emitting layer and the p-type semiconductor layer. The hole supply layer is made from material InxGa1-xN (0<x<1) and is doped with a Group IV-A element at a concentration ranging from 1017 to 1020 cm?3. By being doped with the Group IV-A element, the concentration of holes is increased and inactivation caused by Mg—H bonds is reduced. Thus Mg is activated as acceptors and the light emitting efficiency is further increased.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: October 28, 2014
    Assignee: Genesis Photonics Inc.
    Inventors: Jyun-De Wu, Yu-Chu Li
  • Patent number: 8853728
    Abstract: An LED mounting substrate includes a base substrate, a conductive pattern formed on the base substrate and including a recessed portion on an upper surface thereof, and a light reflecting film formed in an inter-pattern gap of the conductive pattern on the base substrate and in the recessed portion of the conductive pattern.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: October 7, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Yosuke Tsuchiya, Shota Shimonishi, Hiroyuki Tajima, Akira Sengoku
  • Patent number: 8853672
    Abstract: A gallium nitride substrate includes a plurality of physical level differences in a surface thereof. All the physical level differences existing in the surface have a dimension of not more than 4 ?m. A relationship of (H?L)/H×100?80 is satisfied in all the physical level differences, where H represents a higher value of cathodoluminescence emission intensities of a wavelength corresponding to a bandgap of the gallium nitride substrate, and L represents a lower value of the cathodoluminescence emission intensities, the cathodoluminescence emission intensities being measured in an upper step and a lower step of the physical level difference.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: October 7, 2014
    Assignee: Hitachi Metals, Ltd.
    Inventor: Shunsuke Yamamoto
  • Patent number: 8853669
    Abstract: A method of fabricating a substrate for a semipolar III-nitride device, comprising patterning and forming one or more mesas on a surface of a semipolar III-nitride substrate or epilayer, thereby forming a patterned surface of the semipolar III-nitride substrate or epilayer including each of the mesas with a dimension l along a direction of a threading dislocation glide, wherein the threading dislocation glide results from a III-nitride layer deposited heteroepitaxially and coherently on a non-patterned surface of the substrate or epilayer.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: October 7, 2014
    Assignee: The Regents of the University of California
    Inventors: James S. Speck, Anurag Tyagi, Steven P. Denbaars, Shuji Nakamura
  • Publication number: 20140291644
    Abstract: An exemplary printable composition of a liquid or gel suspension of diodes comprises a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary diode comprises: a light emitting or absorbing region having a diameter between about 20 and 30 microns and a height between 2.5 to 7 microns; a plurality of first terminals spaced apart and coupled to the light emitting region peripherally on a first side, each first terminal of the plurality of first terminals having a height between about 0.5 to 2 microns; and one second terminal coupled centrally to a mesa region of the light emitting region on the first side, the second terminal having a height between 1 to 8 microns.
    Type: Application
    Filed: March 24, 2014
    Publication date: October 2, 2014
    Applicant: NthDegree Technologies Worldwide Inc.
    Inventors: Mark David Lowenthal, William Johnstone Ray, Neil O. Shotton, Richard A. Blanchard, Brad Oraw
  • Patent number: 8847204
    Abstract: This invention provides a germanium electroluminescence device and a fabricating method of the same for using germanium of an indirect bandgap semiconductor without modifying a bandgap as a light-emitting layer which emits a 1550 nm-wavelength light and enabling to use not only as infrared LEDs itself but also as light sources for optical communication systems.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: September 30, 2014
    Assignees: Seoul National University R&DB Foundation, The Board of Trustees of the Leland Standford Junior University
    Inventors: Byung-Gook Park, James S. Harris, Jr., Seongjae Cho
  • Patent number: 8847252
    Abstract: A III-nitride light emitting layer is disposed between an n-type region and a p-type region in a double heterostructure. At least a portion of the III-nitride light emitting layer has a graded composition.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: September 30, 2014
    Assignee: Philips Lumileds Lighting Company, LLC
    Inventors: Yu-Chen Shen, Nathan F. Gardner, Satoshi Watanabe, Michael R. Krames, Gerd O. Mueller
  • Patent number: 8847242
    Abstract: A light emitting diode device (e.g., LED package) may include at least two light emitting devices that can be switched independently of one another and thus may be useful in vehicular lighting applications, for example low and high beam headlights. A LED device may include a first LED die and at least one additional LED die disposed at different positions within a common reflector cup or relative to a common lens. Multiple LED sub-assemblies may be mounted to a common lead frame along non-coincident principal axes. Methods for varying intensity or color from multi-LED lamps are further provided.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: September 30, 2014
    Assignee: Cree, Inc.
    Inventor: Edward Lloyd Hutchins
  • Patent number: 8847206
    Abstract: Disclosed is a surface modifying agent including a compound having an ethynyl group at one terminal end, a laminated structure manufactured using the surface modifying agent, a method of manufacturing the laminated structure, and a transistor including the same.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: September 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-il Park, Byung-wook Yoo, Do-hwan Kim, Sang-yoon Lee, Bang-lin Lee, Eun-jeong Jeong
  • Publication number: 20140273323
    Abstract: Methods of manufacture of advanced heterojunction transistors and transistor lasers, and their related structures, are described herein. Other embodiments are also disclosed herein.
    Type: Application
    Filed: March 17, 2014
    Publication date: September 18, 2014
    Inventor: Mattew H. Kim
  • Patent number: 8835950
    Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Chie Hongo, Hajime Nago, Shinya Nunoue
  • Patent number: 8835901
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer, a light emitting part, and a multilayered structural body. The light emitting part is provided between the first and second semiconductor layers and includes barrier layers and well layers alternately stacked. The multilayered structural body is provided between the first semiconductor layer and the light emitting part and includes high energy layers and low energy layers alternately stacked. An average In composition ratio on a side of the second semiconductor is higher than that on a side of the first semiconductor in the multilayered structural body. An average In composition ratio on a side of the second semiconductor is higher than that on a side of the first semiconductor in the light emitting part.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Hajime Nago, Toshiki Hikosaka, Shigeya Kimura, Shinya Nunoue
  • Patent number: 8835904
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type layer, a p-type layer, and a light emitting unit provided between the n-type layer and the p-type layer and including barrier layers and well layers. At least one of the barrier layers includes first and second portion layers. The first portion layer is disposed on a side of the n-type layer. The second portion layer is disposed on a side of the p-type layer, and contains n-type impurity with a concentration higher than that in the first portion layer. At least one of the well layers includes third and fourth portion layers. The third portion layer is disposed on a side of the n-type layer. The fourth portion layer is disposed on a side of the p-type layer, and contains n-type impurity with a concentration higher than that in the third portion layer.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiki Hikosaka, Koichi Tachibana, Hajime Nago, Shinya Nunoue