More Than Two Heterojunctions In Same Device Patents (Class 257/97)
  • Patent number: 7531843
    Abstract: A structure of light-emitting diode (LED) dies having an AC loop (a structure of AC LED dies), which is formed with at least one unit of AC LED micro-dies disposed on a chip. The unit of AC LED micro-dies comprises two LED micro-dies arranged in mutually reverse orientations and connected with each other in parallel, to which an AC power supply may be applied so that the LED unit may continuously emit light in response to a positive-half wave voltage and a negative-half wave voltage in the AC power supply. Since each AC LED micro-die is operated forwardly, the structure of AC LED dies also provides protection from electrical static charge (ESD) and may operate under a high voltage.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: May 12, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Te Lin, Fei-Chang Hwang, Chia-Tai Kuo
  • Patent number: 7528417
    Abstract: A double hetero structure light-emitting diode device includes an active layer (6), a positive-electrode-side cladding layer, a negative-electrode-side cladding layer (4), a window layer (9) and an undoped AlInP layer. The positive-electrode-side cladding layer includes an undoped AlInP layer (7) grown to have a thickness of 0.5 ?m and an intermediate layer (8) doped to assume p-type conductivity and having an intermediate energy band gap value between that of the undoped AlInP layer and that of the window layer. The window layer on the intermediate layer is a GaP layer grown at 730° C. or higher and at a growth rate of 7.8 ?m/hour or more in the presence of Ze serving as a dopant. The negative-electrode-side cladding layer is provided with an undoped AlInP layer (5) having a thickness of 0.1 ?m or more.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: May 5, 2009
    Assignee: Showa Denko K.K.
    Inventors: Ryouichi Takeuchi, Keiichi Matsuzawa, Junichi Yamazaki
  • Patent number: 7529283
    Abstract: A nitride semiconductor light-emitting device includes a nitride semiconductor substrate of which at least part of a surface is formed from a nitride semiconductor and a nitride film semiconductor growth layer laid on the surface of the nitride semiconductor substrate. A carved region in the shape of a depressed portion may be formed on the surface of the nitride semiconductor substrate. The carved region may have an inverted tapered shape or a tapered shape in cross-section. Alternatively, or additionally, the nitride film semiconductor growth layer may include a gallium nitride film or an aluminum containing gallium nitride film where the nitride film semiconductor growth layer makes contact with the nitride semiconductor substrate. Alternatively, or additionally, the nitride film semiconductor growth layer may include a light-emitting portion formed at a location 20 ?m or more away from the carved region.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: May 5, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takeshi Kamikawa, Yoshika Kaneko
  • Publication number: 20090101927
    Abstract: A method of manufacturing a semiconductor light emitting device employs a substrate formed by successively stacking an n-type semiconductor layered portion including an AlGaN layer, a light emitting layer containing In and a p-type semiconductor layered portion on a group III nitride semiconductor substrate having a larger lattice constant than AlGaN. This method includes the steps of selectively etching the substrate from the side of the p-type semiconductor layered portion along a cutting line to expose the AlGaN layer along the cutting line, forming a division guide groove along the cutting line on the exposed AlGaN layer, and dividing the substrate along the division guide groove.
    Type: Application
    Filed: September 2, 2008
    Publication date: April 23, 2009
    Applicant: ROHM CO.,LTD.
    Inventor: Shinichi Kohda
  • Patent number: 7518204
    Abstract: A semiconductor device includes a semiconductor substrate formed of at least two kinds of group III elements and nitrogen, an active layer formed on the semiconductor substrate, and a nitride semiconductor layer formed on a surface of the semiconductor substrate and formed between the semiconductor substrate and the active layer. The nitride semiconductor layer is formed of the same constituent elements of the semiconductor substrate. A composition ratio of the lightest element among the group III elements of the nitride semiconductor layer is higher than a composition ratio of the corresponding element of the semiconductor substrate.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: April 14, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takashi Kano, Masayuki Hata, Yasuhiko Nomura
  • Publication number: 20090090923
    Abstract: A semiconductor light-emitting device and method for manufacturing the semiconductor light-emitting device includes a mask layer etching process on first and second mask layers provided on a Group-III nitride-based compound semiconductor substrate, the mask layer with a higher etching rate being closer to the p-type semiconductor layer; a semiconductor layer etching process; a side-etching process that selectively etches the side of the mask layer with the high etching rate to define a groove portion with a portion of the p-type semiconductor layer exposed; a ZrO2 film forming process that forms a ZrO2 film so as to cover the exposed p-type semiconductor layer; an Al2O3 film forming process that forms an Al2O3 film so as to cover the ZrO2 film; a mask layer removing process; and an electrode layer forming process.
    Type: Application
    Filed: December 5, 2008
    Publication date: April 9, 2009
    Applicant: ROHM CO., LTD.
    Inventor: Masahiro MURAYAMA
  • Patent number: 7514720
    Abstract: The invention relates to a monolithic white light emitting device using wafer bonding or metal bonding. In the invention, a conductive submount substrate is provided. A first light emitter is bonded onto the conductive submount substrate by a metal layer. In the first light emitter, a p-type nitride semiconductor layer, a first active layer, an n-type nitride semiconductor layer and a conductive substrate are stacked sequentially from bottom to top. In addition, a second light emitter is formed on a partial area of the conductive substrate. In the second light emitter, a p-type AlGaInP-based semiconductor layer, an active layer and an n-type AlGaInP-based semiconductor layer are stacked sequentially from bottom to top. Further, a p-electrode is formed on an underside of the conductive submount substrate and an n-electrode is formed on a top surface of the n-type AlGaInP-based semiconductor layer.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: April 7, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Min Ho Kim, Masayoshi Koike, Kyeong Ik Min, Myong Soo Cho
  • Publication number: 20090078947
    Abstract: An end face emission type semiconductor light emitting device which include: a substrate; a first conductive type clad layer stacked on the substrate; an active region layer including an active layer stacked on the first conductive type clad layer; a second conductive type clad layer stacked on the active region layer such that a thickness of a portion thereof at least over an emission region of the active region layer in an emission end face adjacent area is thinner than a thickness of the other portion; and a second conductive type regrowth layer stacked on the second conductive type clad layer, which has a higher refractive index than the second conductive type clad layer.
    Type: Application
    Filed: September 17, 2008
    Publication date: March 26, 2009
    Applicant: FUJIFILM Corporation
    Inventor: Tsuyoshi Ohgoh
  • Publication number: 20090072254
    Abstract: A light emitting device comprising a three-dimensional polarization-graded (3DPG) structure that improves lateral current spreading within the device without introducing additional dopant impurities in the epitaxial structures. The 3DPG structure can include a repeatable stack unit that may be repeated several times within the 3DPG. The stack unit includes a compositionally graded layer and a silicon (Si) delta-doped layer. The graded layer is compositionally graded over a distance from a first material to a second material, introducing a polarization-induced bulk charge into the structure. The Si delta-doped layer compensates for back-depletion of the electron gas at the interface of the graded layers and adjacent layers. The 3DPG facilitates lateral current spreading so that current is injected into the entire active region, increasing the number of radiative recombination events in the active region and improving the external quantum efficiency and the wall-plug efficiency of the device.
    Type: Application
    Filed: September 14, 2007
    Publication date: March 19, 2009
    Inventor: Arpan Chakraborty
  • Patent number: 7495261
    Abstract: A Group III nitride semiconductor light-emitting device includes a stacked structure 11 formed on a crystal substrate (100) to be removed from it and including two Group III nitride semiconductor layers 104 and 106 having different electric conductive types and a light-emitting layer 105 which is stacked between the two Group III nitride semiconductor layers and which includes a Group III nitride semiconductor, and a plate body 111made of material different from that of the crystal substrate and formed on a surface of an uppermost layer which is opposite from the crystal substrate that is removed from the stacked structure.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: February 24, 2009
    Assignee: Showa Denko K.K.
    Inventors: Katsuki Kusunoki, Kazuhiro Mitani, Takashi Udagawa
  • Patent number: 7482635
    Abstract: An object of the present invention is to provide a gallium nitride compound semiconductor multilayer structure useful for producing a gallium nitride compound semiconductor light-emitting device which operates at low voltage while maintaining satisfactory light emission output. The inventive gallium nitride compound semiconductor multilayer structure comprises a substrate, and an n-type layer, a light-emitting layer, and a p-type layer formed on the substrate, the light-emitting layer having a multiple quantum well structure in which a well layer and a barrier layer are alternately stacked repeatedly, said light-emitting layer being sandwiched by the n-type layer and the p-type layer, wherein the well layer comprises a thick portion and a thin portion, and the barrier layer contains a dopant.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: January 27, 2009
    Assignee: Showa Denko K.K.
    Inventors: Masato Kobayakawa, Hitoshi Takeda, Hisayuki Miki, Tetsuo Sakurai
  • Patent number: 7479661
    Abstract: The invention provides a nitride semiconductor device and a manufacturing method thereof. In the invention, n-type and p-type nitride semiconductor layers are formed on a substrate, and an active layer is formed therebetween. The n-type nitride semiconductor layers include first and second n-type GaN layers disposed in the order of distance from the active layer. In addition, in the nitride semiconductor device of the invention, an AlxGal-xN layer, where 0<x<1, is interposed between the first and second n-type GaN layers, thereby forming a two-dimensional electron gas layer at interfaces of the first and second n-type GaN layers.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: January 20, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jae Hoon Lee, Hee Seok Choi, Jeong Tak Oh, Su Yeol Lee
  • Publication number: 20090001394
    Abstract: The invention discloses a semiconductor structure combination for the epitaxy of a semiconductor optoelectronic device and manufacture thereof. The semiconductor structure combination according to the invention includes a substrate and a semiconductor material. The substrate has an upper surface and a recess formed on the upper surface. The sidewalls of the recess provide at least one first site for the growth of at least one first epitaxial crystal of the semiconductor material toward a first preferred orientation. A bottom of the recess provides a second site for the growth of a second epitaxial crystal of the semiconductor material toward the first preferred orientation. Flat regions adjacent to the recess provide at least one third site for the growth of at least one third epitaxial crystal of the semiconductor material toward the first preferred orientation.
    Type: Application
    Filed: December 3, 2007
    Publication date: January 1, 2009
    Inventors: Chih-Ching Cheng, Tzong-Liang Tsai
  • Patent number: 7470938
    Abstract: In a nitride semiconductor light emitting device having patterns formed on the upper and lower surfaces of a substrate from which light is emitted in a flip chip bonding structure, the patterns are capable of changing light inclination at the upper and lower surfaces of the substrate to decrease total reflection at the interfaces, thereby improving light emitting efficiency.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: December 30, 2008
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jae Hoon Lee, Jeong Wook Lee, Hyun Kyung Kim, Yong Chun Kim
  • Publication number: 20080315226
    Abstract: A light emitting diode structure including a substrate, a strain-reducing seed layer, an epitaxial layer, a first electrode and a second electrode is provided. The strain-reducing seed layer having a plurality of clusters is disposed on the substrate, and the material of the clusters is selected from a group consisting of aluminum nitride, magnesium nitride and indium nitride. The epitaxial layer includes a first type doped semiconductor layer, a light emitting layer and a second type doped semiconductor layer. The first electrode is disposed on the exposed first type doped semiconductor layer and electrically connected thereto. The second electrode is disposed on the second type doped semiconductor layer and electrically connected thereto.
    Type: Application
    Filed: May 9, 2008
    Publication date: December 25, 2008
    Applicant: NATIONAL CENTRAL UNIVERSITY
    Inventors: Cheng-Huang Kuo, Wei-Chih Lai, Chi-Wen Kuo
  • Patent number: 7462876
    Abstract: Disclosed herein is a nitride semiconductor light emitting device, which is improved in luminance and reliability. The light emitting device, comprises an n-type nitride semiconductor layer, an active layer and a p-type nitride semiconductor layer sequentially formed on a substrate, an n-side electrode formed on a portion of an upper surface of the n-type nitride semiconductor layer, and at least one intermediate layer formed between the substrate and the n-type nitride semiconductor layer. The intermediate layer has a multilayer structure of three or more layers having different band-gaps, and is positioned below the n-side electrode.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: December 9, 2008
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sang Heon Han, Bang Won Oh, Je Won Kim, Hyun Wook Shim, Joong Seo Kang, Dong Ju Lee
  • Patent number: 7456435
    Abstract: A light-emitting diode having a silicon substrate on which there are successively formed a buffer layer, a p-type nitride semiconductor layer, an active layer, an n-type nitride semiconductor layer, and a current spreading layer. The current spreading layer is a lamination of a first and a second sublayer arranged alternately a required number of times. Composed of different compound semiconductors, the alternating sublayers of the current spreading layer create heterojunctions for offering the two-dimensional gas effect. The current spreading layer is so low in resistivity in a direction parallel to its major surface from which light is emitted, that the current is favorably spread therein for improved efficiency of light emission. A front electrode in the form of a metal pad is mounted centrally on the major surface of the current spreading layer in ohmic contact therewith.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: November 25, 2008
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Hidekazu Aoyagi, Koji Otsuka, Masahiro Sato
  • Publication number: 20080283854
    Abstract: A light emitting diode device layer structure including a p-type contact layer that contains at least some indium (In), wherein the p-type contact layer is a not-intentionally doped strained nitride contact layer.
    Type: Application
    Filed: May 1, 2008
    Publication date: November 20, 2008
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Michael Iza, Hirokuni Asamizu, Christian G. Van de Walle, Steven P. DenBaars, Shuji Nakamura
  • Patent number: 7449723
    Abstract: A semiconductor device is disclosed in which a barrier layer is deposited on the sides of the mesa. The barrier layer may comprise a semiconductor material. The barrier layer reduces diffusion of dopants into the active region of the device.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: November 11, 2008
    Assignee: Avago Technologies Fiber IP (Singapore) Pte. Ltd.
    Inventors: John Stephen Massa, Simon Andrew Wood
  • Publication number: 20080265265
    Abstract: One embodiment of the present invention provides an InGaAlN-based semiconductor light-emitting device which comprises an InGaAlN-based semiconductor multilayer structure and a carbon-based substrate which supports InGaAlN-based semiconductor multilayer structure, wherein the carbon-based substrate comprises at least one carbon-based layer. This carbon-based substrate has both high thermal conductivity and low electrical resistivity.
    Type: Application
    Filed: July 16, 2007
    Publication date: October 30, 2008
    Applicant: LATTICE POWER (JIANGXI) CORPORATION
    Inventors: Chuanbing Xiong, Fengyi Jiang, Li Wang, Yingwen Tang, Changda Zheng, Junlin Liu, Weihua Liu, Guping Wang
  • Patent number: 7396697
    Abstract: A method for fabricating a semiconductor light-emitting element according to the present invention includes the steps of (A) providing a striped masking layer on a first Group III-V compound semiconductor, (B) selectively growing a second Group III-V compound semiconductor over the entire surface of the first Group III-V compound semiconductor except a portion covered with the masking layer, thereby forming a current confining layer that has a striped opening defined by the masking layer, (C) selectively removing the masking layer, and (D) growing a third Group III-V compound semiconductor to cover the surface of the first Group III-V compound semiconductor, which is exposed through the striped opening, and the surface of the current confining layer.
    Type: Grant
    Filed: April 6, 2004
    Date of Patent: July 8, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshiaki Hasegawa, Toshiya Yokogawa, Atsushi Yamada
  • Publication number: 20080157107
    Abstract: A light-emitting diode (LED) and a method for manufacturing the same are described. The light-emitting diode comprises: a conductive substrate including a first surface and a second surface opposite to the first surface; a metal bonding layer deposed on the first surface of the conductive substrate; a reflective metal layer deposed on the metal bonding layer; an N-type semiconductor layer deposed on the reflective metal layer; an active layer deposed on the N-type semiconductor layer; a P-type semiconductor layer deposed on the active layer; a window layer deposed on the P-type semiconductor layer, wherein a thickness of the window layer is substantially at least 50 ?m, and the window layer is composed of a transparent conductive material; and a P-type electrode deposed on the window layer.
    Type: Application
    Filed: January 25, 2007
    Publication date: July 3, 2008
    Applicant: EPITECH TECHNOLOGY CORPORATION
    Inventors: Shih-Chang SHEI, Schang-jing HON, Shih-Chen WEI, Juh-Yuh SU
  • Publication number: 20080142781
    Abstract: Provided is a nitride semiconductor light emitting device including: a first nitride semiconductor layer; an active layer formed above the first nitride semiconductor layer; and a delta doped second nitride semiconductor layer formed above the active layer. According to the present invention, the optical power of the nitride semiconductor light emitting device is enhanced, optical power down phenomenon is improved and reliability against ESD (electro static discharge) is enhanced.
    Type: Application
    Filed: December 5, 2005
    Publication date: June 19, 2008
    Applicant: LG INNOTEK CO., LTD.
    Inventor: Suk Hun Lee
  • Patent number: 7368757
    Abstract: A back electrode 6 is formed in the back of a Si single crystal substrate 2 of a compound semiconductor in which an n-type 3C-SiC single crystal buffer layer 3 having a thickness of 0.05-2 ?m, a carrier concentration of 1016-1021/cm3, a hexagonal InwGaxAl1-w-xN single crystal buffer layer 4 (0?w<1, 0?x<1, w+x<1) having a thickness of 0.01-0.5 ?m, and an n-type hexagonal InyGazAl1-y-zN single crystal layer 5 (0?y<1, 0<z?1, y+z?1) having a thickness of 0.1-5 ?m and a carrier concentration of 1011-1016/cm3 are stacked in order on an n-type Si single crystal substrate top 2 having a crystal-plane orientation {111}, a carrier concentration of 1016-1021/cm3, and a surface electrode 7 is formed on a surface of a hexagonal InyGazAl1-y-zN single crystal layer 5, so as to provide a compound semiconductor device which causes little energy loss and allows an high efficiency and a high breakdown voltage.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: May 6, 2008
    Assignee: Covalent Materials Corporation
    Inventors: Jun Komiyama, Yoshihisa Abe, Shunichi Suzuki, Hideo Nakanishi
  • Patent number: 7365369
    Abstract: A nitride semiconductor device used chiefly as an LD and an LED element. In order to improve the output and to decrease Vf, the device is given either a three-layer structure in which a nitride semiconductor layer doped with n-type impurities serving as an n-type contact layer where an n-electrode is formed is sandwiched between undoped nitride semiconductor layers; or a superlattice structure of nitride. The n-type contact layer has a carrier concentration exceeding 3×1010 cm3, and the resistivity can be lowered below 8×10?3?cm.
    Type: Grant
    Filed: July 27, 1998
    Date of Patent: April 29, 2008
    Assignee: Nichia Corporation
    Inventors: Shuji Nakamura, Takashi Mukai, Koji Tanizawa, Tomotsugu Mitani, Hiroshi Marui
  • Patent number: 7358538
    Abstract: The present invention provides layered hole injection structures including one or more layers of fullerenes for application in an organic electroluminescent device. The layered structures include a bi-layered structure including an electrically conductive layer serving as electrical contact to external circuit and a fullerene layer sandwiched between the conductive layer and a hole transport layer. The layered structure may also includes a tri-layered structure stacked sequentially including a first electrically conductive layer, a fullerene layer and a hole injection layer material selected from thermally stable molecules such as CuPc. The layered structure may also include a four-layered structure stacked sequentially including a first electrically conductive layer, a fullerene layer on the conductive layer, a noble metal layer on the fullerene layer and another fullerene layer on the noble metal layer.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: April 15, 2008
    Inventors: Zheng-Hong Lu, Sijian Han, Yanyan Yuan
  • Patent number: 7351661
    Abstract: A semiconductor device having a trench isolation layer in a semiconductor substrate is provided, wherein the trench isolation layer includes a silicon nitride liner, a silicon oxide liner; and a buried layer, wherein the buried layer includes a first buried layer for filling a lower part of the trench isolation layer and a second buried layer for filling an upper part of the trench isolation layer. A semiconductor device preferably further includes a silicon oxide layer disposed between the semiconductor substrate and the silicon nitride liner. The silicon oxide layer includes a thermal oxide layer densified at a temperature over about 800° C.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: April 1, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Hwa Heo, Soo-Jin Hong
  • Patent number: 7352009
    Abstract: There is provided a light emitting nitride semiconductor device including a substrate, a semiconductor layer of a first conductivity overlying the substrate, a light emitting layer overlying the semiconductor layer of the first conductivity, a semiconductor layer of a second conductivity overlying the light emitting layer, and a second electrode overlying at least the semiconductor layer of the second conductivity, wherein the second electrode has a high reflectance for a main light emission wavelength and the light emitting device allows light to be extracted mainly at a side surface thereof.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: April 1, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Mayuko Fudeta
  • Publication number: 20080073660
    Abstract: A semiconductor laser device comprises an n-type cladding layer, a p-type cladding layer, and an active layer which is sandwiched between the n-type cladding layer and the p-type cladding layer. The p-type cladding layer contains magnesium as a dopant impurity. Further, an n-type diffusion blocking layer of a nitride compound semiconductor material located between the active layer and the p-type cladding layer and is InxAlyGa1?x?yN, where x?0, y?0, and (x+y)<1. The n-type diffusion blocking layer preferably has a concentration of a dopant impurity producing n-type conductivity in a range from 5×1017 cm?3 to 5×1019 cm?3.
    Type: Application
    Filed: September 13, 2007
    Publication date: March 27, 2008
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Akihito Ohno, Masayoshi Takemi, Nobuyuki Tomita
  • Patent number: 7348602
    Abstract: The present invention provides a nitride semiconductor light emitting device with an active layer of the multiple quantum well structure, in which the device has an improved luminous intensity and a good electrostatic withstanding voltage, thereby allowing the expanded application to various products. The active layer 7 is formed of a multiple quantum well structure containing InaGa1?aN (0?a<1). The p-cladding layer 8 is formed on said active layer containing the p-type impurity. The p-cladding layer 8 is mode of a multi-film layer including a first nitride semiconductor film containing Al and a second nitride semiconductor film having a composition different from that of said first nitride semiconductor film. Alternatively, the p-cladding layer 8 is made of single-layered layer made of AlbGa1?bN (0?b?1). A low-doped layer 9 is grown on the p-cladding layer 8 having a p-type impurity concentration lower than that of the p-cladding layer 8.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: March 25, 2008
    Assignee: Nichia Corporation
    Inventor: Koji Tanizawa
  • Patent number: 7323722
    Abstract: In a semiconductor optical device, a first conductive type semiconductor region is provided on a surface of GaAs. The first conductive type semiconductor region has a first region and a second region. An active layer is provided on the first region of the first conductive type semiconductor region. The active layer has a pair of side surfaces. A second conductive type semiconductor region is provided on the sides and top of the active layer, and the second region of the first conductive type semiconductor region. The bandgap energy of the first conductive type semiconductor region is greater than that of the active layer. The bandgap energy of the second conductive type semiconductor region is greater than that of the active layer. The second region of the first conductive type semiconductor region and the second conductive type semiconductor region constitute a pn junction.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: January 29, 2008
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Jun-ichi Hashimoto, Tsukuru Katsuyama
  • Patent number: 7323721
    Abstract: A monolithic, multi-color semiconductor light emitting diode (LED) is formed with a multi-bandgap, multi-quantum well (MQW) active light emitting region which emits light at spaced-apart wavelength bands or regions ranging from UV to red. The MQW active light emitting region comprises a MQW layer stack including n quantum barriers which space apart n?1 quantum wells. Embodiments include those wherein the MQW layer stack includes quantum wells of at least two different bandgaps for emitting light of two different wavelengths, e.g., in the blue or green regions and in at least one other region, and the intensities of the emissions are adjusted to provide a preselected color of combined light emission, preferably white light.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: January 29, 2008
    Assignee: Blue Photonics Inc.
    Inventors: Shirong Liao, Jinlin Ye, Theeradetch Detchprohm, Jyh-Chia Chen, Yea-Chuan Milton Yeh
  • Patent number: 7315048
    Abstract: In one embodiment, light emitted by a plurality of solid-state light emitters is mixed by mounting the plurality of solid-state light emitters on a transparent to translucent substrate so that they primarily emit light away from the substrate. The light emitters are then covered with a transparent to translucent encapsulant; and the encapsulant is coated with a reflective material that reflects light emitted by the light emitters toward the substrate. Related apparatus is also disclosed.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: January 1, 2008
    Assignee: Avago Technologies ECBU IP (Singapore) PTE Ltd
    Inventors: Elizabeth Ching Ling Fung, Thye Linn Mok, Hong Huat Yeoh, Yew Cheong Kuan, Fakhrul Arifin Mohd Afif, Norfidathul Aizar Abdul Karim, Kian Shin Lee, Hui Peng Koay
  • Patent number: 7312474
    Abstract: A light emitting diode is provided having a Group III nitride based superlattice and a Group III nitride based active region on the superlattice. The active region has at least one quantum well structure. The quantum well structure includes a first Group III nitride based barrier layer, a Group III nitride based quantum well layer on the first barrier layer and a second Group III nitride based barrier layer. A Group III nitride based semiconductor device and methods of fabricating a Group III nitride based semiconductor device having an active region comprising at least one quantum well structure are provided. The quantum well structure includes a well support layer comprising a Group III nitride, a quantum well layer comprising a Group III nitride on the well support layer and a cap layer comprising a Group III nitride on the quantum well layer.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: December 25, 2007
    Assignee: Cree, Inc.
    Inventors: David Todd Emerson, James Ibbetson, Michael John Bergmann, Kathleen Marie Doverspike, Michael John O'Loughlin, Howard Dean Nordby, Jr., Amber Christine Abare
  • Patent number: 7306964
    Abstract: The present invention relates to a method of manufacturing a vertically-structured GaN-based light emitting diode. The method of manufacturing a vertically-structured GaN-based light emitting diode includes forming a GaN layer on a substrate; patterning the compound layer in a predetermined shape; forming an n-type GaN layer on the patterned compound layer through the epitaxial lateral over-growth process and sequentially forming an active layer and a p-type GaN layer on the n-type GaN layer; forming a structure supporting layer on the p-type GaN layer; sequentially removing the substrate and the GaN layer formed on the substrate after forming the structure supporting layer; removing the patterned compound layer exposed after removing the GaN layer so as to form an n-type GaN layer patterned in a concave shape; and forming an n-type electrode on the n-type GaN layer patterned in a concave shape.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: December 11, 2007
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jae Hoon Lee, Hee Seok Choi, Jeong Tak Oh, Su Yeol Lee
  • Publication number: 20070272936
    Abstract: A nitride based light emitting device is disclosed. More particularly, a nitride based light emitting device capable of improving light emitting efficiency and reliability thereof is disclosed. The nitride based light emitting device includes a first conductive semiconductor layer connected to a first electrode, a second conductive semiconductor layer connected to a second electrode, an active layer located between the first conductive semiconductor layer and the second conductive semiconductor layer and having a quantum well structure, a first insertion layer located in at least one of a boundary between the first conductive semiconductor layer and the active layer and a boundary between the second conductive semiconductor layer and the active layer, and a second insertion layer located adjacent to the first insertion.
    Type: Application
    Filed: February 6, 2007
    Publication date: November 29, 2007
    Applicants: LG ELECTRONICS INC., LG INNOTEK CO., LTD
    Inventor: Johng Eon Shin
  • Patent number: 7297989
    Abstract: Disclosed are a diboride single crystal substrate which has a cleavage plane as same as that of a nitride compound semiconductor and is electrically conductive; a semiconductor laser diode and a semiconductor device using such a substrate and methods of their manufacture wherein the substrate is a single crystal substrate 1 of diboride XB2 (where X is either Zr or Ti) which is facially oriented in a (0001) plane 2 and has a thickness of 0.1 mm or less. The substrate 1 is permitted cleaving and splitting along a (10-10) plane 4 with ease. Using this substrate to form a semiconductor laser diode of a nitride compound, a vertical structure device can be realized. Resonant planes of a semiconductor laser diode with a minimum of loss can be fabricated by splitting the device in a direction parallel to the (10-10) plane. A method of manufacture that eliminates a margin of cutting is also realized.
    Type: Grant
    Filed: August 21, 2003
    Date of Patent: November 20, 2007
    Assignees: National Institute for Materials Science, Kyocera Corporation
    Inventors: Shigeki Otani, Hiroyuki Kinoshita, Hiroyuki Matsunami, Jun Suda, Hiroshi Amano, Isamu Akasaki, Satoshi Kamiyama
  • Patent number: 7294200
    Abstract: A method for producing a nitride semiconductor crystal comprising steps (a), (b) and (c), which steps follow in sequence as follows: a step (a) for forming fine crystal particles made of a nitride semiconductor on a substrate; a step (b) for forming a nitride semiconductor island structure having a plurality of facets inclined relative to a surface of the substrate using the fine crystal particles as nuclei; and a step (c) for causing the nitride semiconductor island structure to grow in a direction parallel with a surface of the substrate to merge a plurality of the nitride semiconductor island structures with each other, thereby forming a nitride semiconductor crystal layer having a flat surface; the steps (a)-(c) being continuously conducted in the same growing apparatus.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: November 13, 2007
    Assignee: Hitachi Cable, Ltd.
    Inventors: Hajime Fujikura, Kazuyuki Iizuka
  • Patent number: 7288783
    Abstract: Quantum dots are formed on a plurality of surfaces whose normal direction are different from each other. The quantum dots are formed on the surfaces normal to each other, whereby the polarization dependency can be eliminated as described above. Thus, the optical semiconductor device can have very low polarization dependency.
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: October 30, 2007
    Assignee: Fujitsu Limited
    Inventor: Tomoyuki Akiyama
  • Patent number: 7279717
    Abstract: A light emitting device includes an active layer, having a multiple quantum well structure, sandwiched between an n-type semiconductor layer and a p-type semiconductor layer. The active layer includes first and second well layers made of a nitride compound semiconductor containing In, where the second well layer emits light having a main peak wavelength which is longer than that of the first well layer. The active layer also includes an intervening barrier layer disposed between the first and second well layers, and first and second barrier layers. The first well layer isg sandwiched between the first barrier layer and the intervening barrier layer, and the second well layer is sandwiched between the second barrier layer and the intervening barrier layer. A thickness of said first barrier layer is different than a thickness of said second barrier layer.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: October 9, 2007
    Assignee: Nichia Corporation
    Inventor: Motokazu Yamada
  • Patent number: 7276742
    Abstract: A compound semiconductor light emitting device for preparing a chip which improves the light extraction efficiency, enables mounting of easy positioning with only once wire bonding, and leads to a reduction in the manhour. One face of an insulative substrate (11) is overlaid with a semiconductor layer (4) consisting of a plurality of semiconductor thin films to form an active layer (15). One electrode (33) is formed on the top face of this semiconductor layer (4), and the other electrode (33) on the other face of the insulative substrate (11). For the exposure of a first semiconductor thin film layer (13) connected to the other electrode (33), the semiconductor film over the first semiconductor thin film layer (13) is removed to form an exposure region (10). This exposure region (10) is provided with a through hole (2) penetrating through the insulative substrate (11) and first semiconductor thin film layer (13).
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: October 2, 2007
    Assignees: Sanyo Electric Co., Ltd., Tottori Sanyo Electric Co., Ltd.
    Inventors: Keishi Kohno, Katsumi Yagi
  • Patent number: 7274040
    Abstract: A light emitting device includes a substrate, a doped substrate layer, a layer of first conductivity type overlying the doped substrate layer, a light emitting layer overlying the layer of first conductivity type, and a layer of second conductivity type overlying the light emitting layer. A conductive transparent layer, e.g., of indium tin oxide, and a reflective metal layer overlie the layer of second conductivity type and provide electrical contact with the layer of second conductivity type. A plurality of vias may be formed in the reflective metal and conductive transparent layer as well as the layer of second conductivity type, down to the doped substrate layer. A plurality of contacts are formed in the vias and are in electrical contact with the doped substrate layer. An insulating layer formed over the reflective metal layer insulates the plurality of contacts from the conductive transparent layer and reflective metal layer.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: September 25, 2007
    Assignee: Philips Lumileds Lighting Company, LLC
    Inventor: Decai Sun
  • Patent number: 7271424
    Abstract: A light-emitting diode has a sub-mount, a first conductivity type substrate deposed on the sub-mount, a reflector layer deposed between the sub-mount and the first conductivity type substrate, a first conductivity type buffer layer deposed on the first conductivity type substrate, a first conductivity type distributed Bragg reflector (DBR) layer deposed on the first conductivity type buffer layer, an illuminant epitaxial structure deposed on the first conductivity type distributed Bragg reflector layer, and a second conductivity type window layer deposed on the illuminant epitaxial structure.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: September 18, 2007
    Assignees: Epitech Technology Corporation
    Inventor: Shi-Ming Chen
  • Patent number: 7259406
    Abstract: A semiconductor optical element having a includes an n-type GaAs buffer layer, an n-type AlGaInP cladding layer, a first InGaAsP (including zero As content)guide layer without added dopant impurities, an InGaAsP (including zero In content) active layer, a second InGaAsP (including zero As content)guide layer without added dopant impurities, a p-type AlGaInP cladding layer, a p-type band discontinuity reduction layer, and a p-type GaAs contact layer sequentially laminated on an n-type GaAs substrate C or Mg is the dopant impurity in the p-type GaAs contact layer, the p-type band discontinuity reduction layer, and the p-type AlGaInP cladding layer.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: August 21, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshihiko Hanamaki, Kenichi Ono, Kimio Shigihara, Kazushige Kawasaki, Kimitaka Shibata, Naoyuki Shimada
  • Patent number: 7244972
    Abstract: In a field effect transistor, an Si layer 11, an SiC (Si1?yCy) channel layer 12, a CN gate insulating film 13 made of a carbon nitride layer (CN) and a gate electrode 14 are deposited in this order on an Si substrate 10. The thickness of the SiC channel layer 12 is set to a value that is less than or equal to the critical thickness so that a dislocation due to a strain does not occur according to the carbon content. A source region 15 and a drain region 16 are formed on opposite sides of the SiC channel layer 12, and a source electrode 17 and a drain electrode 18 are provided on the source region 15 and the drain region 16, respectively.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: July 17, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Minoru Kubo, Yo Ichikawa, Akira Asai, Takahiro Kawashima
  • Patent number: 7224001
    Abstract: A semiconductor light source for illuminating a physical space has been invented. In various embodiments of the invention, a semiconductor such as and LED chip, laser chip, LED chip array, laser array, an array of chips, or a VCSEL chip is mounted on a heat sink. The heat sink may have multiple panels for mounting chips in various orientations. The chips may be mounted directly to a primary heat sink which is in turn mounted to a multi-panel secondary heat sink. A TE cooler and air circulation may be provided to enhance heat dissipation. An AC/DC converter may be included in the light source fitting.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: May 29, 2007
    Inventor: Densen Cao
  • Patent number: 7211836
    Abstract: A high emission intensity group-III nitride semiconductor light-emitting device obtained by eliminating crystal lattice mismatch with substrate crystal and using a gallium nitride phosphide-based light emitting structure having excellent crystallinity. A gallium nitride phosphide-based multilayer light-emitting structure is formed on a substrate via a boron-phosphide (BP)-based buffer layer. The boron phosphide-based buffer layer is preferably grown at a low temperature and rendered amorphous so as to eliminate the lattice mismatch with the substrate crystal. After the amorphous buffer layer is formed, it is gradually converted into a crystalline layer to fabricate a light-emitting device while keeping the lattice match with the gallium nitride phosphide-based light-emitting part.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: May 1, 2007
    Assignee: Showa Denko Kabushiki Kaisha
    Inventor: Takashi Udagawa
  • Patent number: 7208770
    Abstract: In photonic integrated circuits (PICs) having at least one active semiconductor device, such as, a buried heterostructure semiconductor laser, LED, modulator, photodiode, heterojunction bipolar transistor, field effect transistor or other active device, a plurality of semiconductor layers are formed on a substrate with one of the layers being an active region. A current channel is formed through this active region defined by current blocking layers formed on adjacent sides of a designated active region channel where the blocking layers substantially confine the current through the channel. The blocking layers are characterized by being an aluminum-containing Group III-V compound, i.e., an Al-III-V layer, intentionally doped with oxygen from an oxide source. Also, wet oxide process or a deposited oxide source may be used to laterally form a native oxide of the Al-III-V layer.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: April 24, 2007
    Assignee: Infinera Corporation
    Inventors: Fred A. Kish, Jr., Sheila Hurtt, Charles H. Joyner, Richard P. Schneider
  • Patent number: 7208338
    Abstract: A method of manufacturing a ridge type semiconductor light emitting device includes: a process of epitaxially growing a multi-layered semiconductor layer having at least a first conductive type cladding layer, an active layer, a second conductive type first cladding layer, an etching stop layer, and a second conductive type second cladding layer on a substrate; a process of forming a ridge groove for forming a ridge; and a process of forming a current-flow barrier layer in the ridge groove. The process of forming ridge grooves has first and second anisotropic etching processes of performing anisotropic etching, an etching-mask forming process, and an isotropic etching process of performing anisotropic etching.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: April 24, 2007
    Assignee: Sony Corporation
    Inventors: Mari Chiba, Hisashi Kudo, Shinichi Agatsuma
  • Patent number: 7208752
    Abstract: A structure of a gallium nitride light emitting diode has a transparent conductive window layer including a diffusion barrier layer, an ohmic contact layer, and a window layer. By using the added domain contact layer, the diffusion barrier layer and the P-type semiconductor layer of the light emitting diode are put into ohmic contact. And then, the rising of the contact resistivity is barred by applying the diffusion barrier layer to block the diffusion of the window layer from the contact with the domain contact layer so as to lower down the operating voltage and advance the transparency.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: April 24, 2007
    Assignee: Supernova Optoelectronics Corporation
    Inventors: Mu-Jen Lai, Schang-Jing Hon, Hsueh-Feng Sun, Shih-Ming Yang