Made By Depositing Layers, E.g., Alternatingly Conductive And Insulating Layers (epo) Patents (Class 257/E21.019)
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Patent number: 9299604Abstract: A semiconductor device according to an embodiment of the present invention includes fuse patterns spaced apart from each other by a predetermined distance over a first interlayer insulation film; a second interlayer insulation film disposed between the fuse patterns over the first interlayer insulation film; and a capping film pattern formed over the fuse patterns and the second interlayer insulation films, the capping film pattern including a slot exposing the second interlayer insulation film.Type: GrantFiled: August 12, 2014Date of Patent: March 29, 2016Assignee: SK HYNIX INC.Inventors: Jeong Youl Kim, Ki Soo Choi
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Patent number: 9275834Abstract: A method of removing titanium nitride is described. The silicon nitride resides on a patterned substrate. The titanium nitride is removed with a gas-phase etch using plasma effluents formed in a remote plasma from a fluorine-containing precursor, a nitrogen-and-hydrogen-containing precursor and an oxygen-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents react with the titanium nitride.Type: GrantFiled: February 20, 2015Date of Patent: March 1, 2016Assignee: Applied Materials, Inc.Inventors: Seung Park, Mikhail Korolik, Anchuan Wang, Nitin K. Ingle
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Patent number: 9269720Abstract: A method of fabricating a semiconductor device includes providing a substrate having a cell region and a peripheral circuit region. A plurality of bit line structures are formed on the substrate in the cell region, and a gate structure having the same structure as each of the bit line structures is formed on the substrate in the peripheral circuit region. A spacer is formed on sidewalls of the bit line structures and the gate structure. The bit line structures extend in a first direction and are spaced apart from each other in a second direction that is perpendicular to the first direction by first grooves that extend in the first direction. A sacrificial layer is formed to fill the first grooves and to cover top surfaces of the bit line structures and the gate structure. The sacrificial layer is planarized until the top surfaces of the bit line structures and the gate structure are exposed.Type: GrantFiled: June 3, 2015Date of Patent: February 23, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-woo Bae, Byoung-ho Kwon, Jong-hyuk Park, Hye-sung Park, Jun-seok Lee, Ki-vin Im, Hee-sook Cheon, In-seak Hwang
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Patent number: 8951901Abstract: In sophisticated semiconductor devices, the encapsulation of sensitive gate materials, such as a high-k dielectric material and a metal-containing electrode material, which are provided in an early manufacturing stage may be achieved by forming an undercut gate configuration. To this end, a wet chemical etch sequence is applied after the basic patterning of the gate layer stack, wherein at least ozone-based and hydrofluoric acid-based process steps are performed in an alternating manner, thereby achieving a substantially self-limiting removal behavior.Type: GrantFiled: July 22, 2011Date of Patent: February 10, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Sven Beyer, Berthold Reimer, Falk Graetsch
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Patent number: 8952436Abstract: A DRAM memory device includes at least one memory cell including a transistor having a first electrode, a second electrode and a control electrode. A capacitor is coupled to the first electrode. At least one electrically conductive line is coupled to the second electrode and at least one second electrically conductive line is coupled to the control electrode. The electrically conductive lines are located between the transistor and the capacitor. The capacitor can be provided above a fifth metal level.Type: GrantFiled: January 20, 2011Date of Patent: February 10, 2015Assignee: STMicroelectronics (Crolles 2) SASInventors: Sébastien Cremer, Frédérìc Lalanne, Marc Vernet
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Patent number: 8932933Abstract: A method of forming a hydrophobic surface on a semiconductor device structure. The method comprises forming at least one structure having at least one exposed surface comprising titanium atoms. The at least one exposed surface of at least one structure is contacted with at least one of an organo-phosphonic acid and an organo-phosphoric acid to form a material having a hydrophobic surface on the at least one exposed surface of the least one structure. A method of forming a semiconductor device structure and a semiconductor device structure are also described.Type: GrantFiled: May 4, 2012Date of Patent: January 13, 2015Assignee: Micron Technology, Inc.Inventors: Ian C. Laboriante, Prashant Raghu
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Patent number: 8912629Abstract: A semiconductor device includes a substrate and a plurality of storage nodes on the substrate and extending in a vertical direction relative to the substrate. A lower support pattern is in contact with the storage nodes between a bottom and a top of the storage nodes, the lower support pattern spaced apart from the substrate in the vertical direction, and the lower support pattern having a first maximum thickness in the vertical direction. An upper support pattern is in contact with the storage nodes above the lower support pattern relative to the substrate, the upper support pattern spaced apart from the lower support pattern in the vertical direction, and the lower support pattern having a second maximum thickness in the vertical direction that is greater than the first maximum thickness of the lower support pattern.Type: GrantFiled: March 8, 2012Date of Patent: December 16, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: JungWoo Seo
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Patent number: 8896236Abstract: An organic light emitting diode (OLED) display is provided. The OLED display includes: a substrate; an organic light emitting element including a first electrode on the substrate, an organic emission layer on the first electrode, and a second electrode on the organic emission layer; and an encapsulation member encapsulating the organic light emitting element and including a first conductive layer on the organic light emitting element and electrically connected to the second electrode, an insulation layer on the first conductive layer, and a second conductive layer on the insulation layer and configured to electrically connect to the first electrode.Type: GrantFiled: May 22, 2012Date of Patent: November 25, 2014Assignee: Samsung Display Co., Ltd.Inventors: Hae-Goo Jung, Do-Hyung Ryu, Kuen-Dong Ha
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Patent number: 8884350Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.Type: GrantFiled: January 23, 2013Date of Patent: November 11, 2014Assignee: PS4 Luxco S.A.R.L.Inventor: Toshiyuki Hirota
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Patent number: 8871615Abstract: According to one embodiment, a method includes forming a first SiGe layer having a first profile of a concentration of Ge on a semiconductor substrate, forming a second SiGe layer having a second profile of a concentration of Ge on the first SiGe layer, the second profile lower than a first peak of the first profile, forming a mask layer on the second SiGe layer, etching the first and second SiGe layers by anisotropic etching using the mask layer as a mask to form trenches, selectively removing the first SiGe layer exposed into the trenches to form a cavity under the second SiGe layer, and oxidizing side and lower surfaces of the second SiGe layer exposed in the trenches and the cavity to increase the concentration of Ge in the second SiGe layer.Type: GrantFiled: September 9, 2013Date of Patent: October 28, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Shinji Mori
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Patent number: 8871604Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a capacitor within a trench in a workpiece, the capacitor comprising a bottom electrode, a dielectric layer disposed over the bottom electrode, and a top electrode disposed over the dielectric layer. A cap layer is formed over the capacitor. Forming the capacitor and forming the cap layer comprise optimizing at least one of: a width of the trench, a thickness of the bottom electrode, a thickness of the dielectric layer, a thickness of the top electrode, and a thickness of the cap layer, so that the cap layer completely covers the top electrode.Type: GrantFiled: January 31, 2012Date of Patent: October 28, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Kuo-Chi Tu
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Patent number: 8802532Abstract: Disclosed are example bipolar transistors capable of reducing the area of a collector, reducing the distance between a base and a collector, and/or reducing the number of ion implantation processes. A bipolar transistor may includes a trench formed by etching a portion of a semiconductor substrate. A first collector may be formed on the inner wall of the trench. A second collector may be formed inside the semiconductor substrate in the inner wall of the trench. A first isolation film may be formed on the sidewall of the first collector. An intrinsic base may be connected to the third collector. An extrinsic base may be formed on the intrinsic base and inside the first isolation film. A second isolation film may be formed on the inner wall of the extrinsic base. An emitter may be formed by burying a conductive material inside the second isolation film.Type: GrantFiled: July 6, 2012Date of Patent: August 12, 2014Assignee: Dongbu HiTek Co., Ltd.Inventor: Nam Joo Kim
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Patent number: 8785906Abstract: An area illumination inorganic electro-luminescent device including a substrate; and an array of one or more commonly addressed, light-emitting elements. Each commonly-addressed, light-emitting element includes a first electrode layer formed over the substrate, one or more light-emitting layers formed over the first electrode layer and a second electrode layer formed over the light-emitting layer. The light-emitting layers include multiple core/shell quantum dot emitters formed in a common polycrystalline semiconductor matrix, and a number of different core/shell quantum dot emitters emit light with a spectral power distribution having a peak and a FWHM bandwidth, such that the peak wavelengths differ by an amount less than or equal to the average FWHM bandwidth of the different core/shell quantum dot emitters within the range of 460 to 670 nm.Type: GrantFiled: May 30, 2007Date of Patent: July 22, 2014Assignee: Eastman Kodak CompanyInventors: Michael E. Miller, Paul J. Kane, Ronald S. Cok
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Patent number: 8786001Abstract: A method for forming double-sided capacitors for a semiconductor device includes forming a dielectric structure which supports capacitor bottom plates during wafer processing. The structure is particularly useful for supporting the bottom plates during removal of a base dielectric layer to expose the outside of the bottom plates to form a double-sided capacitor. The support structure further supports the bottom plates during formation of a cell dielectric layer, a capacitor top plate, and final supporting dielectric. An inventive structure is also described.Type: GrantFiled: January 19, 2010Date of Patent: July 22, 2014Assignee: Round Rock Research, LLCInventor: Homer M. Manning
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Patent number: 8779592Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first conductive line disposed over a substrate. The first conductive line is located in a first interconnect layer and extends along a first direction. The semiconductor device includes a second conductive line and a third conductive line each extending along a second direction different from the first direction. The second and third conductive lines are located in a second interconnect layer that is different from the first interconnect layer. The second and third conductive lines are separated by a gap that is located over or below the first conductive line. The semiconductor device includes a fourth conductive line electrically coupling the second and third conductive lines together. The fourth conductive line is located in a third interconnect layer that is different from the first interconnect layer and the second interconnect layer.Type: GrantFiled: May 1, 2012Date of Patent: July 15, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Po Tang, Shih-Ming Chang, Ken-Hsien Hsieh, Ru-Gun Liu
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Patent number: 8748944Abstract: An electrical circuit includes at least two unit cells configured on a planar substrate which extends in one plane. The unit cells respectively have at least two contact points with a different function and include at least one dielectric layer disposed on the substrate and/or on the unit cells and at least two contact surfaces which are disposed parallel to the plane above the contact points and/or the substrate. The contact points with the same function are connected electrically to at least one common contact surface for at least a part of the contact points of the same function via at least one through-contacting through the dielectric layer and able to be contacted in common from outside via the corresponding contact surfaces.Type: GrantFiled: June 16, 2008Date of Patent: June 10, 2014Assignee: MicroGan GmbHInventors: Ingo Daumiller, Ertugrul Soenmez, Mike Kunze
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Patent number: 8735250Abstract: Methods of forming gates of semiconductor devices are provided. The methods may include forming a first recess in a first substrate region having a first conductivity type and forming a second recess in a second substrate region having a second conductivity type. The methods may also include forming a high-k layer in the first and second recesses. The methods may further include providing a first metal on the high-k layer in the first and second substrate regions, the first metal being provided within the second recess. The methods may additionally include removing at least portions of the first metal from the second recess while protecting materials within the first recess from removal. The methods may also include, after removing at least portions of the first metal from the second recess, providing a second metal within the second recess.Type: GrantFiled: September 23, 2011Date of Patent: May 27, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Won Lee, Bo-Un Yoon, Seung-Jae Lee
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Patent number: 8669164Abstract: Microelectronic structures and devices, and method of fabricating a three-dimensional microelectronic structure is provided, comprising passing a first precursor material for a selected three-dimensional microelectronic structure into a reaction chamber at temperatures sufficient to maintain said precursor material in a predominantly gaseous state; maintaining said reaction chamber under sufficient pressures to enhance formation of a first portion of said three-dimensional microelectronic structure; applying an electric field between an electrode and said microelectronic structure at a desired point under conditions whereat said first portion of a selected three-dimensional microelectronic structure is formed from said first precursor material; positionally adjusting either said formed three-dimensional microelectronic structure or said electrode whereby further controlled growth of said three-dimensional microelectronic structure occurs; passing a second precursor material for a selected three-dimensional miType: GrantFiled: April 2, 2010Date of Patent: March 11, 2014Assignee: Los Alamos National Security, LLCInventors: James L. Maxwell, Chris R. Rose, Marcie R. Black, Robert W. Springer
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Patent number: 8637397Abstract: To provide a method of manufacturing a through hole electrode substrate which comprises forming a plurality of through holes passing through the front and back of a wafer-shaped substrate, forming an insulation film on a surface of the substrate and the though hole, forming a seed layer from a metal on at least one side of the substrate and/or the through hole, forming a metal layer having a cap shape on a bottom part of the through hole on a surface on which the seed layer is formed by an electrolytic plating method supplying direct current to the seed layer for a first time period, and filling a metal material into the plurality of through holes by an electrolytic plating method supplying a pulse current to the seed layer and the metal layer.Type: GrantFiled: September 7, 2012Date of Patent: January 28, 2014Assignee: Dai Nippon Printing Co., LtdInventors: Shinji Maekawa, Myuki Suzuki
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Patent number: 8558384Abstract: A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.Type: GrantFiled: June 29, 2012Date of Patent: October 15, 2013Assignee: International Business Machines CorporationInventors: Louis L. Hsu, William R. Tonti, Chih-Chao Yang
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Patent number: 8502383Abstract: An integrated circuit includes active circuitry disposed at a surface of a semiconductor body and an interconnect region disposed above the semiconductor body. A thermoelectric material is disposed in an upper portion of the interconnect region away from the semiconductor body. The thermoelectric material is configured to deliver electrical energy when exposed to a temperature gradient. This material can be used, for example, in a method for detecting the repackaging of the integrated circuit after it has been originally packaged.Type: GrantFiled: September 23, 2011Date of Patent: August 6, 2013Assignee: STMicroelectronics (Rousset) SASInventors: Pascal Fornara, Christian Rivero
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Patent number: 8455360Abstract: A method for fabricating a storage node of a semiconductor device includes forming a sacrificial dielectric pattern with a storage node hole on a substrate, forming a support layer on the sacrificial dielectric pattern, forming a storage node, supported by the support layer, in the storage node hole, performing a full dip-out process to expose the outer wall of the storage node, and performing a cleaning process for removing or reducing a bridge-causing material formed on the surface of the support layer.Type: GrantFiled: March 28, 2011Date of Patent: June 4, 2013Assignee: SK Hynix Inc.Inventors: Hyo Geun Yoon, Ji Yong Park, Sun Jin Lee
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Patent number: 8384143Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.Type: GrantFiled: March 30, 2012Date of Patent: February 26, 2013Assignee: Elpida Memory, Inc.Inventor: Toshiyuki Hirota
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Patent number: 8263457Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive metal nitride-comprising material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Inner sidewalls of the conductive material within the trench are annealed in a nitrogen-comprising atmosphere. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area. The conductive material within the array area is incorporated into a plurality of capacitors.Type: GrantFiled: October 10, 2011Date of Patent: September 11, 2012Assignee: Micron Technology, Inc.Inventors: Vishwanath Bhat, Kevin R. Shea
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Patent number: 8242498Abstract: A compound semiconductor substrate 10 according to the present invention is comprised of a Group III nitride and has a surface layer 12 containing a chloride of not less than 200×1010 atoms/cm2 and not more than 12000×1010 atoms/cm2 in terms of Cl and an oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, at a surface. The inventors conducted elaborate research and newly discovered that when the surface layer 12 at the surface of the compound semiconductor substrate 10 contained the chloride of not less than 200×1010 atoms/cm2 and not more than 12000×1010 atoms/cm2 in terms of Cl and the oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, Si was reduced at an interface between the compound semiconductor substrate 10 and an epitaxial layer 14 formed thereon and, as a result, the electric resistance at the interface was reduced.Type: GrantFiled: November 24, 2010Date of Patent: August 14, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Keiji Ishibashi, Fumitake Nakanishi
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Patent number: 8169015Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.Type: GrantFiled: May 6, 2008Date of Patent: May 1, 2012Assignee: Elpida Memory, Inc.Inventor: Toshiyuki Hirota
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Patent number: 8158512Abstract: There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within a ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; forming a first dielectric layer to cover the discrete compound monolayer; forming a second third monolayer above first dielectric layer; and forming a second discrete compound monolayer; and forming a second dielectric layer to cover the second discrete compound monolayer above the first dielectric layer. There is also provided a semiconductor device formed by the ALD method.Type: GrantFiled: June 17, 2008Date of Patent: April 17, 2012Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Hua Ji, Min-Hwa Chi, Fumitake Mieno, Sean Fuxiong Zhang
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Patent number: 8143123Abstract: A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate with a trench, lining the sidewalls and bottom of the trench with a first layer of dielectric material, filling the trench with a first layer of conductive material to form a first electrode, recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench, forming a layer of polysilicon material on a top surface of the dielectric material and conductive material inside the trench, oxidizing the layer of polysilicon material, and forming a second electrode inside the trench atop the oxidized layer and isolated from trench sidewalls by a second dielectric layer. The oxidation step can be enhanced by either chemically or physically altering the top portion polysilicon such as by implanting impurities.Type: GrantFiled: March 3, 2008Date of Patent: March 27, 2012Assignee: Fairchild Semiconductor CorporationInventors: Thomas E. Grebs, Rodney S. Ridley, Steven P. Sapp, Peter H. Wilson, Babak S. Sani, Gary M. Dolny, John Mytych, Becky Losee, Adam Selsley, Christopher B. Kocon
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Patent number: 8129251Abstract: A METAL-INSULATOR-METAL structured capacitor is formed with polysilicon instead of an oxide film as a sacrificial layer material that defines a storage electrode region. A MPS (Meta-stable Poly Silicon) process is performed to increase the surface area of the sacrificial layer that defines the storage electrode region and also increase the area of the storage electrode formed over sacrificial layer. This process results in increasing the capacity of the capacitor in a stable manner.Type: GrantFiled: November 13, 2006Date of Patent: March 6, 2012Assignee: Hynix Semiconductor Inc.Inventor: Won Sun Seo
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Patent number: 8129240Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive metal nitride-comprising material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Inner sidewalls of the conductive material within the trench are annealed in a nitrogen-comprising atmosphere. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area. The conductive material within the array area is incorporated into a plurality of capacitors.Type: GrantFiled: August 16, 2010Date of Patent: March 6, 2012Assignee: Micron Technology, Inc.Inventors: Vishwanath Bhat, Kevin R. Shea
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Patent number: 8101968Abstract: A group III nitride substrate on which an epitaxially grown layer of good quality can be formed, and a method of manufacturing the same are obtained. A GaN substrate is one of the following: a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface is not more than 2×1014, and the number of silicon atoms per square centimeter of the surface is not more than 3×1013; a group III nitride substrate, wherein the number of silicon atoms per square centimeter of a surface is not more than 3×1013, and a haze level of the surface is not more than 5 ppm; and a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface is not more than 2×1014, and a haze level of the surface is not more than 5 ppm.Type: GrantFiled: January 28, 2011Date of Patent: January 24, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Keiji Ishibashi, Akihiro Hachigo, Masato Irikura, Seiji Nakahata
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Patent number: 8039354Abstract: Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.Type: GrantFiled: August 3, 2010Date of Patent: October 18, 2011Assignee: International Business Machines CorporationInventors: Anil K. Chinthakindi, Douglas D. Coolbaugh, Ebenezer E. Eshun, Zhong-Xiang He, Jeffrey B. Johnson, Jonghae Kim, Jean-Oliver Plouchart, Anthony K. Stamper
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Patent number: 8018045Abstract: The present invention has for its object to provide a multilayer printed circuit board which is very satisfactory in facture toughness, dielectric constant, adhesion and processability, among other characteristics. The present invention is directed to a multilayer printed circuit board comprising a substrate board, a resin insulating layer formed on said board and a conductor circuit constructed on said resin insulating layer, wherein said resin insulating layer comprises a polyolefin resin.Type: GrantFiled: June 25, 2008Date of Patent: September 13, 2011Assignee: Ibiden Co., Ltd.Inventors: Honchin En, Masayuki Hayashi, Dongdong Wang, Kenichi Shimada, Motoo Asai, Koji Sekine, Tohru Nakai, Shinichiro Ichikawa, Yukihiko Toyoda
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Patent number: 7982206Abstract: A light emitting device having high definition, a high aperture ratio, and high reliability is provided. The present invention achieves high definition and a high aperture ratio with a full color flat panel display using red, green, and blue color emission light by intentionally forming laminate portions, wherein portions of different organic compound layers of adjacent light emitting elements overlap with each other, without depending upon the method of forming the organic compound layers or the film formation precision.Type: GrantFiled: May 12, 2010Date of Patent: July 19, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toshiji Hamatani, Toru Takayama
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Publication number: 20110165756Abstract: A semiconductor device includes a guard ring surrounding a memory cell region; a peripheral circuit region outside of the guard ring; a supporting film formed on the guard ring and on the peripheral circuit region; and a contact plug formed in the peripheral circuit region. The guard ring and the contact plug are completely filled with the same conductive material.Type: ApplicationFiled: January 5, 2011Publication date: July 7, 2011Applicant: Elpida Memory, IncInventor: Satoru ISOGAI
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Patent number: 7956400Abstract: An integrated metal-insulator-metal capacitor is formed so that there is an extension portion of its top plate that does not face any portion of the bottom plate, and an extension portion of its bottom plate that does not face any portion of the top plate. Vias connecting the MIM capacitor plates to conductors in an overlying metallization layer are formed so as to contact the extension portions of the top and bottom plates. Etching of the via holes is simplified because it is permissible for the via holes to punch through the extension portions of the capacitor plates. The bottom plate of the MIM capacitor is inlaid. The top plate of the MIM capacitor may be inlaid.Type: GrantFiled: June 15, 2006Date of Patent: June 7, 2011Assignee: Freescale Semiconductor, Inc.Inventor: Brad Smith
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Patent number: 7915133Abstract: A method of forming a ring-type capacitor is provided. The method includes providing a substrate; forming a patterned mask layer on the substrate, the patterned mask layer defining a ring pattern; removing the substrate by using the patterned mask layer as a mask to form a ring-type trench in the substrate; the ring-type trench including an inner wall and an outer wall; and forming a capacitor structure on the inner wall and the outer wall of the ring-type trench.Type: GrantFiled: December 10, 2007Date of Patent: March 29, 2011Assignee: Nanya Technology Corp.Inventors: Kuo-Yao Cho, Wen-Bin Wu, Chiang-Lin Shih, Jen-Jui Huang
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Patent number: 7880268Abstract: A method for forming a MIM-type capacitor by filling of trenches by conformal depositions of insulating materials and of conductive materials, two successive electrodes of the capacitor including on either side of a thin vertical insulating layer at least one conductive layer of same nature, including the step of lowering the level of the conductive layers with respect to the level of the insulating layer separating them.Type: GrantFiled: May 9, 2007Date of Patent: February 1, 2011Assignee: STMicroelectronics S.A.Inventors: Sébastien Cremer, Cédric Perrot, Claire Richard
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Patent number: 7863609Abstract: A compound semiconductor substrate 10 according to the present invention is comprised of a Group III nitride and has a surface layer 12 containing a chloride of not less than 200×1010 atoms/cm2 and not more than 12000×1010 atoms/cm2 in terms of Cl and an oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, at a surface. The inventors conducted elaborate research and newly discovered that when the surface layer 12 at the surface of the compound semiconductor substrate 10 contained the chloride of not less than 200×1010 atoms/cm2 and not more than 12000×1010 atoms/cm2 in terms of Cl and the oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, Si was reduced at an interface between the compound semiconductor substrate 10 and an epitaxial layer 14 formed thereon and, as a result, the electric resistance at the interface was reduced.Type: GrantFiled: April 2, 2010Date of Patent: January 4, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventors: Keiji Ishibashi, Fumitake Nakanishi
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Patent number: 7863173Abstract: Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. An integrated circuit memory cell can be fabricated by forming a cup-shaped electrode on sidewalls of an opening in an insulation layer and through the opening on an ohmic layer that is stacked on a conductive structure. An insulation filling member is formed that at least partially fills an interior of the electrode. The insulation filling member is formed within a range of temperatures that is sufficiently low to not substantially change resistance of the ohmic layer. A variable resistivity material is formed on the insulation filling member and is electrically connected to the electrode.Type: GrantFiled: July 10, 2007Date of Patent: January 4, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Shin-Jae Kang, Gyuhwan Oh, Insun Park, Hyunseok Lim, Nak-Hyun Lim
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Patent number: 7847405Abstract: In one aspect of the present invention, a semiconductor device may include an inter-wiring dielectric film in which a wiring trench is formed, a metal wiring layer formed in the wiring trench in the inter-wiring dielectric film, a first barrier layer formed on a side surface of the wiring trench, the first barrier layer being an oxide film made from a metal different from a main constituent metal element in the wiring layer, a second barrier layer formed on a side surface of the wiring layer, the second barrier layer having a Si atom of the metal used in the wiring layer, and a gap formed between the first barrier layer and the second barrier layer.Type: GrantFiled: May 8, 2009Date of Patent: December 7, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tadayoshi Watanabe, Yumi Hayashi, Takamasa Usui
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Patent number: 7795137Abstract: When a tungsten film (43) is embedded inside of a conductive groove (4A) formed in a wafer (W2) and a silicon oxide film (36) thereon and having a high aspect ratio, film formation and etch back of the tungsten film (43) are successively performed in a chamber of the same apparatus, therefore, a film thickness of the tungsten film (43) deposited in one film formation step is made to be thin. Whereby problems, such as exfoliation of the tungsten film (43), generation of micro-cracks, and occurrence of warpage and cracks of the wafer (W2), are avoided.Type: GrantFiled: August 25, 2006Date of Patent: September 14, 2010Assignees: Hitachi, Ltd., Honda Motor Co., Ltd.Inventors: Toshio Saito, Akira Otaguro, Manabu Otake, Yoshiya Takahira, Namio Katagiri, Nobuaki Miyakawa
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Patent number: 7795648Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.Type: GrantFiled: February 10, 2009Date of Patent: September 14, 2010Assignee: Renesas Technology CorporationInventors: Yoshinori Tanaka, Masahiro Shimizu, Hideaki Arima
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Patent number: 7785962Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive metal nitride-comprising material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Inner sidewalls of the conductive material within the trench are annealed in a nitrogen-comprising atmosphere. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area. The conductive material within the array area is incorporated into a plurality of capacitors.Type: GrantFiled: February 26, 2007Date of Patent: August 31, 2010Assignee: Micron Technology, Inc.Inventors: Vishwanath Bhat, Kevin R. Shea
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Patent number: 7781820Abstract: The semiconductor memory device includes: an interlayer insulating film that is formed on a semiconductor substrate; an insulating film that is formed on the interlayer insulating film and has a cylinder hole; and a capacitor that has an impurity-containing silicon film, a lower metal electrode, a capacitive insulating film and an upper electrode, which are formed so as to cover a bottom and a side of the cylinder hole, wherein the cylinder hole extends through the insulating film so as to expose an end side of the contact plug, the end side facing opposite from the source electrode; and the impurity-containing silicon film has a silicide layer near an interface between the impurity-containing silicon film and the lower metal electrode, the silicide layer being produced by a reaction of impurity-containing silicon included in the impurity-containing silicon film with metal included in the lower metal electrode.Type: GrantFiled: January 22, 2008Date of Patent: August 24, 2010Assignee: Elpida Memory, Inc.Inventor: Shigeru Sugioka
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Patent number: 7781298Abstract: A method for forming a capacitor comprises providing a substrate. A bottom electrode material layer is formed on the substrate. A first mask layer is formed on the bottom electrode material layer. A second mask layer is formed on the first mask layer. The second mask layer is patterned to form a patterned second mask layer in a predetermined region for formation of a capacitor. A plurality of hemispherical grain structures are formed on a sidewall of the patterned second mask layer. The first mask layer is etched by using the hemispherical grain structures and the patterned second mask layer as a mask, thereby forming a patterned first mask layer having a pattern. The pattern of the first mask layer is transferred to the bottom electrode material layer. And, a capacitor dielectric layer and a top electrode layer are formed on the bottom electrode material layer to form the capacitor.Type: GrantFiled: July 3, 2008Date of Patent: August 24, 2010Assignee: Industrial Technology Research InstituteInventors: Hengyuan Lee, Lurng-Shehng Lee, Ching Chiun Wang, Pei-Jer Tzeng
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Patent number: 7781819Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes an insulating layer that is formed on a supporting layer and has a contact hole. A first contact plug is formed on an inner wall and bottom of the contact hole. A second contact plug buries the contact hole and is formed on the first contact plug. A conductive layer is connected to the first contact plug and the second contact plug. The bottom thickness of the first contact plug formed on the bottom of the contact hole is thicker than the inner wall thickness of the first contact plug formed on the inner wall of the contact hole.Type: GrantFiled: November 13, 2008Date of Patent: August 24, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Wan-don Kim, Jin-yong Kim, Yong-suk Tak, Jung-hee Chung, Ki-chul Kim, Oh-seong Kwon
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Patent number: 7768042Abstract: Disclosed herein is a method of manufacturing a thin film transistor including titanium oxides as an active layer and the structure of the thin film transistor film manufactured using the method. The thin film transistor includes: a substrate; an active layer formed on the substrate using polycrystalline or amorphous titanium oxides; and an insulating layer formed on the active layer. Further, the method of manufacturing the thin film transistor includes: forming a substrate; forming an active layer on the substrate using polycrystalline or amorphous titanium oxides; and forming an insulating layer on the active layer.Type: GrantFiled: March 28, 2008Date of Patent: August 3, 2010Assignee: Korea Advanced Institute of Science and TechnologyInventors: Jae-Woo Park, Seunghyup Yoo
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Patent number: 7763925Abstract: A semiconductor device incorporating a capacitor and a method of fabricating the same include a first inter-layer dielectric film formed on a semiconductor substrate, a first electrode pattern formed on the first inter-layer dielectric film, and a capacitor region self-aligned to the first electrode pattern and in which the first inter-layer dielectric film is etched. An MIM capacitor is conformably formed on the sidewall of the first electrode pattern in the capacitor region. In the capacitor region, a first hollow region is formed enclosed by the MIM capacitor and a second electrode pattern fills the first hollow region. The second electrode pattern has a sidewall opposite to the sidewall of the first electrode pattern. The MIM capacitor is conformably formed in the capacitor region that is deepened more than a thickness of an interconnection layer, so that it has a capacitor area wider than an area contacting with the interconnection layer.Type: GrantFiled: May 29, 2007Date of Patent: July 27, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Jun-Pyo Hong
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Patent number: 7763519Abstract: A method for fabricating an interconnect arrangement with increased capacitive coupling is described. A trench structure is formed in a first dielectric having a capacitor region with a first aspect ratio and an interconnect region with a second aspect ratio connected thereto. The trench structure of the interconnect region is completely filled by a first interconnect. The trench structure of the capacitor region is only partially filled by a first capacitor electrode and is completely filled by a capacitor dielectric and a second capacitor electrode. In a second dielectric formed thereon, a second interconnect with a contact via is formed, which is connected to the second capacitor electrode.Type: GrantFiled: August 16, 2005Date of Patent: July 27, 2010Assignee: Infineon Technologies AGInventors: Hans-Joachim Barth, Jürgen Holz