Comprising Inorganic Layer (epo) Patents (Class 257/E21.033)
  • Patent number: 7138341
    Abstract: An exemplary method for making a memory structure comprises forming a first hard mask layer, forming at least one mask layer above the first hard mask layer, patterning the at least one mask layer, etching the at least one mask layer to form an opening having a first lateral width, and a second lateral width different than the first lateral width, forming a second hard mask layer having substantially the first and second lateral widths in the opening, and etching the first hard mask layer using at least one of the lateral widths of the second hard mask layer.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: November 21, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Manish Sharma
  • Patent number: 7115524
    Abstract: The invention includes methods of processing semiconductor substrates. In one implementation, a semiconductor substrate is provided which has an outer surface. Such surface has a peripheral region received about a peripheral edge of the semiconductor substrate. A layer including amorphous carbon is provided over the substrate outer surface. A masking layer is provided outwardly of the amorphous carbon-including layer. A resist layer is provided outwardly of the masking layer. At least a portion of the peripheral region of the outer surface includes the amorphous carbon-including layer and the resist layer, but is substantially void of the masking layer. The amorphous carbon-including layer is patterned using the resist layer and the masking layer effective to form a mask over the semiconductor substrate. After the patterning, the semiconductor substrate is processed inwardly of the mask through openings formed in the mask.
    Type: Grant
    Filed: May 17, 2004
    Date of Patent: October 3, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey W. Honeycutt, Gurtej S. Sandhu