Abstract: A silicon carbide semiconductor device includes a substrate having one of a first conductivity type and a second conductivity type, a drift layer having the first conductivity type, a plurality of base regions having the second conductivity type, a plurality of source regions having the first conductivity type, a surface channel layer having the first conductivity type, a plurality of body layers having the second conductivity type, a gate insulation layer, a gate electrode, a first electrode, a second electrode, and a plurality of second conductivity-type regions. The first electrode is electrically coupled with the source regions and the body layers. The second conductivity-type regions are disposed at portions of the drift layer located under the body layers so as to be connected with the base regions respectively.

Abstract: A SiC device includes: a substrate; a drift layer; a base region; a source region; a channel layer connecting the drift layer and the source region; a gate oxide film on the channel layer and the source region; a gate electrode on the gate oxide film; an interlayer insulation film with a contact hole having a barrier layer and a BPSG insulation film on the gate electrode; a source electrode having upper and lower wiring electrodes on the interlayer insulation film and in the contact hole for connecting the base region and the source region; and a drain electrode on the substrate. The barrier layer prevents a Ni component in the lower wiring electrode from being diffused into the BPSG insulation film.

Abstract: Stress is exerted to the SiC crystal in the region, in which the carriers of a SiC semiconductor device flow, to change the crystal lattice intervals of the SiC crystal. Since the degeneration of the conduction bands in the bottoms thereof is dissolved, since the inter-band scattering is prevented from causing, and since the effective electron mass is reduced due to the crystal lattice interval change, the carrier mobility in the SiC crystal is improved, the resistance of the SiC crystal is reduced and, therefore, the on-resistance of the SiC semiconductor device is reduced.

Abstract: A SiC semiconductor device having a MOS structure includes: a SiC substrate; a channel region providing a current path; first and second impurity regions on upstream and downstream sides of the current path, respectively; and a gate on the channel region through the gate insulating film. The channel region for flowing current between the first and second impurity regions is controlled by a voltage applied to the gate. An interface between the channel region and the gate insulating film has a hydrogen concentration equal to or greater than 4.7×1020 cm?3. The interface provides a channel surface having a (000-1)-orientation surface.

Abstract: Methods of manufacturing a semiconductor device and resulting products. The semiconductor device includes a semiconductor substrate, a hetero semiconductor region hetero-adjoined with the semiconductor substrate, a gate insulation layer contacting the semiconductor substrate and a heterojunction of the hetero semiconductor region, a gate electrode formed on the gate insulation layer, an electric field alleviation region spaced apart from a heterojunction driving end of the heterojunction that contacts the gate insulation layer by a predetermined distance and contacting the semiconductor substrate and the gate insulation layer, a source electrode contacting the hetero semiconductor region and a drain electrode contacting the semiconductor substrate. A mask layer is formed on the hetero semiconductor region, and the electric field alleviation region and the heterojunction driving end are formed by using at least a portion of the first mask layer.

Abstract: Disclosed are embodiments of improved MOSFET and CMOS structures that provides for increased control over short channel effects. Also disclosed are embodiments of associated methods of forming these structures. The embodiments suppress short channel effects by incorporating buried isolation regions into a transistor below source/drain extension regions and between deep source/drain regions and the channel region and, particularly, between deep source/drain regions and the halo regions. Buried isolation regions between the deep source/drain regions and the channel region minimize drain induced barrier lowering (DIBL) as well as punch through. Additionally, because the deep source/drain regions and halo regions are separated by the buried isolation regions, side-wall junction capacitance and junction leakage are also minimized.

Abstract: A silicon carbide metal semiconductor field-effect transistor includes a bi-layer silicon carbide buffer for improving electron confinement in the channel region and/or a layer disposed over at least the channel region of the transistor for suppressing surface effects caused by dangling bonds and interface states. Also, a sloped MESA fabrication method which utilizes a dielectric etch mask that protects the MESA top surface during MESA processing and enables formation of sloped MESA sidewalls.

Abstract: A semiconductor device and a method of manufacturing the device using a (000-1)-faced silicon carbide substrate are provided. A SiC semiconductor device having a high voltage resistancehigh blocking voltage and high channel mobility is manufactured by optimizing the heat-treatment method used following the gate oxidation. The method of manufacturing a semiconductor device includes the steps of forming a gate insulation layer on a semiconductor region formed of silicon carbide having a (000-1) face orientation, forming a gate electrode on the gate insulation layer, forming an electrode on the semiconductor region, cleaning the semiconductor region surface. The gate insulation layer is formed in an atmosphere containing 1% or more H2O (water) vapor at a temperature of from 800° C. to 1150° C. to reduce the interface trap density of the interface between the gate insulation layer and the semiconductor region.

Abstract: A switching element combining a self-aligned, vertical junction field effect transistor with etched-implanted gate and an integrated antiparallel Schottky barrier diode is described. The anode of the diode is connected to the source of the transistor at the device level in order to reduce losses due to stray inductances. The SiC surface in the SBD anode region is conditioned through dry etching to achieve a low Schottky barrier height so as to reduce power losses associated with the turn on voltage of the SBD.