Joining Of Semiconductor Body For Junction Formation (epo) Patents (Class 257/E21.087)
  • Patent number: 9041120
    Abstract: A transistor device comprises: at least one individual transistor cell arranged in a transistor cell field on a semiconductor body, each individual transistor cell comprising a gate electrode; a gate contact, electrically coupled to the gate electrodes of the transistor cells and configured to switch on the at least one transistor cell by providing a gate current in a first direction and configured to switch off the at least one transistor cell by providing a gate current in a second direction, the second direction being opposite to the first direction; at least one gate-resistor structure monolithically integrated in the transistor device, the gate-resistor structure providing a first resistance for the gate current when the gate current flows in the first direction, and providing a second resistance for the gate current, which is different from the first resistance, when the gate current flows in the second direction.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies AG
    Inventors: Stephan Voss, Peter Tuerkes, Holger Huesken
  • Patent number: 8999822
    Abstract: Embodiments of the invention relate generally to creating semiconductor junctions with reduced contact resistance. In one embodiment, the invention provides a method of forming a composition of material, the method comprising: providing at least two populations of semiconducting materials; layering the at least two populations of semiconducting materials to form at least two layers; and consolidating the at least two populations of semiconducting materials, wherein the consolidating creates an electrical connection between the at least two layers.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: April 7, 2015
    Assignee: Evident Technologies
    Inventors: Clinton T. Ballinger, Susanthri Perera, Adam Z. Peng
  • Patent number: 8975156
    Abstract: A method of sealing a first wafer and a second wafer each made of semiconducting materials, including: implanting a metallic species in at least the first wafer, assembling the first wafer and the second wafer by molecular bonding, and after the molecular bonding, forming a metallic ohmic contact including alloys formed between the implanted metallic species and the semiconducting materials of the first wafer and the second wafer, the metallic ohmic contact being formed at an assembly interface between the first wafer and the second wafer, wherein the forming includes causing the implanted metallic species to diffuse towards the interface between the first wafer with the second wafer and beyond the interface.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: March 10, 2015
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Stephane Pocas, Hubert Moriceau, Jean-Francois Michaud
  • Patent number: 8895411
    Abstract: Embodiments of the invention relate generally to creating semiconductor junctions with reduced contact resistance. In one embodiment, the invention provides a method of forming a composition of material, the method comprising: providing at least two populations of semiconducting materials; layering the at least two populations of semiconducting materials to form at least two layers; and consolidating the at least two populations of semiconducting materials, wherein the consolidating creates an electrical connection between the at least two layers.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: November 25, 2014
    Assignee: Evident Technologies
    Inventors: Clinton T. Ballinger, Susanthri Perera, Adam Z. Peng
  • Patent number: 8836116
    Abstract: The embodiments of methods and structures for forming through silicon vias a CMOS substrate bonded to a MEMS substrate and a capping substrate provide mechanisms for integrating CMOS and MEMS devices that use less real-estate and are more reliable. The through silicon vias electrically connect to metal-1 level of the CMOS devices. Copper metal may be plated on a barrier/Cu-seed layer to partially fill the through silicon vias, which saves time and cost. The formation method may involve using dual dielectric layers on the substrate surface as etching mask to eliminate a photolithographical process during the removal of oxide layer at the bottoms of through silicon vias. In some embodiments, the through silicon vias land on polysilicon gate structures to prevent notch formation during etching of the vias.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsueh-An Yang
  • Patent number: 8723185
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon (111) surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: May 13, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai, Ho-Yung David Hwang
  • Patent number: 8703623
    Abstract: A semiconductor arrangement is provided that includes one or more substrate structures. One or more nitride-based material structures are used in fabricating nitride-based devices. One or more intermediary layers are interposed between the one or more substrate structures and the one or more nitride-based material structures. The one or more intermediary layers support the lattice mismatch and thermal expansion coefficients between the one or more nitride-based material structure and the one or more substrate structures. Several new electronic devices based on this arrangement are described.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: April 22, 2014
    Assignee: Massachusetts Institute of Technology
    Inventors: Jinwook Chung, Han Wang, Tomas Palacios
  • Patent number: 8648387
    Abstract: A nitride semiconductor template and a manufacturing method thereof are provided. The nitride semiconductor template includes a carrier substrate with a first thermal expansion coefficient, a nitride semiconductor layer with a second thermal expansion coefficient different from the first thermal expansion coefficient, and a bonding layer. The nitride semiconductor layer disposed on the carrier substrate is at least 10 ?m in thickness. A ratio of a dislocation density of the nitride semiconductor layer at a first surface to that at a second surface is from 0.1 to 10. The bonding layer is disposed between the carrier substrate and the nitride semiconductor layer to adhere the nitride semiconductor layer onto the carrier substrate. The second surface is near an interface between the nitride semiconductor layer and the bonding layer, and the first surface is 10 ?m from the second surface.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: February 11, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Jenq-Dar Tsay, Po-Chun Liu
  • Patent number: 8642443
    Abstract: The present invention relates to the field of semiconductor manufacturing. More specifically, it relates to a method of forming islands of at least partially relaxed strained material on a target substrate including the steps of forming islands of the strained material over a side of a first substrate; bonding the first substrate, on the side including the islands of the strained material, to the target substrate; and after the step of bonding splitting the first substrate from the target substrate and at least partially relaxing the islands of the strained material by a first heat treatment.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: February 4, 2014
    Assignee: Soitec
    Inventor: Romain Boulet
  • Patent number: 8558285
    Abstract: A method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a III-nitride semiconductor, at a temperature below 550° C., to form a device quality heterojunction between the first semiconductor material and the III-nitride semiconductor, wherein the first semiconductor material is different from the III-nitride semiconductor and is selected for superior properties, or preferred integration or fabrication characteristics in the injector region as compared to the III-nitride semiconductor.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: October 15, 2013
    Assignee: The Regents of the University of California
    Inventors: Umesh K. Mishra, Lee S. McCarthy
  • Patent number: 8530256
    Abstract: (a) Forming on a growth substrate a void-containing layer that is made of a group III nitride compound semiconductor and contains voids. (b) Forming on the void-containing layer an n-type layer that is made of an n-type group III nitride compound semiconductor and serves to close the voids. (c) Forming on the n-type layer an active layer made of a group III nitride compound semiconductor. (d) Forming on the active layer a p-type layer made of a p-type group III nitride compound semiconductor. (e) Bonding a support substrate above the p-type layer. (f) Peeling off the growth substrate at the boundary where the void are produced. (g) Planarizing the n-type layer. Step (b) comprises (b1) forming part of the n-type layer under conditions where horizontal growth is relatively weak and (b2) forming the remaining part of the n-type layer under conditions where horizontal growth is relatively strong.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: September 10, 2013
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Yasuyuki Shibata, Ji-Hao Liang, Takako Chinone
  • Patent number: 8486758
    Abstract: Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: July 16, 2013
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Piyush Savalia, Craig Mitchell
  • Patent number: 8455297
    Abstract: Techniques for fabricating carbon nanotube-based devices are provided. In one aspect, a method for fabricating a carbon nanotube-based integrated circuit is provided. The method comprises the following steps. A first wafer comprising carbon nanotubes is provided. A second wafer comprising one or more device elements is provided. One or more of the carbon nanotubes are connected with one or more of the device elements by bonding the first wafer and the second wafer together. A carbon nanotube-based integrated circuit is also provided.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: Phaedon Avouris, Kuan-Neng Chen, Yu-Ming Lin
  • Publication number: 20130049178
    Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Applicant: Aeroflex Colorado Springs Inc.
    Inventors: David B. Kerwin, Joseph Benedetto
  • Publication number: 20130049177
    Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Applicant: Aeroflex Colorado Springs Inc.
    Inventors: David B. Kerwin, Joseph M. Benedetto
  • Patent number: 8378465
    Abstract: The present invention is a method and an apparatus for optical modulation, for example for use in optical communications links. In one embodiment, an apparatus for optical modulation includes a first silicon layer having one or more trenches formed therein, a dielectric layer lining the first silicon layer, and a second silicon layer disposed on the dielectric layer and filling the trenches.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: February 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Yurii A. Vlasov, Fengnian Xia
  • Patent number: 8367520
    Abstract: Methods and structures for producing semiconductor materials, substrates and devices with improved characteristics are disclosed. Structures and methods for forming reduced strain structures include forming an interface between a support structure surface and a strained semiconductor layer. The support structure is selectively etched to form a plurality of semiconductor islands with reduced levels of strain.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: February 5, 2013
    Assignee: Soitec
    Inventor: Chantal Arena
  • Patent number: 8314007
    Abstract: A process for fabricating a heterostructure by bonding a first wafer to a second wafer, with the first wafer having a thermal expansion coefficient that is lower than the thermal expansion coefficient of the second wafer, and conducting at least one bond-strengthening annealing step. After the bonding step and before the bond-strengthening annealing step, at least one trimming step is conducted in which the first wafer is at least partially trimmed.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: November 20, 2012
    Assignee: Soitec
    Inventor: Alexandre Vaufredaz
  • Publication number: 20120241918
    Abstract: The present invention relates to the field of semiconductor manufacturing. More specifically, it relates to a method of forming islands of at least partially relaxed strained material on a target substrate including the steps of forming islands of the strained material over a side of a first substrate; bonding the first substrate, on the side including the islands of the strained material, to the target substrate; and after the step of bonding splitting the first substrate from the target substrate and at least partially relaxing the islands of the strained material by a first heat treatment.
    Type: Application
    Filed: March 23, 2012
    Publication date: September 27, 2012
    Applicant: SOITEC
    Inventor: Romain Boulet
  • Patent number: 8236672
    Abstract: A cavity-containing layer having a plurality of cavities is formed on a growth substrate by carrying out in alternating fashion a plurality of cycles of a first and second growth steps of growing a group III nitride at growth rates different from each other. The semiconductor epitaxial layer is subsequently formed on the cavity-containing layer, after which a support substrate is bonded to the semiconductor epitaxial layer. The growth substrate is separated from the cavity-containing layer.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: August 7, 2012
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Takako Chinone, Ji-Hao Liang, Yasuyuki Shibata, Jiro Higashino
  • Patent number: 8216871
    Abstract: Methods of fabrication of a thermoelectric module from thin film thermoelectric material are disclosed. In general, a thin film thermoelectric module is fabricated by first forming an N-type thin film thermoelectric material layer and one or more metallization layers on a substrate. The one or more metallization layers and the N-type thin film thermoelectric material layer are etched to form a number of N-type thermoelectric material legs. A first electrode assembly is then bonded to a first portion of the N-type thermoelectric material legs, and the first electrode assembly including the first portion of the N-type thermoelectric material legs is removed from the substrate. In a similar manner, a second electrode assembly is bonded to a first portion of a number of P-type thermoelectric material legs. The first and second electrode assemblies are then bonded using a flip-chip bonding process to complete the fabrication of the thermoelectric module.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: July 10, 2012
    Assignee: The Board of Regents of the University of Oklahoma
    Inventor: Patrick John McCann
  • Publication number: 20120132921
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon (111) surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer.
    Type: Application
    Filed: November 30, 2010
    Publication date: May 31, 2012
    Applicant: TAWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai, Ho-Yung David Hwang
  • Publication number: 20120098122
    Abstract: The embodiments of methods and structures for forming through silicon vias a CMOS substrate bonded to a MEMS substrate and a capping substrate provide mechanisms for integrating CMOS and MEMS devices that use less real-estate and are more reliable. The through silicon vias electrically connect to metal-1 level of the CMOS devices. Copper metal may be plated on a barrier/Cu-seed layer to partially fill the through silicon vias, which saves time and cost. The formation method may involve using dual dielectric layers on the substrate surface as etching mask to eliminate a photolithographical process during the removal of oxide layer at the bottoms of through silicon vias. In some embodiments, the through silicon vias land on polysilicon gate structures to prevent notch formation during etching of the vias.
    Type: Application
    Filed: November 11, 2010
    Publication date: April 26, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hsueh-An YANG
  • Publication number: 20120074404
    Abstract: Provided is a supporting substrate (30) to be bonded on a single crystalline wafer composed of a single crystalline body. The supporting substrate is provided with a silicon carbide polycrystalline substrate (10) composed of a silicon carbide polycrystalline body, and a coat layer (20) deposited on the silicon carbide polycrystalline substrate (10). The coat layer (20) is composed of silicon carbide or silicon and is in contact with the single crystalline wafer, and the arithmetic average roughness of the contact surface (22) of the coat layer (20) in contact with the single crystalline wafer is 1 nm or less.
    Type: Application
    Filed: March 19, 2010
    Publication date: March 29, 2012
    Applicant: BRIDGESTONE CORPORATION
    Inventor: Kazuhiro Ushita
  • Publication number: 20120058623
    Abstract: The present invention provides a method of thinning a wafer. First, a wafer is provided. The wafer includes an active surface, a back surface and a side surface. The active surface is disposed opposite to the back surface. The side surface is disposed between the active surface and the back surface and encompasses the peripheral of the wafer. Next, a protective structure is formed on the wafer to at least completely cover the side surface. Last, a thinning process is performed upon the wafer from the back surface.
    Type: Application
    Filed: September 2, 2010
    Publication date: March 8, 2012
    Inventor: Cheng-Yu Hsieh
  • Publication number: 20120024335
    Abstract: The present invention provides a multi-layered thermoelectric device and a method of manufacturing the same. The method for manufacturing a multi-layered thermoelectric device includes the steps of: forming a P-type semiconductor and an N-type semiconductor in a sheet type by mixing thermoelectric semiconductor materials at a preset component ratio; cutting the sheets according to a preset specification of the thermoelectric device; stacking sheets which are made by mixing the thermoelectric semiconductor materials at a preset component ratio and are cut into the same size for each of them; and forming a final thermoelectric device by compressing the stacked sheets. By using the method, scattering phenomenon due to a short wavelength of phonon occurs at a boundary of each layer, which results in active scattering of phonon. Therefore, it is possible to expect an effect of improving a thermoelectric figure of merit of a thermoelectric device.
    Type: Application
    Filed: November 16, 2010
    Publication date: February 2, 2012
    Inventors: Sung Ho LEE, Yong Suk Kim, Young Soo Oh, Tae Kon Koo, Sung Kwon Wi
  • Patent number: 8080842
    Abstract: Disclosed is a nonvolatile memory device with cell and peripheral circuit regions confined on a substrate. Cell gate electrodes are arranged in the cell region while peripheral gate electrodes are arranged in the peripheral-circuit region. Each cell gate electrode includes stacked conductive and semiconductor layers, but the peripheral gate electrode includes stacked semiconductor layers. The conductive layer of the cell gate electrode is different from the lowest semiconductor layer of the peripheral gate electrode in material, which can improve characteristics of memory cells and peripheral transistors without causing mutual interference with each other.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: December 20, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chang-Hyun Lee
  • Publication number: 20110294245
    Abstract: The invention relates to a method of adapting the lattice parameter of a seed layer of a strained material, comprising the following successive steps: a) a structure is provided that has a seed layer of strained material, of lattice parameter A1, of nominal lattice parameter An and of thermal expansion coefficient CTE3, a low-viscosity layer and an intermediate substrate of thermal expansion coefficient CTE1; b) a heat treatment is applied so as to relax the seed layer of strained material; and c) the seed layer is transferred onto a support substrate of thermal expansion coefficient CTE5, the intermediate substrate and the support substrate being chosen so that A1<An and CTE1?CTE3 and CTE5>CTE1 or A1>An and CTE1?CTE3 and CTE5<CTE1.
    Type: Application
    Filed: February 15, 2010
    Publication date: December 1, 2011
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Pascal Guenard, Frederic Dupont
  • Publication number: 20110284870
    Abstract: A method for making a semiconducting structure, including: a) forming, on a surface of a final semiconductor substrate, a semiconducting layer, doped with elements from columns III and V of the Periodic Table so as to form a ground plane, b) forming a dielectric layer, c) then assembling, by direct adhesion of the source substrate, on the final substrate, the layer forming the ground plane between the final substrate and the source substrate, the dielectric layer being between the source substrate and the ground plane, d) then thinning the source substrate, leaving, on the surface of the semiconductor structure, a film made from a semiconducting material.
    Type: Application
    Filed: August 13, 2009
    Publication date: November 24, 2011
    Applicant: COMMISS. A L'ENERGIE ATOM. ET AUX ENERG. ALTERNA.
    Inventors: Yannick Le Tiec, Francois Andrieu
  • Patent number: 8048700
    Abstract: A semiconductor light-emitting device (LE1) comprises a multilayer structure LS generating light. This multilayer structure includes a plurality of laminated compound semiconductor layers (3 to 8) and has first and second main faces (61, 62) opposing each other. A first electrode (21) and a second electrode (31) are arranged on the first and second main faces, respectively. A film made of silicon oxide (10) is also formed on the first main face so as to cover the first electrode. A glass substrate (1) optically transparent to the light generated by the multilayer structure is secured to the multilayer structure through the film made of silicon oxide.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: November 1, 2011
    Assignee: Hamamatsu-shi Photonics K.K.
    Inventor: Akimasa Tanaka
  • Patent number: 8039360
    Abstract: The disclosure identified as methods of mounting integrated circuits, including solar cells, to a substrate wherein the circuits are mounted prior to being singulated into discrete die. Once the semiconductor die sites or other circuits are formed on a wafer, the wafer will be attached, either whole, or divided into one or more multi-die site wafer segments, to a substrate. This attachment may be by conventional surface mount technology, for example. After such mounting, the individual die sites on the wafer segments will be singulated to form discrete die already mounted to the supporting substrate. The singulation may be preferably performed by laser dicing of the wafer segments.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: October 18, 2011
    Assignee: Apple Inc.
    Inventors: Bradley Spare, Michael D. Hillman, Gregory Tice
  • Patent number: 7994506
    Abstract: A semiconductor device having a semiconductor element (a thin film transistor, a thin film diode, a photoelectric conversion element of silicon PIN junction, or a silicon resistor element) which is light-weight, flexible (bendable), and thin as a whole is provided as well as a method of manufacturing the semiconductor device. In the present invention, the element is not formed on a plastic film. Instead, a flat board such as a substrate is used as a form, the space between the substrate (third substrate (17)) and a layer including the element (peeled layer (13)) is filled with coagulant (typically an adhesive) that serves as a second bonding member (16), and the substrate used as a form (third substrate (17)) is peeled off after the adhesive is coagulated to hold the layer including the element (peeled layer (13)) by the coagulated adhesive (second bonding member (16)) alone. In this way, the present invention achieves thinning of the film and reduction in weight.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: August 9, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junya Maruyama, Toru Takayama, Yuugo Goto
  • Publication number: 20110171813
    Abstract: Provided are methods for making a device or device component by providing a multilayer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components.
    Type: Application
    Filed: March 24, 2011
    Publication date: July 14, 2011
    Applicant: The Board of Trustees of the University of Illinois
    Inventors: John A. ROGERS, Ralph G. Nuzzo, Matthew Meitl, Heung Cho Ko, Jongseung Yoon, Etienne Menard, Alfred J. Baca
  • Publication number: 20110156047
    Abstract: A nitride semiconductor template and a manufacturing method thereof are provided. The nitride semiconductor template includes a carrier substrate with a first thermal expansion coefficient, a nitride semiconductor layer with a second thermal expansion coefficient different from the first thermal expansion coefficient, and a bonding layer. The nitride semiconductor layer disposed on the carrier substrate is at least 10 ?m in thickness. A ratio of a dislocation density of the nitride semiconductor layer at a first surface to that at a second surface is from 0.1 to 10. The bonding layer is disposed between the carrier substrate and the nitride semiconductor layer to adhere the nitride semiconductor layer onto the carrier substrate. The second surface is near an interface between the nitride semiconductor layer and the bonding layer, and the first surface is 10 ?m from the second surface.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jenq-Dar Tsay, Po-Chun Liu
  • Publication number: 20110151644
    Abstract: A process for fabricating a heterostructure by bonding a first wafer to a second wafer, with the first wafer having a thermal expansion coefficient that is lower than the thermal expansion coefficient of the second wafer, and conducting at least one bond-strengthening annealing step. After the bonding step and before the bond-strengthening annealing step, at least one trimming step is conducted in which the first wafer is at least partially trimmed.
    Type: Application
    Filed: November 10, 2010
    Publication date: June 23, 2011
    Inventor: Alexandre Vaufredaz
  • Publication number: 20110126874
    Abstract: A thermoelectric segment and a method for fabricating. The fabricating includes forming structures by depositing thin-film metal-semiconductor multilayers on substrates and depositing metal layers on the multilayers, joining metal bonding layers to form dual structures with combined bonding layers; and removing at least one of the substrates; and using the dual structure to form a thermoelectric segments. The method can include dicing the dual structures before or after removing the substrates. The method can include depositing additional bonding layers and joining dual structures to make thermoelectric segments of different thicknesses. Each multilayer can be about 5-10 ?m thick. Each bonding layer can be about 1-2 ?m thick. The bonding layers can be made of a material having high thermal and electrical conductivity. The multilayers can be (Hf,Zr,Ti,W)N/(Sc,Y,La,Ga,In,Al)N superlattice layers. Metal nitride layers can be deposited between each of the bonding layers and multilayers.
    Type: Application
    Filed: November 30, 2010
    Publication date: June 2, 2011
    Inventors: Jeremy Leroy Schroeder, Timothy David Sands
  • Publication number: 20110121311
    Abstract: The present invention provides a method for manufacturing a semiconductor substrate including a low-resistance nitride layer laminated on a substrate, a method for manufacturing a semiconductor device, a semiconductor substrate, and a semiconductor device. A method for manufacturing a semiconductor substrate of the present invention includes the following steps: A nitride substrate having a principal surface and a back surface opposite to the principal surface is prepared. Vapor-phase ions are implanted into the back surface of the nitride substrate. The back surface of the nitride substrate is bonded to a dissimilar substrate to form a bonded substrate. The nitride substrate is partially separated from the bonded substrate to form a laminated substrate including the dissimilar substrate and a nitride layer. The laminated substrate is heat-treated at a temperature over 700° C.
    Type: Application
    Filed: November 10, 2010
    Publication date: May 26, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Fumitaka SATO, Akihiro HACHIGO, Naoki MATSUMOTO, Yoko MAEDA, Seiji NAKAHATA
  • Publication number: 20110108854
    Abstract: Semiconductor devices having atomic lattice matching template interlayers are provided. In one aspect, a semiconductor device can include a first semiconductor material, a second semiconductor material disposed on the first semiconductor material, and an atomic template interlayer disposed between the first semiconductor material and the second semiconductor material, the atomic template interlayer bonding together and facilitating a substantial lattice matching between the first semiconductor material and the second semiconductor material.
    Type: Application
    Filed: October 7, 2010
    Publication date: May 12, 2011
    Inventor: Chien-Min Sung
  • Publication number: 20110065257
    Abstract: New compositions and methods of using those compositions as bonding compositions are provided. The compositions are preferably thermoplastic and comprise imides, amideimides, and/or amideimide-siloxanes (either in polymeric or oligomeric form) dispersed or dissolved in a solvent system, and can be used to bond an active wafer to a carrier wafer or substrate to assist in protecting the active wafer and its active sites during subsequent processing and handling. The compositions form bonding layers that are chemically and thermally resistant, but that can also be softened to allow the wafers to slide apart at the appropriate stage in the fabrication process.
    Type: Application
    Filed: November 18, 2010
    Publication date: March 17, 2011
    Applicant: BREWER SCIENCE INC.
    Inventors: Wenbin Hong, Sunil K. Pillalamarri
  • Publication number: 20110065258
    Abstract: A bonded wafer is thinned from an active layer wafer side, and a thinning stop layer is exposed. Thereafter, the layer is made porous in an HF solution, and then the layer is polished and removed. Thus, the removal of the layer is easy; productivity of substrates is high; no defect is caused due to heat treatment; and evenness in polish amount within a wafer surface can be maintained.
    Type: Application
    Filed: September 8, 2010
    Publication date: March 17, 2011
    Applicant: SUMCO CORPORATION
    Inventors: Hidehiko OKUDA, Takashi SAKAI
  • Publication number: 20110006377
    Abstract: Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.
    Type: Application
    Filed: July 13, 2009
    Publication date: January 13, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Hyung-Kyu Lee, YoungPil Kim, Peter Nicholas Manos, Maroun Khoury, Dadi Setiadi, Chulmin Jung, Hsing-Kuen Liou, Paramasiyan Kamatchi Subramanian, Yongchul Ahn, Jinyoung Kim, Antoine Khoueir
  • Publication number: 20100313957
    Abstract: Solar cells and methods for manufacturing solar cells and/or components or layers thereof are disclosed. An example method for manufacturing a multi-bandgap quantum dot layer for use in a solar cell may include providing a first precursor compound, providing a second precursor compound, and combining a portion of the first precursor compound with a portion of the second precursor compound to form a multi-bandgap quantum dot layer that includes a plurality of quantum dots that differ in bandgap.
    Type: Application
    Filed: June 12, 2009
    Publication date: December 16, 2010
    Applicant: Honeywell International Inc.
    Inventors: Linan Zhao, Zhi Zheng, Marilyn Wang, Xuanbin Liu, Huili Tang
  • Publication number: 20100301347
    Abstract: A semiconductor arrangement is provided that includes one or more substrate structures. One or more nitride-based material structures are used in fabricating nitride-based devices. One or more intermediary layers are interposed between the one or more substrate structures and the one or more nitride-based material structures. The one or more intermediary layers support the lattice mismatch and thermal expansion coefficients between the one or more nitride-based material structure and the one or more substrate structures. Several new electronic devices based on this arrangement are described.
    Type: Application
    Filed: June 1, 2009
    Publication date: December 2, 2010
    Inventors: Jinwook Chung, Han Wang, Tomas Palacios
  • Publication number: 20100261332
    Abstract: The present invention relates to a wafer cleaning and a wafer bonding method using the same that can improve a yield of cleaning process and bonding property in bonding the cleaned wafer by cleaning the wafer using atmospheric pressure plasma and cleaning solution. The wafer cleaning method includes the steps of providing a process chamber with a wafer whose bonding surface faces upward, cleaning and surface-treating the bonding surface of the wafer by supplying atmospheric pressure plasma and a cleaning solution to the bonding surface of the wafer, and withdrawing out the wafer from the process chamber.
    Type: Application
    Filed: October 31, 2007
    Publication date: October 14, 2010
    Inventors: In Sung Kim, Chien Yun Tao, Jeong Il Kang
  • Publication number: 20100244051
    Abstract: An object is to realize an integrated circuit included in a semiconductor device which has multiple functions, or to increase the size of an integrated circuit even when the integrated circuit is formed using a silicon carbide substrate. The integrated circuit includes a first transistor including an island-shaped silicon carbide layer provided over a substrate with a first insulating layer interposed therebetween, a first gate insulating layer provided over the silicon carbide layer, and a first conductive layer provided over the first gate insulating layer and overlapped with the silicon carbide layer; and a second transistor including an island-shaped single crystal silicon layer provided over the substrate with a second insulating layer interposed therebetween, a second gate insulating layer provided over the single crystal silicon layer, and a second conductive layer provided over the second gate insulating layer and overlapped with the single crystal silicon layer.
    Type: Application
    Filed: March 25, 2010
    Publication date: September 30, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Hideto OHNUMA
  • Patent number: 7804100
    Abstract: A device structure includes a III-nitride wurtzite semiconductor light emitting region disposed between a p-type region and an n-type region. A bonded interface is disposed between two surfaces, one of the surfaces being a surface of the device structure. The bonded interface facilitates an orientation of the wurtzite c-axis in the light emitting region that confines carriers in the light emitting region, potentially increasing efficiency at high current density.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: September 28, 2010
    Assignees: Philips Lumileds Lighting Company, LLC, Koninklijke Philips Electronics N.V.
    Inventors: Jonathan J. Wierer, Jr., M. George Craford, John E. Epler, Michael R. Krames
  • Patent number: 7781247
    Abstract: A method of producing one or more vertical light-emitting diode (VLED) dies having a light-emitting diode (LED) stack comprising Group III-Group V combinations of elements (e.g., GaN, AlN, InN, AlGaN, InGaN, and InAlGaN) and a metal substrate is provided. The techniques include forming an InGaN or InAlGaN interface layer above a suitable growth-supporting substrate, such as sapphire or silicon carbide (SiC), and forming the LED stack above the interface layer. Such an interface layer may absorb a majority of the energy from a laser pulse used during laser lift-off of the growth-supporting substrate in an effort to prevent damage to the light emitting layers of the LED stack, which may result in improved brightness performance over VLED dies produced with conventional buffer layers.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: August 24, 2010
    Assignee: SemiLEDs Optoelectronics Co., Ltd.
    Inventor: Anh Chuong Tran
  • Publication number: 20100155740
    Abstract: A cavity-containing layer having a plurality of cavities is formed on a growth substrate by carrying out in alternating fashion a plurality of cycles of a first and second growth steps of growing a group III nitride at growth rates different from each other. The semiconductor epitaxial layer is subsequently formed on the cavity-containing layer, after which a support substrate is bonded to the semiconductor epitaxial layer. The growth substrate is separated from the cavity-containing layer.
    Type: Application
    Filed: December 14, 2009
    Publication date: June 24, 2010
    Applicant: Stanley Electric Co., Ltd.
    Inventors: Takako CHINONE, Ji-Hao Liang, Yasuyuki Shibata, Jiro Higashino
  • Publication number: 20100151618
    Abstract: A method of manufacturing a solar cell by providing a gallium arsenide carrier with a prepared bonding surface; providing a sapphire substrate; bonding the gallium arsenide carrier and the sapphire substrate to produce a composite structure; detaching the bulk of the gallium arsenide carrier from the composite structure, leaving a gallium arsenide growth substrate on the sapphire substrate; and depositing a sequence of layers of semiconductor material forming a solar cell on the growth substrate. For some solar cells, the method further includes mounting a surrogate second substrate on top of the sequence of layers of semiconductor material forming a solar cell; and removing the growth substrate.
    Type: Application
    Filed: December 17, 2008
    Publication date: June 17, 2010
    Applicant: Emcore Solar Power, Inc.
    Inventors: Paul R. Sharps, Arthur Cornfeld, Tansen Varghese, Fred Newman, Jacqueline Diaz
  • Publication number: 20100151612
    Abstract: A method for producing a Group III-V semiconductor device, includes forming, on a base, a plurality of semiconductor devices isolated from one another, forming, through ion implantation, a high-resistance region in a surface layer of a side surface of each semiconductor device, after formation of the high-resistance region, forming a p-electrode and a low-melting-point metal diffusion prevention layer on the top surface of the semiconductor device, bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer, and removing the base through the laser lift-off process.
    Type: Application
    Filed: February 22, 2010
    Publication date: June 17, 2010
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Masanobu Ando, Shigemi Horiuchi, Yoshinori Kinoshita, Kazuyoshi Tomita