By Direct Bonding (epo) Patents (Class 257/E21.088)
  • Patent number: 10446395
    Abstract: Methods of self-aligned multiple patterning and structures formed by self-aligned multiple patterning. A mandrel line is patterned from a first mandrel layer disposed on a hardmask and a second mandrel layer disposed over the first mandrel layer. A first section of the second mandrel layer of the mandrel line is removed to expose a first section of the first mandrel layer. The first section of the first mandrel layer is masked, and the second sections of the second mandrel layer and the underlying second portions of the first mandrel layer are removed to expose first portions of the hardmask. The first portions of the hardmask are then removed with an etching process to form a trench in the hardmask. A second portion of the hardmask is masked by the first portion of the first mandrel layer during the etching process to form a cut in the trench.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Xiaohan Wang, Qiang Fang, Zhiguo Sun, Jinping Liu, Hui Zang
  • Patent number: 10249499
    Abstract: A method for manufacturing a vertical power semiconductor device is provided, wherein a first impurity is provided at the first main side of a semiconductor wafer. A first oxide layer is formed on the first main side of the wafer, wherein the first oxide layer is partially doped with a second impurity in such way that any first portion of the first oxide layer which is doped with the second impurity is spaced away from the semiconductor wafer by a second portion of the first oxide layer which is not doped with the second impurity and which is disposed between the first portion of the first oxide layer and the first main side of the semiconductor wafer. Thereafter a carrier wafer is bonded to the first oxide layer. During front-end-of-line processing on the second main side of the semiconductor wafer, the second impurity is diffused from the first oxide layer into the semiconductor wafer from its first main side by heat generated during the front-end-of-line processing.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: April 2, 2019
    Assignee: ABB Schweiz AG
    Inventors: Wolfgang Janisch, Atze de Vries, Sven Matthias
  • Patent number: 10249788
    Abstract: A semiconductor substrate, a semiconductor device and a manufacturing method of the semiconductor substrate are provided. The semiconductor substrate comprises a first semiconductor layer and a second semiconductor layer located on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer, as well as semiconductor layers obtained by symmetrically rotating the first semiconductor layer and the second semiconductor layer according to their respective lattice structures, have different cleavage planes in a vertical direction. By providing the semiconductor substrates having composite structures, even if thicknesses of the substrates are not changed, the damages to the semiconductor substrates due to stresses by the semiconductor epitaxial layers can be reduced, thereby decreasing the likelihood of breakage of the semiconductor substrates. Furthermore, the processing difficulty is reduced and the reliability of the semiconductor devices is improved.
    Type: Grant
    Filed: July 4, 2016
    Date of Patent: April 2, 2019
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai Cheng
  • Patent number: 10204880
    Abstract: A device and a method for producing a device are disclosed. In an embodiment the device includes a first component, a second component and a connecting element directly arranged between the first component and the second component, wherein the connecting element includes at least a first metal, which is formed as an adhesive layer, a diffusion barrier and a component of a first phase and a second phase of the connecting element, wherein the adhesive layer is arranged on the first component and/or the second component, wherein the first phase and/or the second phase includes, besides the first metal, further metals different from the first metal, wherein a concentration of the first metal in the first phase is greater than a concentration of the first metal in the second phase, and wherein the connecting element includes a layer of a silicide of the first metal.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: February 12, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Barbara Behr, Mathias Wendt, Marcus Zenger
  • Patent number: 10168474
    Abstract: Disclosed are an optical input/output device and an opto-electronic system including the same. The device includes a bulk silicon substrate, at least one vertical-input light detection element monolithically integrated on a portion of the bulk silicon substrate, and at least one vertical-output light source element monolithically integrated on another portion of the bulk silicon substrate adjacent to the vertical-input light detection element. The vertical-output light source element includes a III-V compound semiconductor light source active layer combined with the bulk silicon substrate by a wafer bonding method.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: January 1, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Gyungock Kim, Hyundai Park, In Gyoo Kim, Sang Hoon Kim, Ki Seok Jang, Sang Gi Kim, Jiho Joo, Yongseok Choi, Hyuk Je Kwon, Jaegyu Park, Sun Ae Kim, Jin Hyuk Oh, myung joon Kwack
  • Patent number: 10096971
    Abstract: Various exemplary embodiments relate to an apparatus including: a first substrate including a planar dielectric layer on a semiconducting layer, and a silicon layer located directly on a planar surface of the dielectric layer, adjacent first and second segments of the silicon layer being optically end-coupled, the first segment being thicker than the second segment; and a second substrate including a III-V semiconductor layer segment on a top surface thereof, the first and second substrates being bonded together such that the III-V semiconductor layer segment is in direct contact with a portion of the first segment of the silicon layer.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: October 9, 2018
    Assignee: Alcatel-Lucent USA Inc.
    Inventors: Po Dong, Young-Kai Chen
  • Patent number: 10077188
    Abstract: A method of manufacturing a MEMS chip includes: providing a silicon substrate layer, the silicon substrate layer comprising a front surface configured to perform a MEMS process and a rear surface opposite to the front surface; growing a first oxidation layer mainly made of SiO2 on the rear surface of the silicon substrate layer by performing a thermal oxidation process; and depositing a first thin film layer mainly made of silicon nitride on the first oxidation layer by performing a low pressure chemical vapor deposition process.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: September 18, 2018
    Assignee: CSMC TECHNOLOGIES FAB1 CO., LTD.
    Inventors: Dan Dai, Xinwei Zhang, Guoping Zhou, Changfeng Xia
  • Patent number: 10002754
    Abstract: Electric charging of a substrate caused by a friction between a fluid and a surface of the substrate being rotated can be suppressed. At least a part of a surface insulating layer (thermal oxide film) on a peripheral portion of a substrate W is removed, and an underlayer (silicon wafer) having higher conductivity than a material of the surface insulating layer is exposed. Then, a process is performed on the substrate while holding and rotating the substrate by a substrate holding device. Here, at least a portion of the substrate holding device which comes into contact with the underlayer is made of a conductive material. In performing the process on the substrate, an electric charge generated in the surface insulating layer of the substrate is removed via the underlayer and the substrate holding device.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 19, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Keiichi Tanaka
  • Patent number: 9910018
    Abstract: Micromachined ultrasonic transducers integrated with complementary metal oxide semiconductor (CMOS) substrates are described, as well as methods of fabricating such devices. Fabrication may involve two separate wafer bonding steps. Wafer bonding may be used to fabricate sealed cavities in a substrate. Wafer bonding may also be used to bond the substrate to another substrate, such as a CMOS wafer. At least the second wafer bonding may be performed at a low temperature.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: March 6, 2018
    Assignee: Butterfly Network, Inc.
    Inventors: Jonathan M. Rothberg, Susan A. Alie, Keith G. Fife, Nevada J. Sanchez, Tyler S. Ralston
  • Patent number: 9871133
    Abstract: An LDMOS transistor with a dummy gate comprises an extended drift region over a substrate, a drain region in the extended drift region, a channel region in the extended drift region, a source region in the channel region, a first dielectric layer with a first thickness formed over the extended drift region, a second dielectric layer with a second thickness formed over the extended drift region and the channel region, wherein the first thickness is greater than the second thickness, and wherein the first dielectric layer and the second dielectric layer form two steps, a first gate formed over the first dielectric layer and a second gate formed above the second dielectric layer.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Ruey-Hsin Liu, Jun Cai, Hsueh-Liang Chou, Chi-Chih Chen
  • Patent number: 9865497
    Abstract: A method for manufacturing bonded wafer including: producing bonded wafer having thin-film on its base wafer by an ion implantation delamination method, and reducing film thickness of the thin-film, wherein the step of reducing the film thickness includes a stage of reducing the film thickness by sacrificial oxidation treatment or vapor phase etching, wherein the method for manufacturing bonded wafer further includes a cleaning step of cleaning the bonded wafer exposing the delamination surface just before the step of reducing the film thickness, wherein the cleaning step includes a stage of performing a wet cleaning by successively dipping the bonded wafer to plural of cleaning baths, and wherein the wet cleaning is performed without applying ultrasonic in each of the cleaning baths in the wet cleaning. The method enables to clean bonded wafer exposing delamination surface remaining damage of ion implantation using a cleaning line in a strict control level.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: January 9, 2018
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Isao Yokokawa, Hiroji Aga, Hiroshi Fujisawa
  • Patent number: 9607879
    Abstract: A process for fabrication of a structure includes assembling at least two substrates. At least one of these two substrates is intended to be used in electronics, optics, optoelectronics and/or photovoltaics. The structure includes at least two separation interfaces extending parallel to the main faces of the structure. The assembling process is carried out with a view to a separation of the structure along one interface selected from the interfaces, the separation being carried out by inserting a blade between the substrates and applying a parting force, via the blade. The interface chosen for the separation is formed so that it is more sensitive than the other interface(s) to stress corrosion. Separation occurs due to the combined action of the parting force and of a fluid capable of breaking siloxane (Si—O—Si) bonds present at the interface. A structure obtained by such a process may be separated along the chosen interface.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: March 28, 2017
    Assignee: SOITEC
    Inventor: Didier Landru
  • Patent number: 9548202
    Abstract: The disclosure relates to a method of bonding by molecular adhesion comprising the positioning of a first wafer and of a second wafer within a hermetically sealed vessel, the evacuation of the vessel to a first pressure lower than or equal to 400 hPa, the adjustment of the pressure in the vessel to a second pressure higher than the first pressure by introduction of a dry gas, and bringing the first and second wafers into contact, followed by the initiation of the propagation of a bonding wave between the two wafers, while maintaining the vessel at the second pressure.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: January 17, 2017
    Assignee: Soitec
    Inventors: Marcel Broekaart, Arnaud Castex
  • Patent number: 9299600
    Abstract: A method for repairing an oxide layer and a method for manufacturing a semiconductor structure applying the same are provided. The method for repairing an oxide layer comprises following steps. First, a carrier having a first area and a second area is provided, wherein a repairing oxide layer is formed on the second area. Then, the carrier is attached to a substrate with an oxide layer to be repaired formed thereon, wherein the carrier and the substrate are attached to each other through the repairing oxide layer and the oxide layer to be repaired. Thereafter, the oxide layer to be repaired is bonded with the repairing oxide layer.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: March 29, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Cheng Huang, Yu-Ting Li, Chih-Hsun Lin, Kun-Ju Li, Wu-Sian Sie, Yi-Liang Liu
  • Patent number: 8987753
    Abstract: Provided is a light emitting device, which includes a second conductive type semiconductor layer, an active layer, a first conductive type semiconductor layer, and a intermediate refraction layer. The active layer is disposed on the second conductive type semiconductor layer. The first conductive type semiconductor layer is disposed on the active layer. The intermediate refraction layer is disposed on the first conductive type semiconductor layer. The intermediate refraction layer has a refractivity that is smaller than that of the first conductive type semiconductor layer and is greater than that of air.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: March 24, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: Hyo Kun Son
  • Patent number: 8980671
    Abstract: A manufacturing method of a semiconductor device according to embodiments includes forming a photodiode layer, which is an active region including a photodiode, on a main surface of a first substrate, forming a wiring layer, which includes a wire and a dielectric layer covering the wire, on the photodiode layer, and forming a dielectric film on the wiring layer. The manufacturing method of the semiconductor device according to the embodiments further includes bonding a second substrate to the dielectric film of the first substrate so that a crystal orientation of the photodiode layer matches a crystal orientation of the second substrate.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Hongo, Kazumasa Tanida, Akihiro Hori, Kenji Takahashi, Hideo Numata
  • Patent number: 8951837
    Abstract: A submicron connection layer and a method for using the same to connect wafers is disclosed. The connection layer comprises a bottom metal layer formed on a connection surface of a wafer, an intermediary diffusion-buffer metal layer formed on the bottom metal layer, and a top metal layer formed on the intermediary diffusion-buffer metal layer. The melting point of the intermediary diffusion-buffer metal layer is higher bottom metal layers may form a eutectic phase. During bonding wafers, two top metal layers are joined in a liquid state; next the intermediary diffusion-buffer metal layers are distributed uniformly in the molten top metal layers; then the top and bottom metal layers diffuse to each other to form a low-resistivity eutectic intermetallic compound until the top metal layers are completely exhausted by the bottom metal layers.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: February 10, 2015
    Assignee: National Chiao Tung University
    Inventors: Kuan-Neng Chen, Yao-Jen Chang
  • Patent number: 8940571
    Abstract: P-type semiconductor sheets and n-type semiconductor sheets formed by mixing a powder of semiconductor material, a binder resin, a plasticizer, and a surfactant are prepared. In addition, separator sheets formed by mixing a resin such as PMMA and a plasticizer are prepared. Through holes are formed in each of the separator sheets and then filled with a conductive material. Thereafter, the p-type semiconductor sheet, the separator sheet, the n-type semiconductor sheet and the separator sheet are stacked. The resultant laminated body is cut into a predetermined size and then subjected to a baking process.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: January 27, 2015
    Assignee: Fujitsu Limited
    Inventors: Kazuaki Kurihara, Masaharu Hida, Kazunori Yamanaka
  • Patent number: 8936998
    Abstract: A device is provided with: a first substrate mainly containing silicon dioxide; a second substrate mainly containing silicon, compound semiconductor, silicon dioxide or fluoride; and a bonding functional intermediate layer arranged between the first substrate and the second substrate. The first substrate is bonded to the second substrate thorough room temperature bonding in which a sputtered first surface of the first substrate is contacted with a sputtered second surface of the second substrate via the bonding functional intermediate layer. Here, the material of the bonding functional intermediate layer is selected from among optically transparent materials which are oxide, fluoride, or nitride, the materials being different from the main component of the first substrate and different from the main component of the second substrate.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: January 20, 2015
    Assignees: Mitsubishi Heavy Industries, Ltd., National Institute of Advanced Industrial Science and Technology
    Inventors: Jun Utsumi, Takayuki Goto, Kensuke Ide, Hideki Takagi, Masahiro Funayama
  • Patent number: 8936993
    Abstract: A hybrid substrate comprises first and second active areas made from semiconductor materials laterally offset from one another and separated by an isolation area. The main surfaces of the isolation area and of the first active area form a plane. The hybrid substrate is obtained from a source substrate successively comprising layers made from a first and second semiconductor materials separated by an isolation layer. A single etching mask is used to pattern the isolation area, first active area and second active area. The main surface of the first active area is released thereby forming voids in the source substrate. The etching mask is eliminated above the first active area. A first isolation material is deposited, planarized and etched until the main surface of the first active area is released.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: January 20, 2015
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS
    Inventors: Claire Fenouillet-Béranger, Stéphane Denorme, Philippe Coronel
  • Patent number: 8916450
    Abstract: Methods for removing a material layer from a base substrate utilizing spalling in which mode III stress, i.e., the stress that is perpendicular to the fracture front created in the base substrate, during spalling is reduced. The substantial reduction of the mode III stress during spalling results in a spalling process in which the spalled material has less surface roughness at one of its' edges as compared to prior art spalling processes in which the mode III stress is present and competes with spalling.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: December 23, 2014
    Assignees: International Business Machines Corporation, King Abdulaziz City for Science and Technology
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Ning Li, Devendra K. Sadana, Katherine L. Saenger, Ibrahim Alhomoudi
  • Patent number: 8916448
    Abstract: The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Tien-Jen Cheng, Mukta G. Farooq, John A. Fitzsimmons
  • Patent number: 8836130
    Abstract: An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. In the semiconductor device, silver arranged on a semiconductor element and silver arranged on a base are bonded. No void is present or a small void, if any, is present at an interface between the semiconductor element and the silver arranged on the semiconductor element, no void is present or a small void, if any, is present at an interface between the base and the silver arranged on the base, and one or more silver abnormal growth grains and one or more voids are present in a bonded interface between the silver arranged on the semiconductor element and the silver arranged on the base.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: September 16, 2014
    Assignee: Nichia Corporation
    Inventors: Masafumi Kuramoto, Satoru Ogawa, Teppei Kunimune
  • Patent number: 8796054
    Abstract: A direct wafer bonding process for joining GaN and silicon substrates involves pre-treating each of the wafers in an ammonia plasma in order to render the respective contact surfaces ammophilic. The GaN substrate and the silicon substrate may each comprise single crystal wafers. The resulting hybrid semiconductor structure can be used to form high quality, low cost LEDs.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: August 5, 2014
    Assignee: Corning Incorporated
    Inventor: Alexander Usenko
  • Patent number: 8785292
    Abstract: An anodic bonding apparatus includes a first electrode and a second electrode. The first electrode has a first surface, and the second electrode has a second surface facing the first surface. The first surface includes a first central area; a first substrate placing area for placing a laminated substrate; and a first peripheral area surrounding the first substrate placing area. The second surface includes a second central area corresponding to the first central area; a second substrate placing area surrounding the second central area; and a second peripheral area corresponding to the first peripheral area and surrounding the second substrate placing area. Further, the second electrode includes a curved portion curved toward the first electrode, so that a distance between the first central area and the second central area becomes smaller than a distance between the first peripheral area and the second peripheral area.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: July 22, 2014
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Shinichi Sueyoshi
  • Patent number: 8674382
    Abstract: A semiconductor light emitting device (10) comprises a semiconductor structure (12) comprising a first body (14) of a first semiconductor material (in this case Ge) comprising a first region of a first doping kind (in this case n) and a second body (18) of a second semiconductor material (in this case Si) comprising a first region of a second doping kind (in this case p). The structure comprises a junction region (15) comprising a first heterojunction (16) formed between the first body (14) and the second body (18) and a pn junction (17) formed between regions of the structure of the first and second doping kinds respectively. A biasing arrangement (20) is connected to the structure for, in use, reverse biasing the pn junction, thereby to cause emission of light.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: March 18, 2014
    Assignee: Insiava (Pty) Limited
    Inventors: Lukas Willem Snyman, Monuko Du Plessis
  • Patent number: 8669180
    Abstract: A method for forming semiconductor devices using damascene techniques provides self-aligned conductive lines that have an end-to-end spacing less than 60 nm without shorting. The method includes using at least one sacrificial hardmask layer to produce a mandrel and forming a void in the mandrel. The sacrificial hardmask layers are formed over a base material which is advantageously an insulating material. Another hardmask layer is also disposed over the base material and under the mandrel in some embodiments. Spacer material is formed alongside the mandrel and filling the void. The spacer material serves as a mask and at least one etching procedure is carried out to translate the pattern of the spacer material into the base material. The patterned base material includes trenches and raised portions. Conductive features are formed in the trenches using damascene techniques.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: March 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Patent number: 8664083
    Abstract: InP epitaxial material is directly bonded onto a Silicon-On-Insulator (SOI) wafer having Vertical Outgassing Channels (VOCs) between the bonding surface and the insulator (buried oxide, or BOX) layer. H2O and other molecules near the bonding surface migrate to the closest VOC and are quenched in the buried oxide (BOX) layer quickly by combining with bridging oxygen ions and forming pairs of stable nonbridging hydroxyl groups (Si—OH). Various sizes and spacings of channels are envisioned for various devices.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: March 4, 2014
    Assignee: The Regents of the University of California
    Inventor: Di Liang
  • Patent number: 8609511
    Abstract: According to one embodiment, an insulation film is formed over the surface, backside, and sides of a first substrate. Next, the insulation film formed over the surface of the first substrate is removed. Then, a joining layer is formed over the surface of the first substrate, from which the insulation film has been removed. Subsequently, the first substrate is bonded to a second substrate via a joining layer.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: December 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Shirono, Kazumasa Tanida, Naoko Yamaguchi, Satoshi Hongo, Tsuyoshi Matsumura
  • Patent number: 8604334
    Abstract: An object of the present invention is to provide a simple process to manufacture a wiring connecting photoelectric cells in a photoelectric conversion device. Another object of this invention is to prevent defective rupture from occurring in the said wiring. The photoelectric conversion device comprises a first and a second photoelectric conversion cells comprising respectively a first and a second single crystal semiconductor layers. First electrodes are provided on the downwards surfaces of the first and second photoelectric conversion cells, and second electrodes are provided on their upwards surfaces. The first and second photoelectric conversion cells are fixed onto a support substrate side by side. The second single crystal semiconductor layer has a through hole which reaches the first electrode. The second electrode of the first photoelectric conversion cell is extended to the through hole to be electrically connected to the first electrode of the second photoelectric conversion cell.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: December 10, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuyuki Arai
  • Publication number: 20130320404
    Abstract: A direct wafer bonding process for joining GaN and silicon substrates involves pre-treating each of the wafers in an ammonia plasma in order to render the respective contact surfaces ammophilic. The GaN substrate and the silicon substrate may each comprise single crystal wafers. The resulting hybrid semiconductor structure can be used to form high quality, low cost LEDs.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 5, 2013
    Inventor: Alexander Usenko
  • Patent number: 8575005
    Abstract: A method of manufacturing an electronic device on a plastic substrate includes: providing a carrier as a rigid support for the electronic device; providing a metallic layer on the carrier; forming the plastic substrate on the metallic layer, the metallic layer guaranteeing a temporary bonding of the plastic substrate to the carrier; forming the electronic device on the plastic substrate; and releasing the carrier from the plastic substrate. Releasing the carrier comprises immersing the electronic device bonded to the carrier in a oxygenated water solution that breaks the bonds between the plastic substrate and the metallic layer.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: November 5, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Corrado Accardi, Stella Loverso, Sebastiano Ravesi, Noemi Graziana Sparta
  • Patent number: 8558285
    Abstract: A method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a III-nitride semiconductor, at a temperature below 550° C., to form a device quality heterojunction between the first semiconductor material and the III-nitride semiconductor, wherein the first semiconductor material is different from the III-nitride semiconductor and is selected for superior properties, or preferred integration or fabrication characteristics in the injector region as compared to the III-nitride semiconductor.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: October 15, 2013
    Assignee: The Regents of the University of California
    Inventors: Umesh K. Mishra, Lee S. McCarthy
  • Patent number: 8557678
    Abstract: The invention belongs to the technical field of high-voltage, large-power devices and in particular relates to a method for manufacturing a semiconductor substrate of a large-power device. According to the method, the ion implantation is carried out on the front face of a floating zone silicon wafer first, then a high-temperature resistant metal is used as a medium to bond the back-off floating zone silicon wafer, and a heavily CZ-doped silicon wafer forms the semiconductor substrate. After bonding, the floating zone silicon wafer is used to prepare an insulated gate bipolar transistor (IGBT), and the heavily CZ-doped silicon wafer is used as the low-resistance back contact, so the required amount of the floating zone silicon wafers used is reduced, and production cost is lowered. Meanwhile, the back metallization process is not required after bonding, so the processing procedures are simplified, and the production yield is enhanced.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: October 15, 2013
    Assignee: Fudan University
    Inventors: Pengfei Wang, Xi Lin, Wei Zhang
  • Patent number: 8546875
    Abstract: Described herein are embodiments of a vertical power transistor having drain and gate terminals located on the same side of a semiconductor body and capable of withstanding high voltages in the off-state, in particular voltages of more than 100V.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: October 1, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Andreas Meiser
  • Patent number: 8530336
    Abstract: Defects in a semiconductor substrate are reduced. A semiconductor substrate with fewer defects is manufactured with high yield. Further, a semiconductor device is manufactured with high yield. A semiconductor layer is formed over a supporting substrate with an oxide insulating layer interposed therebetween, adhesiveness between the supporting substrate and the oxide insulating layer in an edge portion of the semiconductor layer is increased, an insulating layer over a surface of the semiconductor layer is removed, and the semiconductor layer is irradiated with laser light, so that a planarized semiconductor layer is obtained. For increasing the adhesiveness between the supporting substrate and the oxide insulating layer in the edge portion of the semiconductor layer, laser light irradiation is performed from the surface of the semiconductor layer.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: September 10, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kosei Nei, Akihisa Shimomura
  • Patent number: 8501518
    Abstract: P-type semiconductor sheets and n-type semiconductor sheets formed by mixing a powder of semiconductor material, a binder resin, a plasticizer, and a surfactant are prepared. In addition, separator sheets formed by mixing a resin such as PMMA and a plasticizer are prepared. Through holes are formed in each of the separator sheets and then filled with a conductive material. Thereafter, the p-type semiconductor sheet, the separator sheet, the n-type semiconductor sheet and the separator sheet are stacked. The resultant laminated body is cut into a predetermined size and then subjected to a baking process.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: August 6, 2013
    Assignee: Fujitsu Limited
    Inventors: Kazuaki Kurihara, Masaharu Hida, Kazunori Yamanaka
  • Patent number: 8492869
    Abstract: A 3D integrated circuit structure is provided. The 3D integrated circuit structure includes an interface wafer including a first wiring layer, a first active circuitry layer including active circuitry, and a wafer including active circuitry. The first active circuitry layer is bonded face down to the interface wafer, and the wafer is bonded face down to the first active circuitry layer. The first active circuitry layer is lower-cost than the wafer.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Fei Liu, Sampath Purushothaman, Albert M. Young, Roy R. Yu
  • Patent number: 8486758
    Abstract: Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: July 16, 2013
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Piyush Savalia, Craig Mitchell
  • Patent number: 8476646
    Abstract: Provided is a light emitting device, which includes a second conductive type semiconductor layer, an active layer, a first conductive type semiconductor layer, and a intermediate refraction layer. The active layer is disposed on the second conductive type semiconductor layer. The first conductive type semiconductor layer is disposed on the active layer. The intermediate refraction layer is disposed on the first conductive type semiconductor layer. The intermediate refraction layer has a refractivity that is smaller than that of the first conductive type semiconductor layer and is greater than that of air.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: July 2, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventor: Hyo Kun Son
  • Patent number: 8471385
    Abstract: A method for the connection of two wafers in which a contact area is formed between the two wafers by placing the two wafers one on top of the other. The contact area is heated locally and for a limited time. A wafer arrangement comprises two wafers which have been placed one on top of the other and between whose opposite surfaces a contact area is located. The wafers are connected to one another at selected areas of the contact area.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: June 25, 2013
    Assignee: Osram Opto Semiconductors GmbH
    Inventor: Klaus Streubel
  • Patent number: 8466039
    Abstract: A method of cleaving a substrate is disclosed. A species, such as hydrogen or helium, is implanted into a substrate to form a layer of microbubbles. The substrate is then annealed a pressure greater than atmosphere. This annealing may be performed in the presence of the species that was implanted. This diffuses the species into the substrate. The substrate is then cleaved along the layer of microbubbles. Other steps to form an oxide layer or to bond to a handle also may be included.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: June 18, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Deepak A. Ramappa, Julian G. Blake
  • Patent number: 8461018
    Abstract: A method and/or system are provided for producing a structure comprising a thin layer of semiconductor material on a substrate. The method includes creating an area of embrittlement in the thickness of a donor substrate, bonding the donor substrate with a support substrate and detaching the donor substrate at the level of the area of embrittlement to transfer a thin layer of the donor substrate onto the support substrate. The method also includes thermal treatment of this resulting structure to stabilize the bonding interface between the thin layer and the substrate support. The invention also relates to the structures obtained by such a process.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: June 11, 2013
    Assignee: S.O.I.TEC Silicon on Insulator Technologies
    Inventors: Eric Neyret, Sebastien Kerdiles
  • Patent number: 8420504
    Abstract: There are provided a semiconductor device having a structure which can realize not only suppression of a punch-through current but also reuse of a silicon wafer used for bonding, in manufacturing a semiconductor device using an SOI technique, and a manufacturing method thereof. A semiconductor film into which an impurity imparting a conductivity type opposite to that of a source region and a drain region is implanted is formed over a substrate, and a single crystal semiconductor film is bonded to the semiconductor film by an SOI technique to form a stacked semiconductor film. A channel formation region is formed using the stacked semiconductor film, thereby suppressing a punch-through current in a semiconductor device.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: April 16, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Sho Kato, Fumito Isaka, Tetsuya Kakehata, Hiromichi Godo, Akihisa Shimomura
  • Patent number: 8420479
    Abstract: A contact level in a semiconductor device may be used for providing a capacitor that may be directly connected to a transistor, thereby providing a very space-efficient capacitor/transistor configuration. For example, superior dynamic RAM arrays may be formed on the basis of the capacitor/transistor configuration disclosed herein.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: April 16, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Dmytro Chumakov
  • Patent number: 8399336
    Abstract: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer that includes active circuitry is provided, and a first portion of the first active circuitry layer wafer is removed such that a second portion of the first active circuitry layer wafer remains. Another wafer that includes active circuitry is provided, and the other wafer is bonded to the second portion of the first active circuitry layer wafer. The first active circuitry layer wafer is lower-cost than the other wafer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: March 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Fei Liu, Sampath Purushothaman, Albert M. Young, Roy R. Yu
  • Patent number: 8361822
    Abstract: A method for producing a light-emitting device, includes: performing, on a first substrate made of III-V group compound semiconductor, crystal growth of a laminated body including an etching easy layer contiguous to the first substrate and a light-emitting layer made of nitride semiconductor; bonding a second substrate and the laminated body; and detaching the second substrate provided with the light-emitting layer from the first substrate by, one of removing the etching easy layer by using a solution etching method, and removing the first substrate and the etching easy layer by using mechanical polishing method.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: January 29, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryo Saeki
  • Patent number: 8354330
    Abstract: The present invention relates to a method of fabricating an SOI SJ LDMOS structure that can completely eliminate the substrate-assisted depletion effects, comprising the following steps: step one: a conducting layer is prepared below the SOI BOX layer using the bonding technique; the conducting layer is prepared in the following way: depositing a barrier layer on a first bulk silicon wafer, and then depositing a charge conducting layer, thereby obtaining a first intermediate structure; forming a silicon dioxide layer on a second bulk silicon wafer via thermal oxidation, then depositing a barrier layer, and finally depositing a charge conducting layer, thereby obtaining a second intermediate structure; bonding the first intermediate structure and the second intermediate structure using the metal bonding technology to arrange the conducting layer below the SOI BOX layer; step two: a SJ LDMOS structure is fabricated on the SOI substrate having a conducting layer.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: January 15, 2013
    Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
    Inventors: Xinhong Cheng, Dawei He, Zhongjian Wang, Dawei Xu, Chao Xia, Zhaorui Song, Yuehui Yu
  • Patent number: 8343851
    Abstract: A wafer temporary bonding method using silicon direct bonding (SDB) may include preparing a carrier wafer and a device wafer, adjusting roughness of a surface of the carrier wafer, and combining the carrier wafer and the device wafer using the SDB. Because the method uses SDB, instead of an adhesive layer, for a temporary bonding process, a module or process to generate and remove an adhesive is unnecessary. Also, a defect in a subsequent process, for example, a back-grinding process, due to irregularity of the adhesive may be prevented.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: January 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-ho Kim, Dae-lok Bae, Jong-wook Lee, Seung-woo Choi, Pil-kyu Kang
  • Patent number: 8329554
    Abstract: A method of making a semiconductor device includes forming an under-film layer over bumps disposed on a surface of a wafer to completely cover the bumps, and forming an adhesive layer over the under-film layer. The method further includes attaching a support layer over the adhesive layer, removing a portion of a back surface of the wafer, and removing the support layer to expose the adhesive layer that remains disposed over the under-film layer. The method further includes removing the adhesive layer to expose the under-film layer while the bumps remain completely covered by the under-film layer, and singulating the wafer to form a semiconductor die. The method further includes pressing the bumps into contact with a substrate while the under-film layer provides an underfill between the semiconductor die and the substrate.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: December 11, 2012
    Assignee: STATS ChipPac, Ltd.
    Inventors: Junghoon Shin, Sangho Lee, Sungyoon Lee