Abstract: A semiconductor structure includes a first substrate including a first pad thereover, a second substrate including a bump thereover and a dielectric material. The first pad includes an inner portion and an outer portion being higher than and surrounding the inner portion. The bump is bonded to the inner portion and surrounded by the outer portion. The dielectric material is disposed between the first substrate and the second substrate to encapsulate the first pad and the bump.

Abstract: The disclosed technology relates generally to the field of semiconductor devices, and more particularly to co-integration of GaN-based devices with Si-based devices. In one aspect, a method of forming a semiconductor device includes forming a first wafer including, on a front side thereof, a III-V semiconductor layer stack formed on a first substrate and a first bonding layer. The III-V semiconductor layer stack includes a GaN-based device layer structure formed on the first substrate. The method additionally includes, subsequent to forming the first wafer, bonding the first bonding layer to a second bonding layer of a second wafer. The second wafer includes a second silicon substrate supporting an active device layer, a back-end-of-line interconnect structure and the second bonding layer. The method further comprises, subsequent to bonding, thinning the first wafer from a backside, wherein thinning includes removing at least the first substrate.

Abstract: An ultra-thin-body GaN-on-Insulator device and a method of manufacturing may be provided. The device comprises a front-end-of-line processed CMOS platform terminated with an interlayer dielectric material, a first bonding layer atop the interlayer dielectric material and an ultra-thin-body GaN-based hetero-structure terminated with a second bonding layer. The GaN-based hetero-structure is bonded with the second bonding layer to the first bonding layer of the CMOS platform building the ultra-thin-body GaN-on-Insulator device.

Abstract: Semiconductor structures and methods of forming the same are disclosed. The semiconductor structure includes a first die, a second die, a first encapsulating material and a protection layer. The first die includes a first substrate. The second die is bonded to the first die and includes a second substrate. The first encapsulating material encapsulates the first die. The protection layer is disposed on a sidewall of the first substrate and between the first substrate and the first encapsulating material, wherein a material of the protection layer is different from materials of the second substrate and the first encapsulating material.

Abstract: Methods of self-aligned multiple patterning and structures formed by self-aligned multiple patterning. A mandrel line is patterned from a first mandrel layer disposed on a hardmask and a second mandrel layer disposed over the first mandrel layer. A first section of the second mandrel layer of the mandrel line is removed to expose a first section of the first mandrel layer. The first section of the first mandrel layer is masked, and the second sections of the second mandrel layer and the underlying second portions of the first mandrel layer are removed to expose first portions of the hardmask. The first portions of the hardmask are then removed with an etching process to form a trench in the hardmask. A second portion of the hardmask is masked by the first portion of the first mandrel layer during the etching process to form a cut in the trench.

Abstract: A semiconductor substrate, a semiconductor device and a manufacturing method of the semiconductor substrate are provided. The semiconductor substrate comprises a first semiconductor layer and a second semiconductor layer located on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer, as well as semiconductor layers obtained by symmetrically rotating the first semiconductor layer and the second semiconductor layer according to their respective lattice structures, have different cleavage planes in a vertical direction. By providing the semiconductor substrates having composite structures, even if thicknesses of the substrates are not changed, the damages to the semiconductor substrates due to stresses by the semiconductor epitaxial layers can be reduced, thereby decreasing the likelihood of breakage of the semiconductor substrates. Furthermore, the processing difficulty is reduced and the reliability of the semiconductor devices is improved.

Abstract: A method for manufacturing a vertical power semiconductor device is provided, wherein a first impurity is provided at the first main side of a semiconductor wafer. A first oxide layer is formed on the first main side of the wafer, wherein the first oxide layer is partially doped with a second impurity in such way that any first portion of the first oxide layer which is doped with the second impurity is spaced away from the semiconductor wafer by a second portion of the first oxide layer which is not doped with the second impurity and which is disposed between the first portion of the first oxide layer and the first main side of the semiconductor wafer. Thereafter a carrier wafer is bonded to the first oxide layer. During front-end-of-line processing on the second main side of the semiconductor wafer, the second impurity is diffused from the first oxide layer into the semiconductor wafer from its first main side by heat generated during the front-end-of-line processing.

Abstract: A device and a method for producing a device are disclosed. In an embodiment the device includes a first component, a second component and a connecting element directly arranged between the first component and the second component, wherein the connecting element includes at least a first metal, which is formed as an adhesive layer, a diffusion barrier and a component of a first phase and a second phase of the connecting element, wherein the adhesive layer is arranged on the first component and/or the second component, wherein the first phase and/or the second phase includes, besides the first metal, further metals different from the first metal, wherein a concentration of the first metal in the first phase is greater than a concentration of the first metal in the second phase, and wherein the connecting element includes a layer of a silicide of the first metal.

Abstract: Disclosed are an optical input/output device and an opto-electronic system including the same. The device includes a bulk silicon substrate, at least one vertical-input light detection element monolithically integrated on a portion of the bulk silicon substrate, and at least one vertical-output light source element monolithically integrated on another portion of the bulk silicon substrate adjacent to the vertical-input light detection element. The vertical-output light source element includes a III-V compound semiconductor light source active layer combined with the bulk silicon substrate by a wafer bonding method.

Abstract: Various exemplary embodiments relate to an apparatus including: a first substrate including a planar dielectric layer on a semiconducting layer, and a silicon layer located directly on a planar surface of the dielectric layer, adjacent first and second segments of the silicon layer being optically end-coupled, the first segment being thicker than the second segment; and a second substrate including a III-V semiconductor layer segment on a top surface thereof, the first and second substrates being bonded together such that the III-V semiconductor layer segment is in direct contact with a portion of the first segment of the silicon layer.

Abstract: A method of manufacturing a MEMS chip includes: providing a silicon substrate layer, the silicon substrate layer comprising a front surface configured to perform a MEMS process and a rear surface opposite to the front surface; growing a first oxidation layer mainly made of SiO2 on the rear surface of the silicon substrate layer by performing a thermal oxidation process; and depositing a first thin film layer mainly made of silicon nitride on the first oxidation layer by performing a low pressure chemical vapor deposition process.

Abstract: Electric charging of a substrate caused by a friction between a fluid and a surface of the substrate being rotated can be suppressed. At least a part of a surface insulating layer (thermal oxide film) on a peripheral portion of a substrate W is removed, and an underlayer (silicon wafer) having higher conductivity than a material of the surface insulating layer is exposed. Then, a process is performed on the substrate while holding and rotating the substrate by a substrate holding device. Here, at least a portion of the substrate holding device which comes into contact with the underlayer is made of a conductive material. In performing the process on the substrate, an electric charge generated in the surface insulating layer of the substrate is removed via the underlayer and the substrate holding device.

Abstract: Micromachined ultrasonic transducers integrated with complementary metal oxide semiconductor (CMOS) substrates are described, as well as methods of fabricating such devices. Fabrication may involve two separate wafer bonding steps. Wafer bonding may be used to fabricate sealed cavities in a substrate. Wafer bonding may also be used to bond the substrate to another substrate, such as a CMOS wafer. At least the second wafer bonding may be performed at a low temperature.

Abstract: An LDMOS transistor with a dummy gate comprises an extended drift region over a substrate, a drain region in the extended drift region, a channel region in the extended drift region, a source region in the channel region, a first dielectric layer with a first thickness formed over the extended drift region, a second dielectric layer with a second thickness formed over the extended drift region and the channel region, wherein the first thickness is greater than the second thickness, and wherein the first dielectric layer and the second dielectric layer form two steps, a first gate formed over the first dielectric layer and a second gate formed above the second dielectric layer.

Abstract: A method for manufacturing bonded wafer including: producing bonded wafer having thin-film on its base wafer by an ion implantation delamination method, and reducing film thickness of the thin-film, wherein the step of reducing the film thickness includes a stage of reducing the film thickness by sacrificial oxidation treatment or vapor phase etching, wherein the method for manufacturing bonded wafer further includes a cleaning step of cleaning the bonded wafer exposing the delamination surface just before the step of reducing the film thickness, wherein the cleaning step includes a stage of performing a wet cleaning by successively dipping the bonded wafer to plural of cleaning baths, and wherein the wet cleaning is performed without applying ultrasonic in each of the cleaning baths in the wet cleaning. The method enables to clean bonded wafer exposing delamination surface remaining damage of ion implantation using a cleaning line in a strict control level.

Abstract: A process for fabrication of a structure includes assembling at least two substrates. At least one of these two substrates is intended to be used in electronics, optics, optoelectronics and/or photovoltaics. The structure includes at least two separation interfaces extending parallel to the main faces of the structure. The assembling process is carried out with a view to a separation of the structure along one interface selected from the interfaces, the separation being carried out by inserting a blade between the substrates and applying a parting force, via the blade. The interface chosen for the separation is formed so that it is more sensitive than the other interface(s) to stress corrosion. Separation occurs due to the combined action of the parting force and of a fluid capable of breaking siloxane (Si—O—Si) bonds present at the interface. A structure obtained by such a process may be separated along the chosen interface.

Abstract: The disclosure relates to a method of bonding by molecular adhesion comprising the positioning of a first wafer and of a second wafer within a hermetically sealed vessel, the evacuation of the vessel to a first pressure lower than or equal to 400 hPa, the adjustment of the pressure in the vessel to a second pressure higher than the first pressure by introduction of a dry gas, and bringing the first and second wafers into contact, followed by the initiation of the propagation of a bonding wave between the two wafers, while maintaining the vessel at the second pressure.

Abstract: A method for repairing an oxide layer and a method for manufacturing a semiconductor structure applying the same are provided. The method for repairing an oxide layer comprises following steps. First, a carrier having a first area and a second area is provided, wherein a repairing oxide layer is formed on the second area. Then, the carrier is attached to a substrate with an oxide layer to be repaired formed thereon, wherein the carrier and the substrate are attached to each other through the repairing oxide layer and the oxide layer to be repaired. Thereafter, the oxide layer to be repaired is bonded with the repairing oxide layer.

Abstract: Provided is a light emitting device, which includes a second conductive type semiconductor layer, an active layer, a first conductive type semiconductor layer, and a intermediate refraction layer. The active layer is disposed on the second conductive type semiconductor layer. The first conductive type semiconductor layer is disposed on the active layer. The intermediate refraction layer is disposed on the first conductive type semiconductor layer. The intermediate refraction layer has a refractivity that is smaller than that of the first conductive type semiconductor layer and is greater than that of air.

Abstract: A manufacturing method of a semiconductor device according to embodiments includes forming a photodiode layer, which is an active region including a photodiode, on a main surface of a first substrate, forming a wiring layer, which includes a wire and a dielectric layer covering the wire, on the photodiode layer, and forming a dielectric film on the wiring layer. The manufacturing method of the semiconductor device according to the embodiments further includes bonding a second substrate to the dielectric film of the first substrate so that a crystal orientation of the photodiode layer matches a crystal orientation of the second substrate.

Abstract: A submicron connection layer and a method for using the same to connect wafers is disclosed. The connection layer comprises a bottom metal layer formed on a connection surface of a wafer, an intermediary diffusion-buffer metal layer formed on the bottom metal layer, and a top metal layer formed on the intermediary diffusion-buffer metal layer. The melting point of the intermediary diffusion-buffer metal layer is higher bottom metal layers may form a eutectic phase. During bonding wafers, two top metal layers are joined in a liquid state; next the intermediary diffusion-buffer metal layers are distributed uniformly in the molten top metal layers; then the top and bottom metal layers diffuse to each other to form a low-resistivity eutectic intermetallic compound until the top metal layers are completely exhausted by the bottom metal layers.

Abstract: P-type semiconductor sheets and n-type semiconductor sheets formed by mixing a powder of semiconductor material, a binder resin, a plasticizer, and a surfactant are prepared. In addition, separator sheets formed by mixing a resin such as PMMA and a plasticizer are prepared. Through holes are formed in each of the separator sheets and then filled with a conductive material. Thereafter, the p-type semiconductor sheet, the separator sheet, the n-type semiconductor sheet and the separator sheet are stacked. The resultant laminated body is cut into a predetermined size and then subjected to a baking process.

Abstract: A device is provided with: a first substrate mainly containing silicon dioxide; a second substrate mainly containing silicon, compound semiconductor, silicon dioxide or fluoride; and a bonding functional intermediate layer arranged between the first substrate and the second substrate. The first substrate is bonded to the second substrate thorough room temperature bonding in which a sputtered first surface of the first substrate is contacted with a sputtered second surface of the second substrate via the bonding functional intermediate layer. Here, the material of the bonding functional intermediate layer is selected from among optically transparent materials which are oxide, fluoride, or nitride, the materials being different from the main component of the first substrate and different from the main component of the second substrate.

Abstract: A hybrid substrate comprises first and second active areas made from semiconductor materials laterally offset from one another and separated by an isolation area. The main surfaces of the isolation area and of the first active area form a plane. The hybrid substrate is obtained from a source substrate successively comprising layers made from a first and second semiconductor materials separated by an isolation layer. A single etching mask is used to pattern the isolation area, first active area and second active area. The main surface of the first active area is released thereby forming voids in the source substrate. The etching mask is eliminated above the first active area. A first isolation material is deposited, planarized and etched until the main surface of the first active area is released.

Abstract: The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility.

Abstract: Methods for removing a material layer from a base substrate utilizing spalling in which mode III stress, i.e., the stress that is perpendicular to the fracture front created in the base substrate, during spalling is reduced. The substantial reduction of the mode III stress during spalling results in a spalling process in which the spalled material has less surface roughness at one of its' edges as compared to prior art spalling processes in which the mode III stress is present and competes with spalling.

Abstract: An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. In the semiconductor device, silver arranged on a semiconductor element and silver arranged on a base are bonded. No void is present or a small void, if any, is present at an interface between the semiconductor element and the silver arranged on the semiconductor element, no void is present or a small void, if any, is present at an interface between the base and the silver arranged on the base, and one or more silver abnormal growth grains and one or more voids are present in a bonded interface between the silver arranged on the semiconductor element and the silver arranged on the base.

Abstract: A direct wafer bonding process for joining GaN and silicon substrates involves pre-treating each of the wafers in an ammonia plasma in order to render the respective contact surfaces ammophilic. The GaN substrate and the silicon substrate may each comprise single crystal wafers. The resulting hybrid semiconductor structure can be used to form high quality, low cost LEDs.

Abstract: An anodic bonding apparatus includes a first electrode and a second electrode. The first electrode has a first surface, and the second electrode has a second surface facing the first surface. The first surface includes a first central area; a first substrate placing area for placing a laminated substrate; and a first peripheral area surrounding the first substrate placing area. The second surface includes a second central area corresponding to the first central area; a second substrate placing area surrounding the second central area; and a second peripheral area corresponding to the first peripheral area and surrounding the second substrate placing area. Further, the second electrode includes a curved portion curved toward the first electrode, so that a distance between the first central area and the second central area becomes smaller than a distance between the first peripheral area and the second peripheral area.

Abstract: A semiconductor light emitting device (10) comprises a semiconductor structure (12) comprising a first body (14) of a first semiconductor material (in this case Ge) comprising a first region of a first doping kind (in this case n) and a second body (18) of a second semiconductor material (in this case Si) comprising a first region of a second doping kind (in this case p). The structure comprises a junction region (15) comprising a first heterojunction (16) formed between the first body (14) and the second body (18) and a pn junction (17) formed between regions of the structure of the first and second doping kinds respectively. A biasing arrangement (20) is connected to the structure for, in use, reverse biasing the pn junction, thereby to cause emission of light.

Abstract: A method for forming semiconductor devices using damascene techniques provides self-aligned conductive lines that have an end-to-end spacing less than 60 nm without shorting. The method includes using at least one sacrificial hardmask layer to produce a mandrel and forming a void in the mandrel. The sacrificial hardmask layers are formed over a base material which is advantageously an insulating material. Another hardmask layer is also disposed over the base material and under the mandrel in some embodiments. Spacer material is formed alongside the mandrel and filling the void. The spacer material serves as a mask and at least one etching procedure is carried out to translate the pattern of the spacer material into the base material. The patterned base material includes trenches and raised portions. Conductive features are formed in the trenches using damascene techniques.

Abstract: InP epitaxial material is directly bonded onto a Silicon-On-Insulator (SOI) wafer having Vertical Outgassing Channels (VOCs) between the bonding surface and the insulator (buried oxide, or BOX) layer. H2O and other molecules near the bonding surface migrate to the closest VOC and are quenched in the buried oxide (BOX) layer quickly by combining with bridging oxygen ions and forming pairs of stable nonbridging hydroxyl groups (Si—OH). Various sizes and spacings of channels are envisioned for various devices.

Abstract: According to one embodiment, an insulation film is formed over the surface, backside, and sides of a first substrate. Next, the insulation film formed over the surface of the first substrate is removed. Then, a joining layer is formed over the surface of the first substrate, from which the insulation film has been removed. Subsequently, the first substrate is bonded to a second substrate via a joining layer.

Abstract: An object of the present invention is to provide a simple process to manufacture a wiring connecting photoelectric cells in a photoelectric conversion device. Another object of this invention is to prevent defective rupture from occurring in the said wiring. The photoelectric conversion device comprises a first and a second photoelectric conversion cells comprising respectively a first and a second single crystal semiconductor layers. First electrodes are provided on the downwards surfaces of the first and second photoelectric conversion cells, and second electrodes are provided on their upwards surfaces. The first and second photoelectric conversion cells are fixed onto a support substrate side by side. The second single crystal semiconductor layer has a through hole which reaches the first electrode. The second electrode of the first photoelectric conversion cell is extended to the through hole to be electrically connected to the first electrode of the second photoelectric conversion cell.

Abstract: A direct wafer bonding process for joining GaN and silicon substrates involves pre-treating each of the wafers in an ammonia plasma in order to render the respective contact surfaces ammophilic. The GaN substrate and the silicon substrate may each comprise single crystal wafers. The resulting hybrid semiconductor structure can be used to form high quality, low cost LEDs.

Abstract: A method of manufacturing an electronic device on a plastic substrate includes: providing a carrier as a rigid support for the electronic device; providing a metallic layer on the carrier; forming the plastic substrate on the metallic layer, the metallic layer guaranteeing a temporary bonding of the plastic substrate to the carrier; forming the electronic device on the plastic substrate; and releasing the carrier from the plastic substrate. Releasing the carrier comprises immersing the electronic device bonded to the carrier in a oxygenated water solution that breaks the bonds between the plastic substrate and the metallic layer.

Abstract: The invention belongs to the technical field of high-voltage, large-power devices and in particular relates to a method for manufacturing a semiconductor substrate of a large-power device. According to the method, the ion implantation is carried out on the front face of a floating zone silicon wafer first, then a high-temperature resistant metal is used as a medium to bond the back-off floating zone silicon wafer, and a heavily CZ-doped silicon wafer forms the semiconductor substrate. After bonding, the floating zone silicon wafer is used to prepare an insulated gate bipolar transistor (IGBT), and the heavily CZ-doped silicon wafer is used as the low-resistance back contact, so the required amount of the floating zone silicon wafers used is reduced, and production cost is lowered. Meanwhile, the back metallization process is not required after bonding, so the processing procedures are simplified, and the production yield is enhanced.

Abstract: A method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a III-nitride semiconductor, at a temperature below 550° C., to form a device quality heterojunction between the first semiconductor material and the III-nitride semiconductor, wherein the first semiconductor material is different from the III-nitride semiconductor and is selected for superior properties, or preferred integration or fabrication characteristics in the injector region as compared to the III-nitride semiconductor.

Abstract: Described herein are embodiments of a vertical power transistor having drain and gate terminals located on the same side of a semiconductor body and capable of withstanding high voltages in the off-state, in particular voltages of more than 100V.

Abstract: Defects in a semiconductor substrate are reduced. A semiconductor substrate with fewer defects is manufactured with high yield. Further, a semiconductor device is manufactured with high yield. A semiconductor layer is formed over a supporting substrate with an oxide insulating layer interposed therebetween, adhesiveness between the supporting substrate and the oxide insulating layer in an edge portion of the semiconductor layer is increased, an insulating layer over a surface of the semiconductor layer is removed, and the semiconductor layer is irradiated with laser light, so that a planarized semiconductor layer is obtained. For increasing the adhesiveness between the supporting substrate and the oxide insulating layer in the edge portion of the semiconductor layer, laser light irradiation is performed from the surface of the semiconductor layer.

Abstract: P-type semiconductor sheets and n-type semiconductor sheets formed by mixing a powder of semiconductor material, a binder resin, a plasticizer, and a surfactant are prepared. In addition, separator sheets formed by mixing a resin such as PMMA and a plasticizer are prepared. Through holes are formed in each of the separator sheets and then filled with a conductive material. Thereafter, the p-type semiconductor sheet, the separator sheet, the n-type semiconductor sheet and the separator sheet are stacked. The resultant laminated body is cut into a predetermined size and then subjected to a baking process.

Abstract: A 3D integrated circuit structure is provided. The 3D integrated circuit structure includes an interface wafer including a first wiring layer, a first active circuitry layer including active circuitry, and a wafer including active circuitry. The first active circuitry layer is bonded face down to the interface wafer, and the wafer is bonded face down to the first active circuitry layer. The first active circuitry layer is lower-cost than the wafer.

Abstract: Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.

Abstract: Provided is a light emitting device, which includes a second conductive type semiconductor layer, an active layer, a first conductive type semiconductor layer, and a intermediate refraction layer. The active layer is disposed on the second conductive type semiconductor layer. The first conductive type semiconductor layer is disposed on the active layer. The intermediate refraction layer is disposed on the first conductive type semiconductor layer. The intermediate refraction layer has a refractivity that is smaller than that of the first conductive type semiconductor layer and is greater than that of air.

Abstract: A method for the connection of two wafers in which a contact area is formed between the two wafers by placing the two wafers one on top of the other. The contact area is heated locally and for a limited time. A wafer arrangement comprises two wafers which have been placed one on top of the other and between whose opposite surfaces a contact area is located. The wafers are connected to one another at selected areas of the contact area.

Abstract: A method of cleaving a substrate is disclosed. A species, such as hydrogen or helium, is implanted into a substrate to form a layer of microbubbles. The substrate is then annealed a pressure greater than atmosphere. This annealing may be performed in the presence of the species that was implanted. This diffuses the species into the substrate. The substrate is then cleaved along the layer of microbubbles. Other steps to form an oxide layer or to bond to a handle also may be included.

Abstract: A method and/or system are provided for producing a structure comprising a thin layer of semiconductor material on a substrate. The method includes creating an area of embrittlement in the thickness of a donor substrate, bonding the donor substrate with a support substrate and detaching the donor substrate at the level of the area of embrittlement to transfer a thin layer of the donor substrate onto the support substrate. The method also includes thermal treatment of this resulting structure to stabilize the bonding interface between the thin layer and the substrate support. The invention also relates to the structures obtained by such a process.

Abstract: There are provided a semiconductor device having a structure which can realize not only suppression of a punch-through current but also reuse of a silicon wafer used for bonding, in manufacturing a semiconductor device using an SOI technique, and a manufacturing method thereof. A semiconductor film into which an impurity imparting a conductivity type opposite to that of a source region and a drain region is implanted is formed over a substrate, and a single crystal semiconductor film is bonded to the semiconductor film by an SOI technique to form a stacked semiconductor film. A channel formation region is formed using the stacked semiconductor film, thereby suppressing a punch-through current in a semiconductor device.

Abstract: A contact level in a semiconductor device may be used for providing a capacitor that may be directly connected to a transistor, thereby providing a very space-efficient capacitor/transistor configuration. For example, superior dynamic RAM arrays may be formed on the basis of the capacitor/transistor configuration disclosed herein.

Abstract: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer that includes active circuitry is provided, and a first portion of the first active circuitry layer wafer is removed such that a second portion of the first active circuitry layer wafer remains. Another wafer that includes active circuitry is provided, and the other wafer is bonded to the second portion of the first active circuitry layer wafer. The first active circuitry layer wafer is lower-cost than the other wafer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.