Abstract: A method of manufacturing a solar cell by providing a gallium arsenide carrier with a prepared bonding surface; providing a sapphire substrate; bonding the gallium arsenide carrier and the sapphire substrate to produce a composite structure; detaching the bulk of the gallium arsenide carrier from the composite structure, leaving a gallium arsenide growth substrate on the sapphire substrate; and depositing a sequence of layers of semiconductor material forming a solar cell on the growth substrate. For some solar cells, the method further includes mounting a surrogate second substrate on top of the sequence of layers of semiconductor material forming a solar cell; and removing the growth substrate.

Abstract: An object is to manufacture a semiconductor substrate having a single crystal semiconductor layer with favorable characteristics, without requiring CMP treatment and/or heat treatment at high temperature. In addition, another object is to improve productivity of semiconductor substrates. Vapor-phase epitaxial growth is performed by using a first single crystal semiconductor layer provided over a first substrate as a seed layer, whereby a second single crystal semiconductor layer is formed over the first single crystal semiconductor layer, and separation is performed at an interface of the both layers. Thus, the second single crystal semiconductor layer is transferred to the second substrate to provide a semiconductor substrate, and the semiconductor substrate is reused by performing laser light treatment on the seed layer.

Abstract: A method of ion cleaving using microwave radiation is described. The method includes using microwave radiation to induce exfoliation of a semiconductor layer from a donor substrate. The donor substrate may be implanted, bonded to a carrier substrate, and heated via the microwave radiation. The implanted portion of the donor substrate may include increased damage and/or dipoles (relative to non-implanted portions of the donor substrate), which more readily absorb microwave radiation. Consequently, by using microwave radiation, an exfoliation time may be reduced to 12 seconds or less. In addition, a presented method also includes the use of focused ion beam implantation to achieve a pattern-less transfer of a semiconductor layer onto a carrier substrate.

Abstract: A method includes: forming a first layer containing silicon oxide on a first substrate; partially removing the first layer to form an exposure portion on the first substrate; depositing amorphous gallium nitride system compound semiconductor on the first substrate with the exposure portion; evaporating the semiconductor on the first layer to form cores of the semiconductor on the exposure portion of the first substrate; forming an epitaxial layer of the semiconductor on the first substrate through increase in a size of the core, combination of the cores, crystal growth, formation of facets, bending of dislocation lines, transverse crystal growth onto the first layer, collision between adjoining crystal grains, combination of the transversely grown crystals, formation of dislocation networks, and formation of a flat surface of the semiconductor; and removing the epitaxial layer of the semiconductor on the exposure portion on the first substrate to form a separating groove.

Abstract: Processes for transferring a semiconductor material to a polymer substrate to provide flexible semiconductor material include implanting ions to a predetermined depth in a semiconductor substrate, heat-treating the ion-implanted semiconductor substrate for a period of time and at a temperature effective to cause defect formation and enlargement of the implanted ion defect, adhering the ion-implanted, heat-treated substrate to a polymer substrate, and separating a semiconductor film such as a single crystal silicon film from the semiconductor substrate; and devices having single crystal silicon films disposed directly or indirectly on polymer films.

Abstract: Methods and structures for producing semiconductor materials, substrates and devices with improved characteristics are disclosed. Structures and methods for forming reduced strain structures include forming an interface between a support structure surface and a strained semiconductor layer. The support structure is selectively etched to form a plurality of semiconductor islands with reduced levels of strain.

Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

Abstract: The present invention relates to method of fabricating a (110) oriented silicon substrate and to a method of fabricating a bonded pair of substrates comprising such a (110) oriented silicon substrate. The invention further relates to a silicon substrate with (110) orientation and to a bonded pair of silicon substrates comprising a first silicon substrate with (100) orientation and a second silicon substrate with (110) orientation. It is the object of the present invention to provide methods and substrates of the above mentioned type with a high efficiency wherein the formed (110) substrate has at least near and at its surface virtually no defects. The object is solved by a method of fabricating a silicon substrate with (110) orientation and by a method of fabricating a bonded pair of silicon substrates, comprising the steps of providing a basic silicon substrate with (110) orientation, said basic silicon substrate having a roughness being equal or less than 0.

Abstract: A polycrystalline Si thin film and a single crystal Si thin film are formed on an SiO2 film deposited on an insulating substrate. A polycrystalline Si layer is grown by thermally crystallizing an amorphous Si thin film so as to form the polycrystalline Si thin film. A single crystal Si substrate, having (a) an SiO2 film thereon and (b) a hydrogen ion implantation portion therein, is bonded to an area of the polycrystalline Si thin film that has been subjected to etching removal, and is subjected to a heating process. Then, the single crystal Si substrate is divided at the hydrogen ion implantation portion in an exfoliating manner, so as to form the single crystal Si thin film. As a result, it is possible to provide a large-size semiconductor device, having the single crystal Si thin film, whose property is stable, at a low cost.

Abstract: A method for manufacturing a thin-film device includes forming a separation layer on a substrate, forming a support layer of mainly clay containing silicate mineral having a layered crystal structure on the separation layer, forming a thin-film functional member on the support layer, applying an energy to the separation layer to reduce the adhesion between the substrate and the support layer, and removing the substrate from the support layer and the thin-film functional member.

Abstract: A method for bonding a semiconductor structure with a substrate and a high efficiency photonic device manufactured by using the same method are disclosed. The method comprises steps of: providing a semiconductor structure and a substrate; forming a composite bonding layer on the semiconductor structure; and bonding the substrate with the composite bonding layer on the semiconductor structure to form a composite alloyed bonding layer. The semiconductor structure includes a compound semiconductor substrate and a high efficiency photonic device is produced after the compound semiconductor substrate is removed. Besides, the composite bonding layer can be formed on the substrate or formed on both the semiconductor structure and substrate simultaneously.

Abstract: Disclosed is a photoelectric conversion device comprising a first conductive support having a layer containing a semiconductor, a second conductive support arranged opposite to the first conductive support and having a counter electrode, and a charge transfer layer interposed between the first conductive support and the second conductive support at a certain distance from the supports, and a sealing agent which is arranged around the charge transfer layer in the form of a single or more than single layer for bonding the first conductive support and the second conductive support together.

Abstract: The present invention provides a semiconductor device which can be produced by simple and cheap processes and effectively achieve improved performances and a reduced electric power consumption. Further, the present invention provides a production method thereof and a display device including the semiconductor device or a semiconductor device produced by the production method. The present invention is a semiconductor device including a pixel part and an integrated circuit part on a substrate, the pixel part including a switching element having a gate electrode formed on a semiconductor thin film, the integrated circuit part including a semiconductor layer on a gate electrode, wherein a passivation film is formed on the gate electrode in the pixel part.

Abstract: An apparatus and method for manufacturing metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, which MOS transistors are area efficient, and where the drive strength and leakage current of the MOS transistors is improved. The invention uses a dynamic threshold voltage control scheme that does not require a change to the existing MOS technology process. The invention provides a technique that controls the threshold voltage of the transistor. In the OFF state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. In the ON state, the threshold voltage is set to a low value, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS.

Abstract: Embodiments herein present device, method, etc. for a hybrid orientation scheme for standard orthogonal circuits. An integrated circuit of embodiments of the invention comprises a hybrid orientation substrate, comprising first areas having a first crystalline orientation and second areas having a second crystalline orientation. The first crystalline orientation of the first areas is not parallel or perpendicular to the second crystalline orientation of the second areas. The integrated circuit further comprises first type devices on the first areas and second type devices on the second areas, wherein the first type devices are parallel or perpendicular to the second type devices. Specifically, the first type devices comprise p-type field effect transistors (PFETs) and the second type devices comprise n-type field effect transistors (NFETs).

Abstract: One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline semiconductor bridge is formed over a substrate. The bridge has a first portion bonded to the substrate, a second portion bonded to the substrate, and a middle portion between the first and second portions separated from the substrate. The middle portion of the bridge is bonded to the substrate to provide a compressed crystalline semiconductor layer on the substrate. Other aspects are provided herein.

Abstract: An image sensor includes a first substrate, a lower metal line, a circuitry, a first insulating layer, a crystalline semiconductor layer, a photodiode, and a contact line. The lower metal line and the circuitry are formed on and/or over the first substrate and the first insulating layer is formed on and/or over the lower metal line. The crystalline semiconductor layer contacts the first insulating layer and is bonded to the first substrate. The photodiode is formed in the crystalline semiconductor layer. The contact line electrically connects the photodiode to the lower metal line.

Abstract: New compositions and methods of using those compositions as bonding compositions are provided. The compositions are preferably thermoplastic and comprise imides, amideimides, and/or amideimide-siloxanes (either in polymeric or oligomeric form) dispersed or dissolved in a solvent system, and can be used to bond an active wafer to a carrier wafer or substrate to assist in protecting the active wafer and its active sites during subsequent processing and handling. The compositions form bonding layers that are chemically and thermally resistant, but that can also be softened to allow the wafers to slide apart at the appropriate stage in the fabrication process.

Abstract: A direct bond substrate formed by bonding semiconductor substrates together, a semiconductor device using the direct bond substrate and a manufacturing method thereof are disclosed. A nitride film, oxynitride film, carbide film or an oxide film containing carbon is provided on the bonded interface of the semiconductor substrates in the direct bond substrate.

Abstract: It is an object of the present invention to obtain a large-sized SOI substrate by providing a single-crystal silicon layer over a large-sized glass substrate in a large area. After a plurality of rectangular single-crystal semiconductor substrates each provided with a separation layer are aligned over a dummy substrate and both of the substrates are fixed with a low-temperature coagulant, the plurality of single-crystal semiconductor substrates are bonded to a support substrate; the temperature is raised up to a temperature, at which the low-temperature coagulant does not to have a bonding effect, so as to isolate the dummy substrate and the single-crystal semiconductor substrates; heat treatment is performed to separate part of the single-crystal semiconductor substrates, along a boundary of the respective separation layers; and single-crystal semiconductor layers are provided over the support substrate.

Abstract: The invention concerns a method for preparing a thin layer (28) or a chip to be transferred onto another substrate, this method including the realization, above the surface of said thin layer or said chip, of at least one layer, called adhesive layer (25), and of at least one layer, called first barrier layer (22), the adhesive layer being made of a material of which etching presents selectivity in relation to the material of the barrier layer.

Abstract: A process for preparing a semiconductor wafer with a strained layer having an elevated critical thickness.

Abstract: The present invention provides a production method of a semiconductor device, which can improve characteristics of a semiconductor element including a single crystal semiconductor layer formed by transferring on an insulating substrate. The present invention is a production method of a semiconductor device comprising a single crystal semiconductor layer formed on an insulating substrate, the production method comprising the steps of: implanting a substance for separation into a single crystal semiconductor substrate, thereby forming a separation layer; transferring a part of the single crystal semiconductor substrate, separated at the separation layer, onto the insulating substrate, thereby forming the single crystal semiconductor layer; forming a hydrogen-containing layer on at least one side of the single crystal semiconductor layer; and diffusing hydrogen from the hydrogen-containing layer to the single crystal semiconductor layer.

Abstract: The present invention provides a method of manufacturing a bonded wafer. When bonding the top wafer through an insulating film exceeding about 1,000 Angstroms in thickness to the base wafer, a top wafer and a base wafer in which the total number of particles having a size of equal to or greater than about 0.20 micrometers present on the two surfaces being bonded is equal to or less than about 0.014 particles/cm2 are bonded; and when bonding the top wafer through an insulating film having a thickness of equal to or less than about 1,000 Angstroms to the base wafer, or with no insulating film present between the top wafer and the base wafer, a top wafer and a base wafer are bonded wherein the total number of particles having a size of equal to or greater than about 0.20 micrometers present on the two surfaces being bonded is equal to or less than about 0.007 particles/cm2.

Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

Abstract: A method for producing Microelectromechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI) wafer includes providing an SOI wafer, performing a mesa etch to at least partially define the MEMS device, bonding the SOI wafer to an interposer by direct boding, removing the handle layer of the SOI wafer, removing the oxide layer of the SOI wafer, and further etching the device layer of the SOI wafer to define the MEMS device. A structure manufactured according to the above described processes includes an interposer comprising an SOI wafer and a MEMS device mounted on the interposer. The MEMS device comprises posts extending from a silicon plate. The MEMS device is directly mounted to the interposer by bonding the posts of the MEMS device to the device layer of the interposer.

Abstract: An object of the present invention is to provide an adhesive sheet that can fill irregularities due to wiring of a substrate or a wire attached to a semiconductor chip, etc., does not form resin burrs during dicing, and has satisfactory heat resistance and moisture resistance. The present invention relates to an adhesive sheet comprising 100 parts by weight of a resin comprising 15 to 40 wt % of a high molecular weight component containing a crosslinking functional group and having a weight-average molecular weight of 100,000 or greater and a Tg of ?50° C. to 50° C., and 60 to 85 wt % of a thermosetting component containing an epoxy resin as a main component, and 40 to 180 parts by weight of a filler, the adhesive sheet having a thickness of 10 to 250 ?m.

Abstract: An adhesive bonding sheet having an optically transmitting supporting substrate and an adhesive bonding layer, and being used in both a dicing step and a semiconductor element adhesion step, wherein the adhesive bonding layer comprises: a polymer component (A) having a weight average molecular weight of 100,000 or more including functional groups; an epoxy resin (B); a phenolic epoxy resin curing agent (C); a photoreactive monomer (D), wherein the Tg of the cured material obtained by ultraviolet light irradiation is 250° C. or more; and a photoinitiator (E) which generates a base and a radical by irradiation with ultraviolet light of wavelength 200-450nm.

Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.