Abstract: Methods for forming a ceramic matrix composite (CMC) are generally provided. The method may include melt infiltrating a silicon mixture into a ceramic matrix composite preform, with the silicon mixture including SiGa, SiIn, or a mixture thereof. The silicon mixture may include silicon metal in combination with SiGa, SiIn, or the mixture thereof. Additionally, the silicon mixture may further include B within the SiGa, SiIn, or the mixture thereof (e.g., in the form of SiBGa, SiBIn, or a mixture thereof).

Abstract: Methods are described for fabricating HIT solar cells, including double heterojunction and hybrid heterojunction-homojunction solar cells, with very thin single crystal silicon wafers, where the silicon wafer may be less than 80 microns thick, and even less than 50 microns thick. The methods overcome potential issues with handling these very thin wafers by using a process including epitaxial silicon deposition on a growth substrate, partial cell fabrication, attachment to a support substrate and then separation from the growth substrate. Some embodiments of the present invention may include a solar cell device architecture comprising the combination of a heterostructure on the front side of the device with a homojunction at the rear of the device. Furthermore, device performance may be enhanced by including a dielectric stack on the backside of the device for reflecting long wavelength infrared radiation.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.

Abstract: A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the sample's GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO2 layer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiO2 layer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiO2 layer on the nMOSFET structure; performing a CMOS process.

Abstract: P-type silicon single crystals from which wafers having high resistivity, good radial uniformity of resistivity and less variation in resistivity can be obtained, are manufactured by the Czochralski method from an initial silicon melt in which boron and phosphorus are present, the boron concentration is not higher than 4E14 atoms/cm3 and the ratio of the phosphorus concentration to the boron concentration is not lower than 0.42 and not higher than 0.50.

Abstract: A method of forming an epitaxial layer includes the following steps. At first, a first epitaxial growth process is performed to form a first epitaxial layer on a substrate, and a gas source of silicon, a gas source of carbon, a gas source of phosphorous and a gas source of germanium are introduced during the first epitaxial growth process to form the first epitaxial layer including silicon, carbon, phosphorous and germanium. Subsequently, a second epitaxial growth process is performed to form a second epitaxial layer, and a number of elements in the second epitaxial layer is smaller than a number of elements in the first epitaxial layer.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming a carbon-containing layer on a front surface of a semiconductor substrate and depositing a metal film on the carbon layer. A thermal cycle degrades the carbon-containing layer, which forms graphene directly upon the semiconductor substrate upon cooling. In some embodiments, the carbon source is a carbon-containing gas, and the thermal cycle causes diffusion of carbon atoms into the metal film, which, upon cooling, segregate and precipitate into a layer of graphene directly on the semiconductor substrate.

Abstract: A method for producing a structure including an active part with a first and a second suspended zone. The method includes machining the front face of a first substrate to define the lateral contours of at least one first suspended zone according to a first thickness less than that of the first substrate forming a stop layer of etching of the first suspended zone under the suspended zone, forming on the front face of the first substrate a sacrificial layer, machining from the rear face of the first substrate up to releasing the sacrificial layer to form at least one second suspended zone to reach the stop layer of the first suspended zone, and releasing the first and second suspended zones.

Abstract: To provide a light-emitting device including the plurality of light-emitting elements having a structure in which a light-emitting area is large and defects in patterning of light-emitting elements are suppressed. To provide a lighting device including the light-emitting device. The light-emitting device includes a first wiring provided over a substrate having an insulating surface, an insulating film provided over the first wiring, a second wiring provided over the insulating film, and a light-emitting element unit including a plurality of light-emitting elements provided over the first wiring with the insulating film provided therebetween. The plurality of light-emitting elements each include a first electrode layer having a light-blocking property, a layer containing an organic compound in contact with the first electrode layer, and a second electrode layer having a light-transmitting property in contact with the layer containing an organic compound.

Abstract: A method for fabricating a semiconductor device includes forming a metal layer on a substrate, forming a plurality of layers of a magnetic tunnel junction (MTJ) element on the metal layer, forming a carbon layer including a hole, wherein the hole penetrates through the carbon layer, forming a metal pattern in the hole of the carbon layer, removing the carbon layer; and patterning the plurality of layers of the MTJ element using the metal pattern as an etching mask.

Abstract: The present invention relates to a method for decreasing or increasing the band gap shift in the production of photovoltaic devices by means of coating a substrate with a formulation containing a silicon compound, e.g., in the production of a solar cell comprising a step in which a substrate is coated with a liquid-silane formulation, the invention being characterized in that the formulation also contains at least one germanium compound. The invention further relates to the method for producing such a photovoltaic device.

Abstract: The invention provides a solid-state image pickup device and method for realizing a higher sensitivity and a higher S/N ratio especially in the low-luminance region while maintaining a wide dynamic range.

Abstract: A CMOS image sensor includes a substrate including silicon, a silicon germanium (SiGe) epitaxial layer formed over the substrate, the SiGe epitaxial layer formed through epitaxial growth and doped with a predetermined concentration level of impurities, an undoped silicon epitaxial layer formed over the SiGe epitaxial layer by epitaxial growth, and a photodiode region formed from a top surface of the undoped silicon epitaxial layer to a predetermined depth in the SiGe epitaxial layer.

Abstract: A method of forming an inverted T shaped channel structure having a vertical channel portion and a horizontal channel portion for an Inverted T channel Field Effect Transistor ITFET device comprises semiconductor substrate, a first layer of a first semiconductor material over the semiconductor substrate and a second layer of a second semiconductor material over the first layer. The first and the second semiconductor materials are selected such that the first semiconductor material has a rate of removal which is less than a rate of removal of the second semiconductor material.

Abstract: There is provided a group III nitride semiconductor epitaxial substrate which has a suppressed level of threading dislocation in the vertical direction and excellent crystal quality, the group III nitride semiconductor epitaxial substrate including a substrate (1) for growing an epitaxial film; and an ELO layer (4) having a composition of AlxGa1-xN (0?x?1) formed either on top of the substrate (1) or on top of a group III nitride layer (2) formed on top of the substrate (1), wherein the ELO layer (4) is a layer formed by using a mask pattern (3), which is composed of carbon and is formed either on top of the substrate (1) or on top of the group III nitride layer (2).

Abstract: A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess.

Abstract: The present disclosure provides a nanotube solution being treated with a molecular additive, a nanotube film having enhanced adhesion property due to the treatment of the molecular additive, and methods for forming the nanotube solution and the nanotube film. The nanotube solution includes a liquid medium, nanotubes in the liquid medium, and a molecular additive in the liquid medium, wherein the molecular additive includes molecules that provide source elements for forming a group IV oxide within the nanotube solution. The molecular additive can introduce silicon (Si) and/or germanium (Ge) in the liquid medium, such that nominal silicon and/or germanium concentrations of the nanotube solution ranges from about 5 ppm to about 60 ppm.

Abstract: A semiconductor substrate is irradiated with accelerated hydrogen ions, thereby forming a damaged region including a large amount of hydrogen. After a single crystal semiconductor substrate and a supporting substrate are bonded to each other, the semiconductor substrate is heated, so that the single crystal semiconductor substrate is separated in the damaged region. A single crystal semiconductor layer which is separated from the single crystal semiconductor substrate is irradiated with a laser beam. The single crystal semiconductor layer is melted by laser beam irradiation, whereby the single crystal semiconductor layer is recrystallized to recover its crystallinity and to planarized a surface of the single crystal semiconductor layer. After the laser beam irradiation, the single crystal semiconductor layer is heated at a temperature at which the single crystal semiconductor layer is not melted, so that the lifetime of the single crystal semiconductor layer is improved.

Abstract: Silicon single crystal substrates having uniform resistance, few BMDs in a surface layer and a moderate number of BMDs in a center of thickness of the substrate are formed from Czochralski silicon single crystals. The substrates have a resistivity in the center of a first main surface not lower than 50 ?·cm and a rate of change in resistivity in the first main surface not higher than 3%, an average density of bulk micro defects in a region between the first main surface and a plane at a depth of 50 ?m of less than 1×108/cm3, and an average density of bulk micro defects in a region lying between a plane at a depth of 300 ?m and a plane at a depth of 400 ?m from the first main surface not lower than 1×108 /cm3 and not higher than 1×109 /cm3.

Abstract: Doped semiconductor ink formulations, methods of making doped semiconductor ink formulations, methods of coating or printing thin films, methods of forming electronic devices and/or structures from the thin films, and methods for modifying and controlling the threshold voltage of a thin film transistor using the films are disclosed. A desired dopant may be added to an ink formulation comprising a Group IVA compound and a solvent, and then the ink may be printed on a substrate to form thin films and conductive structures/devices, such as thin film transistors. By adding a customized amount of the dopant to the ink prior to printing, the threshold voltage of a thin film transistor made from the doped semiconductor ink may be independently controlled upon activation of the dopant.

Abstract: Methods of selective formation leave high quality epitaxial material using a repeated deposition and selective etch process. During the deposition process, an inert carrier gas is provided with a silicon-containing source without hydrogen carrier gas. After depositing silicon-containing material, an inert carrier gas is provided with an etchant to selectively etch deposited material without hydrogen. The deposition and etch processes can be repeated until a desired thickness of silicon-containing material is achieved. Using the processes described within, it is possible to maintain temperature and pressure conditions, as well as inert carrier gas flow rates, to provide for increased throughput. The inert flow can be constant, or etch rates can be increased by reducing inert flow for the etch phases of the cycles.

Abstract: A method of forming an integrated circuit structure, the method includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; forming a seed layer in the opening; forming a copper line on the seed layer, wherein at least one of the seed layer and the copper line includes an alloying material; and forming an etch stop layer on the copper line.

Abstract: Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein.

Abstract: A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess.

Abstract: A three-dimensional polycrystalline semiconductor material provides a major ingredient forming individual crystalline grains having a nominal maximum grain diameter less than or equal to 50 nm, and a minor ingredient forming boundaries between the individual crystalline grains.

Abstract: A method of forming an inverted T shaped channel structure having a vertical channel portion and a horizontal channel portion for an Inverted T channel Field Effect Transistor ITFET device comprises providing a semiconductor substrate, providing a first layer of a first semiconductor material over the semiconductor substrate, and providing a second layer of a second semiconductor material over the first layer. The first and the second semiconductor materials are selected such that the first semiconductor material has a rate of removal which is less than a rate of removal of the second semiconductor material. The method further comprises removing a portion of the first layer and a portion of the second layer selectively according to the different rates of removal so as to provide a lateral layer and the vertical channel portion of the inverted T shaped channel structure and removing a portion of the lateral layer so as to provide the horizontal channel portion of the inverted T shaped channel structure.

Abstract: A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm?2 to be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.

Abstract: A nanostructure comprising germanium, including wires of less than 1 micron in diameter and walls of less than 1 micron in width, in contact with the substrate and extending outward from the substrate is provided along with a method of preparation.

Abstract: An integrated circuit system includes a substrate, a carbon-containing silicon region over the substrate, a non-carbon-containing silicon region over the substrate, and a silicon-carbon region, including the non-carbon-containing silicon region and the carbon-containing silicon region.

Abstract: A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation.

Abstract: A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide material. Consequently, a lateral offset of the strain-inducing semiconductor material may be reduced, while nevertheless providing a sufficient thickness of corresponding offset spacers during the cavity etch process, thereby preserving gate electrode integrity. For instance, P-channel transistors may have a silicon/germanium alloy with a hexagonal shape, thereby significantly enhancing the overall strain transfer efficiency.

Abstract: In a strained SOI semiconductor layer, the stress relaxation which may typically occur during the patterning of trench isolation structures may be reduced by selecting an appropriate reduced target height of the active regions, thereby enabling the formation of transistor elements on the active region of reduced height, which may still include a significant amount of the initial strain component. The active regions of reduced height may be advantageously used for forming fully depleted field effect transistors.

Abstract: In accordance with one or more embodiments, a semiconductor structure includes a semiconductor substrate, a first semiconductor material over the semiconductor substrate, and a second semiconductor material over a portion the first semiconductor material, wherein the second semiconductor material comprises silicon-germanium-carbon (SiGeC) and wherein the first semiconductor material is a silicon epitaxial layer. The semiconductor structure further includes an active device, wherein a portion of the active device is formed in the second semiconductor material and a dielectric structure extending from the first surface of the first semiconductor material into the semiconductor substrate through the first semiconductor material.

Abstract: A semiconductor process and apparatus to provide a way to reduce plasma-induced damage by applying a patterned layer of photoresist (114) which includes resist openings formed (117) over the active circuit areas (13, 14) as well as additional resist openings (119) formed over inactive areas (15) in order to maintain the threshold coverage level to control the amount of resist coverage over a semiconductor structure so that the total amount of resist coverage is at or below a threshold coverage level. Where additional resist openings (119) are required in order to maintain the threshold coverage level, these openings may be used to create additional charge dissipation structures (e.g., 152) for use in manufacturing the final structure.

Abstract: The present invention provides a method for manufacturing a gallium nitride semiconductor epitaxial crystal substrate with a dielectric film which has a low gate leak current and negligibly low gate lag, drain lag, and current collapse characteristics. The method for manufacturing a semiconductor epitaxial crystal substrate is a method for manufacturing a semiconductor epitaxial crystal substrate in which a dielectric layer of a nitride dielectric material or an oxide dielectric material in an amorphous form functioning as a passivation film or a gate insulator is provided on a surface of a nitride semiconductor crystal layer grown by metal organic chemical vapor deposition. In the method, after the nitride semiconductor crystal layer is grown in an epitaxial growth chamber, the dielectric layer is grown on the nitride semiconductor crystal layer in the epitaxial growth chamber.

Abstract: A method for packaging solar cell module. The method includes providing a first substrate member and forming a plurality of thin film photovoltaic cells overlying the surface region of the first substrate member. A first connector member and a second connector member having a second thickness are operably coupled to each of the plurality of thin film photovoltaic cells. A first spacer element and a second spacer element overly portions of the surface region of the first substrate member. The method provides a laminating material overlying the plurality of thin film photovoltaic cells, the spacer elements, and the connector members. A second substrate member overlies the laminating material. A lamination process is performed to form the solar cell module by maintaining a spatial gap occupied by the laminating material between an upper surface regions of the connector members and the second substrate member using the spacer elements.

Abstract: A semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown over a porous III-nitride region. A III-nitride layer comprising InN is disposed between the light emitting layer and the porous III-nitride region. Since the III-nitride layer comprising InN is grown on the porous region, the III-nitride layer comprising InN may be at least partially relaxed, i.e. the III-nitride layer comprising InN may have an in-plane lattice constant larger than an in-plane lattice constant of a conventional GaN layer grown on sapphire.

Abstract: A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the silicon layer to form an amorphous silicon germanium layer. The silicon germanium layer is then oxidized to convert the silicon germanium layer into a silicon dioxide layer and to convert at least a portion of the silicon layer into germanium-rich silicon. The silicon dioxide layer is then removed prior to forming transistors using the germanium-rich silicon. In one embodiment, the germanium-rich silicon is selectively formed using a patterned masking layer over the silicon layer and under the silicon germanium layer. Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.

Abstract: The invention provides a method of fabricating and electromechanical device having an active element on at least one substrate, the method having the steps of: a) making a heterogeneous substrate having a first portion, an interface layer, and a second portion, the first portion including one or more buried zones sandwiched between first and second regions formed in a first monocrystalline material, the first region extending to the surface of the first portion, and the second region extending to the interface layer, at least one said buried zone being made at least in part out of a second monocrystalline material so as to make it selectively attackable relative to the first and second regions; b) making openings from the surface of the first portion and through the first region, which openings open out to at least one said buried zone; and c) etching at least part of at least one buried zone to form at least one cavity so as to define at least one active element that is at least a portion of the second regio

Abstract: The present invention relates to a Tunnel Field Effect Transistor (TFET), which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The TFET further includes a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.

Abstract: A semiconductor process and apparatus fabricate a metal gate electrode (30) and an integrated semiconductor resistor (32) by forming a metal-based layer (26) and semiconductor layer (28) over a gate dielectric layer (24) and then selectively implanting the resistor semiconductor layer (28) in a resistor area (97) to create a conductive upper region (46) and a conduction barrier (47), thereby confining current flow in the resistor semiconductor layer (36) to only the top region (46) in the finally formed device.

Abstract: A method for manufacturing a junction semiconductor device having a drain region including a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region including a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.

Abstract: A complementary BiCMOS semiconductor device comprises a substrate of a first conductivity type and a number of active regions which are provided therein and which are delimited in the lateral direction by shallow field insulation regions, in which vertical npn-bipolar transistors with an epitaxial base are arranged in a first subnumber of the active regions and vertical pnp-bipolar transistors with an epitaxial base are arranged in a second subnumber of the active regions, wherein either one transistor type or both transistor types have both a collector region and also a collector contact region in one and the same respective active region. To improve the high-frequency properties exclusively in a first transistor type in which the conductivity type of the substrate is identical to that of the collector region, an insulation doping region is provided between the collector region and the substrate.

Abstract: A semiconductor substrate is irradiated with accelerated hydrogen ions, thereby forming a damaged region including a large amount of hydrogen. After a single crystal semiconductor substrate and a supporting substrate are bonded to each other, the semiconductor substrate is heated, so that the single crystal semiconductor substrate is separated in the damaged region. A single crystal semiconductor layer which is separated from the single crystal semiconductor substrate is irradiated with a laser beam. The single crystal semiconductor layer is melted by laser beam irradiation, whereby the single crystal semiconductor layer is recrystallized to recover its crystallinity and to planarized a surface of the single crystal semiconductor layer. After the laser beam irradiation, the single crystal semiconductor layer is heated at a temperature at which the single crystal semiconductor layer is not melted, so that the lifetime of the single crystal semiconductor layer is improved.

Abstract: The present invention provides a semiconductor device formed over an insulating substrate, typically a semiconductor device having a structure in which mounting strength to a wiring board can be increased in an optical sensor, a solar battery, or a circuit using a TFT, and which can make it mount on a wiring board with high density, and further a method for manufacturing the same. According to the present invention, in a semiconductor device, a semiconductor element is formed on an insulating substrate, a concave portion is formed on a side face of the semiconductor device, and a conductive film electrically connected to the semiconductor element is formed in the concave portion.

Abstract: A method for manufacturing a semiconductor device includes steps of: forming a trench on a main surface of a silicon substrate; forming a first epitaxial film on the main surface and in the trench; and forming a second epitaxial film on the first epitaxial film. The step of forming the first epitaxial film has a first process condition with a first growth rate of the first epitaxial film. The step of forming the second epitaxial film has a second process condition with a second growth rate of the second epitaxial film. The second growth rate is larger than the first growth rate.

Abstract: The present invention relates to a method of treating a structure produced from semiconductor materials, wherein the structure includes a first and second substrates defining a common interface that has defects. The method includes forming a layer, called the disorganized layer, which includes the interface, in which at least a part of the crystal lattice is disorganized; and reorganizing the crystal lattice of the disorganized layer in order to force the defects back deeper into the first substrate.

Abstract: A method for producing a thin film promoter layer is disclosed. The method includes depositing a Group IV semiconductor ink on a substrate, the Group IV semiconductor ink including a set of Group IV semiconductor nanoparticles and a set of metal nanoparticles to form a porous compact. The method also includes heating the substrate to a first temperature between about 350° C. to about 765° C. and for a first time period between 5 min to about 3 hours.

Abstract: In a first aspect, a first method of forming an epitaxial film on a substrate is provided. The first method includes (a) providing a substrate; (b) exposing the substrate to at least a silicon source so as to form an epitaxial film on at least a portion of the substrate; and (c) exposing the substrate to HCl and Cl2 so as to etch the epitaxial film and any other films formed during step (b). Numerous other aspects are provided.

Abstract: A liquid injector is used to vaporize and inject a silicon precursor into a process chamber to form silicon-containing layers during a semiconductor fabrication process. The injector is connected to a source of silicon precursor, which preferably comprises liquid trisilane in a mixture with one or more dopant precursors. The mixture is metered as a liquid and delivered to the injector, where it is then vaporized and injected into the process chamber.