Abstract: Methods of manufacturing a semiconductor device include forming a gate insulation layer including a high-k dielectric material on a substrate that is divided into a first region and a second region; forming a diffusion barrier layer including a first metal on a second portion of the gate insulation layer in the second region; forming a diffusion layer on the gate insulation layer and the diffusion barrier layer; and diffusing an element of the diffusion layer into a first portion of the gate insulation layer in the first region.

Abstract: Disclosed is a method for forming a dual gate electrode of a semiconductor device, which may improve manufacturing productivity by simplifying a process of forming gate electrodes in PMOS and NMOS regions, respectively, and may provide improvement in performance by making the two gate electrodes have a different thickness and material state in a manner that one of the two gate electrodes has a single-layer structure and the other one has a two-layer structure.

Abstract: A gate in a semiconductor device is formed to have a dummy gate pattern that protects a gate. Metal lines are formed to supply power for a semiconductor device and transfer a signal. A semiconductor device includes a quad coupled receiver type input/output buffer. The semiconductor device is formed with a gate line that extends over an active region, and a gate pad located outside of the active region. The gate line and the gate pad are adjoined such that the gate line and a side of the gate pad form a line. Dummy gates may also be applied. The semiconductor device includes a first metal line patterns supplying power to a block having a plurality of cells, a second metal line pattern transferring a signal to the cells, and dummy metal line patterns divided into in a longitudinal direction.

Abstract: A method for fabricating an integrated device is disclosed. A polysilicon gate electrode layer is provided on a substrate. In an embodiment, a treatment is provided on the polysilicon gate electrode layer to introduce species in the gate electrode layer and form an electrically neutralized portion therein. Then, a hard mask layer with limited thickness is applied on the treated polysilicon gate electrode layer. A tilt angle ion implantation is thus performing on the substrate after patterning the hard mask layer and the treated polysilicon gate electrode to from a gate structure.

Abstract: Device isolation regions for isolating a device forming region are formed over a substrate. Subsequently, a gate insulation film is formed over the device forming region. Then, a lower gate electrode film comprised of a metal nitride film is formed over the gate insulation film. Further, a heat treatment is performed to the lower gate electrode film and then an upper gate electrode film is formed over the lower gate electrode film.

Abstract: In a replacement gate approach, the exposure of the placeholder material of the gate electrode structures may be accomplished on the basis of an etch process, thereby avoiding the introduction of process-related non-uniformities, which are typically associated with a complex polishing process for exposing the top surface of the placeholder material. In some illustrative embodiments, the placeholder material may be exposed by an etch process based on a sacrificial mask material.

Abstract: A layer-stacked wiring made up of a microcrystalline silicon thin film and a metal thin film is provided which is capable of suppressing an excessive silicide formation reaction between the microcrystalline silicon thin film and metal thin film, thereby preventing peeling of the thin film. In a polycrystalline silicon TFT (Thin Film Transistor) using the layer-stacked wiring, the microcrystalline silicon thin film is so configured that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 60% or more of a film thickness of the microcrystalline silicon thin film amount to 15% or less of total number of crystal grains or that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 50% or less of a film thickness of the microcrystalline silicon thin film amount to 85% or more of the total number of crystal grains making up the microcrystalline silicon thin film.

Abstract: Disclosed are a field effect transistor structure and a method of forming the structure. A gate stack is formed on the wafer above a designated channel region. Spacer material is deposited and anisotropically etched until just prior to exposing any horizontal surfaces of the wafer or gate stack, thereby leaving relatively thin horizontal portions of spacer material on the wafer surface and relatively thick vertical portions of spacer material on the gate sidewalls. The remaining spacer material is selectively and isotropically etched just until the horizontal portions of spacer material are completely removed, thereby leaving only the vertical portions of the spacer material on the gate sidewalls. This selective isotropic etch removes the horizontal portions of spacer material without damaging the wafer surface. Raised epitaxial source/drain regions can be formed on the undamaged wafer surface adjacent to the gate sidewall spacers in order to tailor source/drain resistance values.

Abstract: A semiconductor device and method for manufacturing a tensile strained NMOS and a compressive strained PMOS transistor pair, wherein a stressor material is sacrificial is disclosed. The method provides for a substrate, which includes a source/drain for an NMOS transistor, and a PMOS transistor. A first barrier layer is formed on the substrate and a first stressor material is formed on the first barrier layer. The first barrier layer is selectively removed from the PMOS transistor. The substrate is flash annealed and the remaining first stressor material and barrier layer is removed from the substrate.

Abstract: A semiconductor device manufacturing method which sequentially forms a gate oxide film and gate electrode material over a semiconductor layer of an SOI substrate and patterns the material into gate electrodes. The method further comprises the steps of forming sidewalls made of an insulator to cover side surfaces of the gate electrode; ion-implanting into the semiconductor layer on both sides of the gate electrode to form drain/source regions; partially etching the sidewalls to expose upper parts of the side surfaces of the gate electrode; depositing a metal film to cover the tops of the drain/source regions and of the gate electrode and the exposed upper parts of the side surfaces of the gate electrode; and performing heat treatment on the SOI substrate to form silicide layers respectively in the surfaces of the gate electrode and of the drain/source regions.

Abstract: A field effect transistor device and method which includes a semiconductor substrate, a dielectric gate layer, preferably a high dielectric constant gate layer, overlaying the semiconductor substrate and an electrically conductive oxygen barrier layer overlaying the gate dielectric layer. In one embodiment, there is a conductive layer between the gate dielectric layer and the oxygen barrier layer. In another embodiment, there is a low resistivity metal layer on the oxygen barrier layer.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a substrate. A dummy gate is formed over the substrate. A dielectric material is formed around the dummy gate. The dummy gate is then removed to form an opening in the dielectric material. Thereafter, a work function metal layer is formed to partially fill the opening. The remainder of the opening is then filled with a conductive layer using one of a polysilicon substitute method and a spin coating method.

Abstract: Disclosed is a semiconductor component arrangement and a method for producing a semiconductor component arrangement. The method comprises producing a trench transistor structure with at least one trench disposed in the semiconductor body and with at least an gate electrode disposed in the at least one trench. An electrode structure is disposed in at least one further trench and comprises at least one electrode. The at least one trench of the transistor structure and the at least one further trench are produced by common process steps. Furthermore, the at least one electrode of the electrode structure and the gate electrode are produced by common process steps.

Abstract: A method for forming a device is presented. A substrate prepared with a feature having first and second adjacent surfaces is provided. A device layer is formed on the first and second adjacent surfaces of the feature. A first portion of the device layer over the first adjacent surface includes nano-crystals, whereas a second portion of the device layer over the second adjacent surface is devoid of nano-crystals.

Abstract: The present disclosure provides various methods of fabricating a semiconductor device. A method of fabricating a semiconductor device includes providing a semiconductor substrate and forming a gate structure over the substrate. The gate structure includes a first spacer and a second spacer formed apart from the first spacer. The gate structure also includes a dummy gate formed between the first and second spacers. The method also includes removing a portion of the dummy gate from the gate structure thereby forming a partial trench. Additionally, the method includes removing a portion of the first spacer and a portion of the second spacer adjacent the partial trench thereby forming a widened portion of the partial trench. In addition, the method includes removing a remaining portion of the dummy gate from the gate structure thereby forming a full trench. A high k film and a metal gate are formed in the full trench.

Abstract: A gate electrode of one of an nFET and a pFET includes a metal-containing layer in contact with a gate insulating film and a first silicon-containing layer formed on the metal-containing layer, and a gate electrode of the other FET includes a second silicon-containing layer in contact with a gate insulating film and a third silicon-containing layer formed on the second silicon-containing layer. The first silicon-containing layer and the third silicon-containing layer are formed by the same silicon-containing material film.

Abstract: Provided is a method for manufacturing a MOS transistor.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, and a transistor formed in the substrate. The transistor has a gate structure that includes an interfacial layer formed on the substrate, a high-k dielectric layer formed on the interfacial layer, a capping layer formed on the high-k dielectric layer, the capping layer including a silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof, and a polysilicon layer formed on the capping layer.

Abstract: The method of manufacturing a semiconductor device comprises; forming an HfSiO film 36 on a silicon substrate 26; exposing the HfSiO film 36 to NH3 gas to thereby form an HfSiON film 38; forming an HfSiO film 40 on the HfSiON film 38; adhering Al to the surface of the HfSiO film 40 to thereby form an Al adhered layer 58 on the surface of the HfSiO film 40; and forming a polysilicon film 42 on the HfSiO film 40 with the Al adhered layer 58 formed on the surface.

Abstract: A semiconductor device able to secure electrical effective thicknesses required for insulating films of electronic circuit elements by using depletion of electrodes of the electronic circuit elements even if the physical thicknesses of the insulating films are not different, where gate electrodes of high withstand voltage use transistors to which high power source voltages are supplied contain an impurity at a relatively low concentration, so the gate electrodes are easily depleted at the time of application of the gate voltage; depletion of the gate electrodes is equivalent to increasing the thickness of the gate insulating films; the electrical effective thicknesses required of the gate insulating films can be made thicker; and the gate electrodes of high performance transistors for which a high speed and large drive current are required do not contain an impurity at a high concentration where depletion of the gate electrodes will not occur, so the electrical effective thickness of the gate insulating films

Abstract: The present invention relates to a method for processing semiconductor devices with a fine structure, and more particularly, to a processing method suitable for miniaturizing semiconductor devices with a so-called high-k/metal gate structure. In an embodiment of the present invention, a deposited film, which includes an insulating film made of Hf or Zr and a material of Mg, Y or Al existing on, under or in the insulating film, is formed on a Si substrate and is removed by repeating a dry etching process and a wet etching process at least one time. The wet etching process is performed prior to the dry etching process.

Abstract: A rework method of a gate insulating layer of a thin film transistor includes the following steps. First, a substrate including a silicon nitride layer, which serves as a gate insulating layer, disposed thereon. Subsequently, a first film removal process is performed to remove the silicon nitride layer. The first film removal process includes an inductively coupled plasma (ICP) etching process. The ICP etching process is carried out by introducing gases including sulfur hexafluoride and oxygen. The ICP etching process has an etching selectivity ratio of the silicon nitride layer to the substrate, which is substantially between 18 and 30.

Abstract: A method and structure to create damascene local interconnect during metal gate deposition. A method includes: forming a gate dielectric on an upper surface of a substrate; forming a mandrel on the gate dielectric; forming an interlevel dielectric (ILD) layer on a same level as the mandrel; forming a trench in the ILD layer; removing the mandrel; and forming a metal layer on the gate dielectric and in the trench.

Abstract: A method for fabricating a semiconductor device comprising a gate stack of a gate dielectric and a gate electrode, the method including forming a gate dielectric layer over a semiconductor substrate the gate dielectric layer being a metal oxide or semimetal oxide having a first electronegativity; forming a dielectric VT adjustment layer, the dielectric VT adjustment layer being a metal oxide or semimetal oxide having a second electronegativity; and forming a gate electrode over the gate dielectric layer and the VT adjustment layer; wherein the Effective Work Function of said gate stack is tuned to a desired value by tuning the thickness and composition of the dielectric VT adjustment layer and wherein the second electronegativity value is higher than both the first electronegativity value and the electronegativity of Al2O3

Abstract: A MOS transistor made in monolithic form, vias contacting the gate and the source and drain regions of the transistor being formed on the other side of the channel region with respect to the gate.

Abstract: A method of fabricating a semiconductor device according to one embodiment includes: forming a gate electrode by shaping a semiconductor film formed above a semiconductor substrate; forming a protective film on a side face of the gate electrode by plasma discharge of a first gas or a second gas, the first gas containing at least one of HBr, Cl2, CF4, SF6, and NF3 in addition to O2 and a flow rate of O2 therein being greater than 80% of the total of the entire flow rate, and the second gas containing at least one of HBr, Cl2, CF4, SF6, and NF3 in addition to O2 and N2 and a flow rate of sum of O2 and N2 therein being greater than 80% of the total of the entire flow rate; and removing a residue of the semiconductor film above the semiconductor substrate after forming the protective film.

Abstract: A gate of a transistor includes a gate oxide layer formed on a semiconductor device, a first conductive layer pattern including polysilicon doped with boron and formed on the gate oxide layer, a diffusion preventing layer pattern including amorphous silicon formed by a chemical vapor deposition process using a reaction gas having trisilane (Si3H8) and formed on the first conductive layer pattern, and a second conductive layer pattern including metal silicide and formed on the diffusion preventing layer pattern. Since a gate of PMOS transistor includes a diffusion preventing layer having an excellent surface morphology, diffusion of impurities is sufficiently prevented. Thus, the threshold voltage of PMOS transistor may be reduced and threshold voltage distribution may be improved.

Abstract: According to an aspect of an embodiment, a semiconductor device has a semiconductor substrate, a gate insulating film on the semiconductor substrate, a gate electrode formed on the gate insulating film, an impurity diffusion region formed in an area of the semiconductor substrate adjacent to the gate electrode to a first depth to the semiconductor substrate, the impurity diffusion region containing impurity, an inert substance containing region formed in the area of the semiconductor substrate to a second depth deeper than the first depth, the inert substance containing region containing an inert substance, and a diffusion suppressing region formed in the area of the semiconductor substrate to a third depth deeper than the second depth, the diffusion suppressing region containing a diffusion suppressing substance suppressing diffusion of the impurity.

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a metal-containing layer on the gate dielectric; and forming a composite layer over the metal-containing layer. The step of forming the composite layer includes forming an un-doped silicon layer substantially free from p-type and n-type impurities; and forming a silicon layer adjoining the un-doped silicon layer. The step of forming the silicon layer comprises in-situ doping a first impurity. (or need to be change to: forming a silicon layer first & then forming un-doped silicon layer) The method further includes performing an annealing to diffuse the first impurity in the silicon layer into the un-doped silicon layer.

Abstract: The present invention provides a method for making SONOS memory, comprising the following steps: depositing silicon oxide layer and silicon oxynitride layer in sequence on underlayer; coating a layer of photoresist on the silicon oxynitride layer; removing part of the photoresist and form the logic area; removing silicon oxynitride layer in the logic area; removing the bottom oxide layer in the logic area; growing top oxide layer on the silicon oxynitride layer and logic area; removing the top oxide layer in the logic area; growing gate oxide layer; forming device structure of SONOS and logic area. The present invention can avoid the damage of top oxide layer and lateral etching in wet etching so as to improve the defect-free rate of devices.

Abstract: A semiconductor device comprises a buried gate formed by being buried under a surface of a semiconductor substrate, a dummy gate formed on the buried gate, and a landing plug formed on a junction region of the semiconductor substrate being adjacent to the dummy gate.

Abstract: Substrate devices having tuned work functions and methods of forming thereof are provided. In some embodiments, forming devices on substrates may include depositing a dielectric layer atop a substrate having a conductivity well; depositing a work function layer comprising titanium aluminum or titanium aluminum nitride having a first nitrogen composition atop the dielectric layer; etching the work function layer to selectively remove at least a portion of the work function layer from atop the dielectric layer; depositing a layer comprising titanium aluminum or titanium aluminum nitride having a second nitrogen composition atop the work function layer and the substrate, wherein at least one of the work function layer or the layer comprises nitrogen; etching the layer and the dielectric layer to selectively remove a portion of the layer and the dielectric layer from atop the substrate; and annealing the substrate at a temperature less than about 1500 degrees Celsius.

Abstract: A method of fabricating a metal gate structure is provided. The method includes providing a semiconductor substrate with a planarized polysilicon material; patterned the planarized polysilicon material to form at least a first gate and a second gate, wherein the first gate is located on the active region and the second gate at least partially overlaps with the isolation region; forming an inter-layer dielectric material covering the gates; planarizing the inter-layer dielectric material until exposing the gates and forming an inter layer-dielectric layer; performing an etching process to remove the gates to form a first recess and a second recess within the inter-layer dielectric layer; forming a gate dielectric material on a surface of each of the recesses; forming at least a metal material within the recesses; and performing a planarization process.

Abstract: A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.

Abstract: Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a plurality of active regions which are defined in a semiconductor substrate, a plurality of gate lines which are formed as zigzag lines, extend across the active regions, are symmetrically arranged, and define a plurality of first regions and a plurality of second regions therebetween, and wherein the first regions being narrower than the second regions. The semiconductor device further includes an insulation layer which defines a plurality of contact regions by filling empty spaces in the first regions between the gate lines and, extending from the first regions, and surrounding sidewalls of portions of the gate lines in the second regions, and wherein the contact regions partially exposing the active regions and a plurality of contacts which respectively fill the contact regions.

Abstract: A semiconductor and a method for forming the same are disclosed. The method for forming the semiconductor device includes forming a buried gate on a semiconductor substrate including an active region, forming an insulating layer on the semiconductor substrate, selectively removing the insulating layer from at least an upper part of the active region, forming a bit line on an upper part between the buried gates formed on the active region, and forming a storage electrode contact that is formed at both sides of the bit line and has an extended lower part, so that prevents short circuiting between the storage electrode contact and the bit line, and improves contact resistance by enlarging a contact area between the storage electrode contact and the active region, so that unique characteristics of the semiconductor device are improved.

Abstract: A passivated semiconductor structure and associated method are disclosed. The structure includes a silicon carbide substrate or layer; an oxidation layer on the silicon carbide substrate for lowering the interface density between the silicon carbide substrate and the thermal oxidation layer; a first sputtered non-stoichiometric silicon nitride layer on the thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping; a second sputtered non-stoichiometric silicon nitride layer on the first layer for positioning subsequent passivation layers further from the substrate without encapsulating the structure; a sputtered stoichiometric silicon nitride layer on the second sputtered layer for encapsulating the structure and for enhancing the hydrogen barrier properties of the passivation layers; and a chemical vapor deposited environmental barrier layer of stoichiometric silicon nitride for step coverage and crack prevention on the encapsulant layer.

Abstract: A method of manufacturing a semiconductor device (1200), the method comprising forming a sacrificial pattern having a recess on a substrate (402), filling the recess and covering the substrate and the sacrificial pattern with a semiconductor structure, forming an annular trench in the semiconductor structure to expose a portion of the sacrificial pattern and to separate material (904) of the semiconductor structure enclosed by the annular trench from material (906) of the semiconductor structure surrounding the annular trench, removing the exposed sacrificial pattern to expose material of the semiconductor structure filling the recess, and converting the exposed material of the semiconductor structure filling the recess into electrically insulting material (1202).

Abstract: A method of doping p-type impurity ions in a dual poly gate, comprising: forming a polysilicon layer doped with n-type impurity ions on a substrate with a gate insulation layer being interposed between the polysilicon layer and the substrate; exposing a region of the polysilicon layer; implementing a first doping of p-type impurity ions into the exposed region of the polysilicon layer by ion implantation so with a projection range Rp to a predetermined depth of the polysilicon layer; and implementing a second doping of p-type impurity ions into the exposed region of the polysilicon layer doped with the p-type impurity ions by plasma doping with a sloped doping profile.

Abstract: Embodiments of a cascode amplifier (CA) include a bottom transistor with a relatively thin gate dielectric and higher ratio of channel length to width and a series coupled top transistor with a relatively thick gate dielectric and a lower ratio of channel length to width. A cascode current mirror (CCM) is formed using a coupled pair of CAs, one forming the reference current (RC) side and the other forming the mirror current side of the CCM. The gates of the bottom transistors are tied together and to the common node between the series coupled bottom and top transistors of the RC side, and the gates of the top transistors are coupled together and to the top drain node of the RC side. The area of the CCM can be substantially shrunk without adverse affect on the matching, noise performance and maximum allowable operating voltage.

Abstract: A method for fabricating a semiconductor device includes forming a gate insulation layer over a substrate, sequentially forming a silicon layer and a metal layer over the gate insulation layer, performing a first gate etching process to etch the metal layer using a gate hard mask layer, formed on the metal layer, as an etch barrier, and then partially etch the silicon layer, thereby forming a first pattern, performing a second gate etching process to partially etch the silicon layer, thereby forming an undercut beneath the metal layer, forming a capping layer on both sidewalls of the first pattern including the undercut, performing a third gate etching process to etch the silicon layer to expose the gate insulation layer using the gate hard mask layer and the capping layer as an etch barrier, thereby forming a second pattern, and performing a gate re-oxidation process.

Abstract: A method for fabricating a semiconductor device is provided. A first active region and a second active region are defined in a substrate. An electrode covering the first active region and the second active region is formed on the substrate. A first sacrificial layer is formed on the second active layer. A first work function electrode is formed on the first active layer by performing a first doping process to a portion of the electrode. The first sacrificial layer is removed. A second sacrificial layer is formed on the first active layer.

Abstract: A method of fabricating a semiconductor device is provided. The method of fabricating the semiconductor device comprises providing a substrate. Next, an insulating layer, a conductive layer and a silicide layer are formed on the substrate in sequence. Next, a hard masking layer is formed on the silicide layer exposing a portion of the silicide layer. A first etching step is performed to remove the silicide layer and the underlying conductive layer which are not covered by the hard masking layer, thereby forming a gate stack. And next, a second etching step is performed to remove any remaining conductive layer not covered by the hard masking layer after the first etching step. The second etching step is performed with an etchant comprising ammonium hydroxide.

Abstract: Embodiments of methods, apparatuses, devices, and/or systems for forming a thin film component are described.

Abstract: A method of manufacturing a metal compound thin film is disclosed. The method may include forming a first metal compound layer on a substrate by atomic layer deposition, performing annealing on the first metal compound layer in an atmosphere containing a nitrogen compound gas, thereby diffusing nitrogen into the first metal compound layer, and forming a second metal compound layer on the first metal compound layer by atomic layer deposition.

Abstract: A semiconductor device includes a transistor region, a first guard ring, a second guard ring, and a silicide region. A first-conductive-type transistor is formed in the transistor region. The first guard ring is a second-conductive-type first impurity diffusion layer surrounding the transistor region with a first width, and is coupled to a first reference potential. The second guard ring is a first-conductive-type transistor second impurity diffusion layer surrounding the first guard ring with a second width. The silicide region is formed on the surface of the second guard ring such that substantially no silicide is formed on a portion of the surface of the second guard ring on the side facing a drain region of the first-conductive-type transistor, and is connected to a second reference potential line whose potential is higher than that of the first reference potential line.

Abstract: A method of forming patterns of a semiconductor device comprises providing a semiconductor substrate comprising a first region wherein first patterns are to be formed and a second region wherein second patterns are to be formed, each of the second patterns having a wider width than the first patterns, forming an etch target layer over the semiconductor substrate, forming first etch patterns over the etch target layer of the first and second regions, forming second etch patterns on both sidewalls of each of the first etch patterns, wherein the second etch pattern formed in the second region has a wider width than the second etch pattern formed in the first region, removing the first etch patterns, forming third etch patterns over the etch target layer of the second region, the third etch pattern overlapping part of the second pattern, and etching the etch target layer using the third etch patterns and the second etch patterns as an etch mask, to form the first and second patterns.

Abstract: A method and apparatus are described for fabricating single metal gate electrodes (35, 36) over a high-k gate dielectric layer (31, 32) that is separately doped in the PMOS and NMOS device areas (96, 97) by forming first capping oxide layer (23) with a first dopant species on a high-k gate dielectric layer (22) in at least the NMOS device area and also forming second capping oxide layer (27) with a second dopant species on a high-k gate dielectric layer (22) in at least the PMOS device area, where the first and second dopant species are diffused into the gate dielectric layer (22) to form a first fixed charge layer (31) in the PMOS device area of the high-k gate dielectric area and a second fixed charge layer (32) in the NMOS device area of the high-k gate dielectric area.

Abstract: A method of patterning a plurality of polysilicon structures includes forming a polysilicon layer over a semiconductor body, and patterning the polysilicon layer to form a first polysilicon structure using a first patterning process that reduces line-edge roughness (LER). The method further includes patterning the polysilicon layer to form a second polysilicon structure using a second patterning process that is different from the first patterning process after performing the first patterning process.