Schottky Gate Structure (epo) Patents (Class 257/E21.186)
  • Patent number: 8987124
    Abstract: A silicon carbide substrate having a main face is prepared. By applying thermal oxidation to the main face of the silicon carbide substrate at a first temperature, an oxide film is formed on the main face. After the oxide film is formed, heat treatment is applied to the silicon carbide substrate at a second temperature higher than the first temperature. An opening exposing a portion of the main face is formed at the oxide film. A Schottky electrode is formed on the main face exposed by the opening.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: March 24, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tomihito Miyazaki, Toru Hiyoshi
  • Publication number: 20130234278
    Abstract: The present disclosure relates to a Schottky contact for a semiconductor device. The semiconductor device has a body formed from one or more epitaxial layers, which reside over a substrate. The Schottky contact may include a Schottky layer, a first diffusion barrier layer, and a third layer. The Schottky layer is formed of a first metal and is provided over at least a portion of a first surface of the body. The first diffusion barrier layer is formed of a silicide of the first metal and is provided over the Schottky layer. The third layer is formed of a second metal and is provided over the first diffusion barrier layer. In one embodiment, the first metal is nickel, and as such, the silicide is nickel silicide. Various other layers may be provided between or above the Schottky layer, the first diffusion barrier layer, and the third layer.
    Type: Application
    Filed: March 7, 2012
    Publication date: September 12, 2013
    Applicant: CREE, INC.
    Inventors: Helmut Hagleitner, Saptharishi Sriram
  • Publication number: 20130149850
    Abstract: A method for manufacturing a semiconductor device includes the steps of preparing a substrate made of silicon carbide and having an n type region formed to include a main surface, forming a p type region in a region including the main surface, forming an oxide film on the main surface across the n type region and the p type region, by heating the substrate having the p type region formed therein at a temperature of 1250° C. or more, removing the oxide film to expose at least a part of the main surface, and forming a Schottky electrode in contact with the main surface that has been exposed by removing the oxide film.
    Type: Application
    Filed: November 6, 2012
    Publication date: June 13, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventor: Sumitomo Electric Industries, Ltd.
  • Patent number: 8183103
    Abstract: A method for manufacturing an integrated circuit structure is disclosed. First, a dielectric layer is formed on a substrate, the substrate has a transistor region and a diode region. Next, a contact hole and an opening are formed in the dielectric layer, a size of the opening being larger than that of the contact hole. Next, a first metal layer is formed on the dielectric layer and filled into the contact hole and the opening. Next, a portion of the first metal layer is removed to form a contact plug above the transistor region and form a metal spacer on a sidewall of the opening. Next, an ion implantation process is performed to form a lightly doped region in the substrate at a bottom of the opening. Finally, a contact metal layer is formed on the lightly doped region.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: May 22, 2012
    Assignee: United Microelectronics Corp.
    Inventor: Yan-Hsiu Liu
  • Patent number: 8183558
    Abstract: A compound semiconductor device includes a compound semiconductor substrate; epitaxially grown layers formed over the compound semiconductor substrate and including a channel layer and a resistance lowering cap layer above the channel layer; source and drain electrodes in ohmic contact with the channel layer; recess formed by removing the cap layer between the source and drain electrodes; a first insulating film formed on an upper surface of the cap layer and having side edges at positions retracted from edges, or at same positions as the edges of the cap layer in a direction of departing from the recess; a second insulating film having gate electrode opening and formed covering a semiconductor surface in the recess and the first insulating film; and a gate electrode formed on the recess via the gate electrode opening.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: May 22, 2012
    Assignee: Fujitsu Limited
    Inventors: Kozo Makiyama, Tsuyoshi Takahashi
  • Patent number: 8174048
    Abstract: A III-nitride device includes a recessed electrode to produce a nominally off, or an enhancement mode, device. By providing a recessed electrode, a conduction channel formed at the interface of two III-nitride materials is interrupted when the electrode contact is inactive to prevent current flow in the device. The electrode can be a schottky contact or an insulated metal contact. Two ohmic contacts can be provided to form a rectifier device with nominally off characteristics. The recesses formed with the electrode can have sloped sides. The electrode can be formed in a number of geometries in conjunction with current carrying electrodes of the device. A nominally on device, or pinch resistor, is formed when the electrode is not recessed. A diode is also formed by providing non-recessed ohmic and schottky contacts through an insulator to an AlGaN layer.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: May 8, 2012
    Assignee: International Rectifier Corporation
    Inventor: Robert Beach
  • Patent number: 7943994
    Abstract: The present invention discloses an integrated PMOS transistor and Schottky diode, comprising a PMOS transistor which includes a gate, a source, a drain and a channel region between the source and drain, wherein the source, drain and channel region are formed in a substrate, and a parasitic diode is formed between the drain and the channel region; and a Schottky diode formed in the substrate and connected in reverse series with the parasitic diode, the Schottky diode having one end connected with the parasitic diode and the other end connected with the source.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: May 17, 2011
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventor: Chih-Feng Huang
  • Patent number: 7928480
    Abstract: A semiconductor device has a semiconductor layer, and a first electrode (Schottky electrode or MIS electrode) and a second electrode (ohmic electrode) which are formed on the semiconductor layer apart from each other. The first electrode has a cross section in the shape of a polygon. A second electrode-side corner of the polygon has an interior angle of which an outward extension line of a bisector crosses the semiconductor layer or the second electrode. The interior angle of such a second electrode-side corner is larger than 90°.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: April 19, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masaharu Yamashita, John Kevin Twynam
  • Patent number: 7915713
    Abstract: An integrated circuit includes a first field effect transistor of a first carrier type and a second field effect transistor of a second, different carrier type. In a conductive state, a first channel of the first field effect transistor is oriented to one of a first set of equivalent crystal planes of a semiconductor substrate and a second channel of the second field effect transistor is oriented to at least one of a second, different set of equivalent crystal planes. The first set of equivalent crystal planes is parallel to a main surface of the semiconductor substrate and the second set of equivalent crystal planes is perpendicular to the main surface.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: March 29, 2011
    Assignee: Qimonda AG
    Inventors: Juergen Faul, Juergen Holz
  • Patent number: 7906417
    Abstract: A method for manufacturing a compound semiconductor device forms an EB resist layer on first SiN film, performs EB exposure at high dose for recess forming opening and at low dose for eaves removing opening, develops the high dose EB resist pattern to etch the first SiN film, selectively etches the cap layer to form a recess wider than the opening of the first SiN film leaving eaves of SiN, develops the low dose EB resist pattern to form the eaves removing opening, etches the first SiN film to extinguish the eaves, forms second SiN film on the exposed surface, forms a resist pattern having a gate electrode opening on the second SiN film to etch the second SiN film, forms a metal layer to form a gate electrode by lift-off. The SiN film in eaves shape will not be left.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: March 15, 2011
    Assignee: Fujitsu Limited
    Inventors: Kozo Makiyama, Tsuyoshi Takahashi
  • Publication number: 20100216301
    Abstract: In one aspect, a method includes forming a silicon dioxide layer on a surface of a diamond layer disposed on a gallium nitride (GaN)-type layer. The method also includes etching the silicon dioxide layer to form a pattern. The method further includes etching portions of the diamond exposed by the pattern.
    Type: Application
    Filed: February 23, 2009
    Publication date: August 26, 2010
    Inventors: MARY Y. CHEN, Peter W. Deelman
  • Publication number: 20100117186
    Abstract: The invention provides a semiconductor device and a method for fabricating the same capable of preventing a field plate portion from being delaminated from an insulating film by stress inherent in a semiconductor layer even if the stress is released in forming a trench in part of the semiconductor layer where the semiconductor device is to be separated and capable of having a higher breakdown property of the semiconductor device. The semiconductor device has source, drain and gate electrodes, insulating films that insulate the electrodes on an electron supplying layer and a mesa-structure formed at part where the semiconductor device is to be separated. The gate electrode has a first electrode layer having a function of the electrode and a second electrode layer having a field plate portion whose part that contacts with the insulating film is made of a metallic material that adheres well to the insulating film.
    Type: Application
    Filed: June 24, 2009
    Publication date: May 13, 2010
    Inventors: Hiroshi Kambayashi, Shusuke Kaya, Nariaki Ikeda
  • Patent number: 7692222
    Abstract: A semiconductor structure and method wherein a recess is disposed in a surface portion of a semiconductor structure and a dielectric film is disposed on and in contract with the semiconductor. The dielectric film has an aperture therein. Portions of the dielectric film are disposed adjacent to the aperture and overhang underlying portions of the recess. An electric contact has first portions thereof disposed on said adjacent portions of the dielectric film, second portions disposed on said underlying portions of the recess, with portions of the dielectric film being disposed between said first portion of the electric contact and the second portions of the electric contact, and third portions of the electric contact being disposed on and in contact with a bottom portion of the recess in the semiconductor structure. The electric contact is formed by atomic layer deposition of an electrically conductive material over the dielectric film and through the aperture in such dielectric film.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: April 6, 2010
    Assignee: Raytheon Company
    Inventors: Kamal Tabatabaie, Robert B. Hallock
  • Patent number: 7586150
    Abstract: A method of manufacturing a local recess channel transistor in a semiconductor device. A hard mask layer is formed on a semiconductor substrate that exposes a portion of the substrate. The exposed portion of the substrate is etched using the hard mask layer as an etch mask to form a recess trench. A trench spacer is formed on the substrate along a portion of sidewalls of the recess trench. The substrate along a lower portion of the recess trench is exposed after the trench spacer is formed. The exposed portion of the substrate along the lower portion of the recess trench is doped with a channel impurity to form a local channel impurity doped region surrounding the lower portion of the recess trench. A portion of the local channel impurity doped region surrounding the lower portion of the recess trench is doped with a Vth adjusting impurity to form a Vth adjusting impurity doped region inside the local channel impurity doped region. The width of the lower portion of the recess trench is expanded.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: September 8, 2009
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Se-myeong Jang, Yong-chul Oh, Makoto Yoshida
  • Patent number: 7544593
    Abstract: Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: June 9, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshitaka Tsunashima, Seiji Ihumiya, Yasumasa Suizu, Yoshio Ozawa, Kiyotaka Miyano, Masayuki Tanaka
  • Publication number: 20090111253
    Abstract: Methods of fabricating compound semiconductor devices are described.
    Type: Application
    Filed: October 31, 2007
    Publication date: April 30, 2009
    Inventors: Nathan Ray Perkins, Timothy Arthur Valade, Albert William Wang
  • Publication number: 20080220599
    Abstract: A method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices, particularly for integrated HBT/HEMT devices on a common substrate is disclosed. The method is based on dual-resist processes, wherein a first thin photo-resist layer is utilized for defining the gate dimension, while a second thicker photo-resist layer is used to obtain a better coverage on the surface for facilitating gate metal lift-off. The dual-resist method not only reduces the final gate length, but also mitigates the gate recess undercuts, as compared with those fabricated by the conventional single-resist processes. Furthermore, the dual-resist method of the present invention is also beneficial for the fabrication of multi-gate device with good gate-length uniformity.
    Type: Application
    Filed: May 15, 2008
    Publication date: September 11, 2008
    Applicant: WIN Semiconductors Corp.
    Inventors: Cheng-Kuo Lin, Chia-Liang Chao, Ming-Chang Tu, Tsung-Chi Tsai, Yu-Chi Wang
  • Publication number: 20080188066
    Abstract: A method for fabricating a semiconductor device includes: forming a dummy gate that defines a region in which a gate electrode should be formed on a semiconductor substrate; forming a surface film on the semiconductor substrate by directional sputtering vertical to a surface of the semiconductor substrate, the directional sputtering being one of collimate sputtering, long throw sputtering and ion beam sputtering; removing the surface film formed along a sidewall of the dummy gate; removing the dummy gate; and forming the gate electrode in the region from which the dummy gate on the semiconductor substrate has been removed.
    Type: Application
    Filed: February 7, 2008
    Publication date: August 7, 2008
    Applicant: EUDYNA DEVICES INC.
    Inventors: Masataka WATANABE, Hiroshi YANO
  • Publication number: 20080006853
    Abstract: The present invention provides a Schottky electrode for a nitride semiconductor device having a high barrier height, a low leak current performance and a low resistance and being thermally stable, and a process for production thereof. The Schottky electrode for a nitride semiconductor has a layered structure that comprises a copper (Cu) layer being in contact with the nitride semiconductor and a first electrode material layer formed on the copper (Cu) layer as an upper layer. As the first electrode material, a metal material which has a thermal expansion coefficient smaller than the thermal expansion coefficient of copper (Cu) and starts to undergo a solid phase reaction with copper (Cu) at a temperature of 400° C. or higher is employed.
    Type: Application
    Filed: July 8, 2005
    Publication date: January 10, 2008
    Applicant: NEC CORPORATION
    Inventors: Hironobu Miyamoto, Tatsuo Nakayama, Yuji Ando, Yasuhiro Okamoto, Masaaki Kuzuhara, Takashi Inoue, Koji Hataya