Abstract: In one aspect, a method of a neuron circuit includes the step of providing a plurality of 2N?1 single-level-cell (SLC) flash cells for each synapse (Yi) connected to a bit line forming a neuron. The method includes the step of providing an input vector (Xi) for each synapse Yi wherein each input vector is translated into an equivalent electrical signal ESi (current IDACi, pulse, TPULSEi, etc). The method includes the step of providing an input current to each synapse sub-circuit varying from 20*ESi to (2N?1)*ESi. The method includes the step of providing a set of weight vectors or synapse (Yi), wherein each weight vector is translated into an equivalent threshold voltage level or resistance level to be stored in one of many non-volatile memory cells assigned to each synapse (Yi).

Abstract: A semiconductor device is described. The semiconductor device includes a substrate and a metal layer disposed on the substrate. A seed layer is formed on the metal layer. A ferroelectric gate layer is formed on the seed layer. A channel layer is formed over the ferroelectric gate layer. The seed layer is arranged to increase the orthorhombic phase fraction of the ferroelectric gate layer.

Abstract: A semiconductor device includes a substrate having a first region and a second region, insulating patterns in the substrate in the second region that define active patterns of the substrate, gate electrodes spaced apart from each other and stacked on an upper surface of the substrate and extending in a first direction, first separation regions extending in the first direction and in contact with the active patterns, second separation regions extending between the first separation regions in the first direction, and channel structures penetrating through the gate electrodes in the first region. At least one of the second separation regions is in contact with the substrate below the insulating patterns.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.

Abstract: An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.

Abstract: The present disclosure relates to memory devices, in particular, flash memory devices, storage class memory (SCM) devices or dynamic random access memory (DRAM) devices. The disclosure provides a memory device with a ferroelectric trapping layer. In particular, a memory cell for the memory device comprises a layer stack including: a semiconductor layer; a tunnel layer provided directly on the semiconductor layer; a ferroelectric trapping layer provided directly on the tunnel layer; and a conductive gate layer provided directly on the ferroelectric trapping layer. A blocking layer between the ferroelectric trapping layer and the gate layer may be omitted.

Abstract: A method of making a spot size converter comprising a multi-tip waveguide comprising a first and a second waveguide portions, the method comprising the steps of: coating a multilayer wafer comprising a waveguide material layer with a resist material; exposing the coated resist material to a deep UV beam or an electron beam; developing resist material to form an partial waveguide pattern within the resist material; transferring the partial waveguide pattern to the waveguide material layer, forming an initial waveguide; placing a second layer of resist material over the initial waveguide; patterning a tapered gap region shape in the second layer of resist material by exposing the second layer of resist material to a deep UV beam or an electron beam; and transferring the tapered gap region shape to the waveguide material layer of the initial waveguide to form a tapered gap region inside the initial waveguide.

Abstract: A CVD preparation method for minimizing camera module dot defects includes: performing ultrasonic cleaning and drying on a base substrate to obtain a pre-treated base substrate; placing the pre-treated base substrate into a reaction chamber, evacuating, and introducing nitrogen or inert gas to slightly positive pressure; simultaneously introducing precursor I and precursor II at a temperature of 500-700° C. to deposit a low-refractive-index L layer on the base substrate; halting introduction of the precursor I and the precursor II, and purging the reaction chamber with nitrogen or the inert gas; introducing raw gas precursor III and precursor IV at a temperature of 600-800° C. to deposit a high-refractive-index H layer on the low-refractive-index L layer; and halting introduction of the precursor III and precursor IV, and purging the reaction chamber with nitrogen or inert gas; and cooling to room temperature to obtain an optical element with coating films having different refractive indices.

Abstract: A memory array and a structure of the memory array are provided. The memory array includes flash transistors, word lines and bit lines. The flash transistors are arranged in columns and rows. The flash transistors in each column are in serial connection with one another. The word lines are respectively coupled to gate terminals of a row of the flash transistors. The bit lines are respectively coupled to opposite ends of a column of the flash transistors. Band-to-band tunneling current at a selected flash transistor is utilized as read current during a read operation. The BTB tunneling current flows from one of the source/drain terminals of the selected flash transistor to the substrate, rather than flowing from one of the source/drain terminals to the other. As a result, charges stored in multiple programming sites of each flash transistor can be respectively sensed.

Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes: providing a first wafer including a substrate; forming a hole in the first wafer, which extends through the substrate; forming an insulating dielectric layer over a side wall of the hole; filling the hole with a conductive layer; removing at least part of the insulating dielectric layer situated in correspondence with the substrate, forming an air gap between the conductive layer and the substrate; and forming a closure layer, which closes the air gap. With the present invention, parasitic capacitance present between the conductive layer, the insulating dielectric layer and the substrate is significantly reduced, resulting in an improvement in performance of the semiconductor device.

Abstract: An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.

Abstract: Some embodiments include a memory cell having a conductive gate comprising ruthenium. A charge-blocking region is adjacent the conductive gate, a charge-storage region is adjacent the charge-blocking region, a tunneling material is adjacent the charge-storage region, and a channel material is adjacent the tunneling material. Some embodiments include an assembly having a vertical stack of alternating insulative levels and wordline levels. The wordline levels contain conductive wordline material which includes ruthenium. Semiconductor material extends through the stack as a channel structure. Charge-storage regions are between the conductive wordline material and the channel structure. Charge-blocking regions are between the charge-storage regions and the conductive wordline material. Some embodiments include methods of forming integrated assemblies.

Abstract: A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity region, and the second impurity region are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer.

Abstract: In one embodiment, memory cell includes a control gate, a floating gate, a substrate comprising a source region and a drain region, a first isolator between the control gate and floating gate, and a second isolator between the floating gate and the substrate. The memory cell is configured to have a retention time that is within a statistical window around a selected lifespan. The selected lifespan may be less than ten years, such as, for example, less than one year, less than one month, or less than one week.

Abstract: A method of a flash memory controller includes: providing an input/output (I/O) circuit coupled to the flash memory device; and sending a data toggle set-feature signal to the flash memory device to enable, disable, or configure a data toggle operation of the flash memory device; the data toggle operation of the flash memory device is arranged to make the flash memory device control the flash memory device's data register selecting and transferring a first data unit and a second data unit to the flash memory device's I/O control circuit to make the I/O control circuit sequentially transmit the first data unit and the second data unit to the flash memory controller through the specific communication interface in response to a specific read command or a data toggle command transmitted by the flash memory controller.

Abstract: A device includes a semiconductor substrate; a word line extending over the semiconductor substrate; a memory film extending along the word line, wherein the memory film contacts the word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; source lines extending along the memory film, wherein the memory film is between the source lines and the word line; bit lines extending along the memory film, wherein the memory film is between the bit lines and the word line; and isolation regions, wherein each isolation region is between a source line and a bit line, wherein each of the isolation regions includes an air gap and a seal extending over the air gap.

Abstract: Various implementations described herein are related to a device having multiple transistors that are arranged as a bitcell. The device may include multiple wordlines that are coupled to the multiple transistors. Also, one or more wordlines may be formed with frontside metal, and one or more other wordlines may be formed with buried metal.

Abstract: A memory structure and a manufacturing method for the same are provided. The memory structure includes a charge trapping layer, a first silicon oxynitride tunneling film and a second silicon oxynitride tunneling film. The first silicon oxynitride tunneling film is between the charge trapping layer and the second silicon oxynitride tunneling film. A first atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the first silicon oxynitride tunneling film is 10% to 50%. A second atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the second silicon oxynitride tunneling film is 1% to 15%. The concentration of the nitrogen atom of the second silicon oxynitride tunneling film is lower than that of the first silicon oxynitride tunneling film.

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

Abstract: A memory cell of a non-volatile memory includes a memory element. The memory element is a transistor. The memory element includes an asymmetric spacer. In the memory element, a channel under the wider part of the spacer is longer. When the program operation of the memory element is performed, more carriers are injected into a charge-trapping layer of the spacer through the longer channel. Consequently, the program operation of the memory element is performed more efficiently, and the time period of performing the program operation is reduced.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.

Abstract: An alternating stack of insulating layers and electrically conductive layers, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, and memory stack structures extending through the alternating stack are formed over a substrate. A patterned etch mask layer including discrete openings is formed thereabove. Via cavities through an upper region of the retro-stepped dielectric material portion by performing a first anisotropic etch process. Metal plates are selectively formed on physically exposed surfaces of a first subset of the electrically conductive layers by a selective metal deposition process. A subset of the via cavities without any metal plates therein are vertically extended downward by performing a second anisotropic etch process while the metal plates protect underlying electrically conductive layers. Via cavities can be formed without punching through electrically conductive layers.

Abstract: A NAND flash memory capable of reducing the planar size of a memory cell is provided. The three-dimensional NAND flash memory includes a substrate, an insulating layer, a lower conductive layer (a source), a three-dimensional memory cell structure, and a bit line. The memory cell structure includes a plurality of strip-shaped gate stacks including stacks of insulators and conductors stacked along a vertical direction from the substrate; and a plurality of channel stacks separately arranged along one side of the gate stack. An upper end of the channel stack is electrically connected to the orthogonal bit line, and a lower end of the channel stack is electrically connected to the lower conductive layer.

Abstract: A phase change memory device based on a nano current channel is provided. A nano current channel layer structure is adopted and configured to limit the current channel. As such, when flowing through the layer, the current enters the phase change layer from nano crystal grains with high electrical conductivity, and the current is thereby confined in the nano current channels. By using the nano-scale conductive channels, the contact area between the phase change layer and the electrode layer is significantly decreased, the current density at local contact channel is significantly increased, and heat generation efficiency of the current in the phase change layer is improved. Moreover, an electrically insulating and heat-insulating material with low electrical conductivity and low thermal conductivity prevents heat in the phase change layer from being dissipated to the electrode layer, and Joule heat utilization efficiency of the phase change layer is thereby improved.

Abstract: A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer.

Abstract: A display device according to an embodiment includes: a first conductive layer that is disposed on a substrate; a transistor that is disposed on the substrate; and a light emitting element that is electrically connected to the transistor, wherein the transistor includes a semiconductor layer that at least partially overlaps the first conductive layer and is disposed on the first conductive layer, and a gate electrode that is disposed on the semiconductor layer. The semiconductor layer includes a first region that does not overlap the first conductive layer, a third region that overlaps the first conductive layer, and a second region that is disposed between the first region and the third region and traverses an edge of the first conductive layer. The first width of the semiconductor layer in the first region is smaller than a second width of the semiconductor layer in the second region.

Abstract: A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes first and second stacking structures, isolation pillars, gate dielectric layers, channel layers and conductive pillars. The stacking structures are laterally spaced apart from each other. The stacking structures respectively comprises alternately stacked insulating layers and conductive layers. The isolation pillars laterally extend between the stacking structures. The isolation pillars further protrude into the stacking structures, and a space between the stacking structures is divided into cell regions. The gate dielectric layers are respectively formed in one of the cell regions, and cover opposing sidewalls of the stacking structures and sidewalls of the isolation pillars. The channel layers respectively cover an inner surface of one of the gate dielectric layers.

Abstract: A thin-film memory transistor includes a source region, a drain region, a channel region, a gate electrode, and a charge-trapping layer provided between the channel region and the gate electrode and electrically isolated therefrom, wherein the charge-trapping layer has includes a number of charge-trapping sites that is 70% occupied or evacuated using a single voltage pulse of a predetermined width of 500 nanoseconds or less and a magnitude of 15.0 volts or less. The charge-trapping layer comprises silicon-rich nitride may have a refractive index of 2.05 or greater or comprises nano-crystals of germanium (Ge), zirconium oxide (ZrO2), or zinc oxide (ZnO). The thin-film memory transistor may be implemented, for example, in a 3-dimensional array of NOR memory strings formed above a planar surface of a semiconductor substrate.

Abstract: Device, systems, and structures include a stack of vertically-alternating tiers of materials arranged in one or more decks of tiers. A channel opening, in which a channel pillar may be formed, extends through the stack. The pillar includes a “shoulder portion” extending laterally into an “undercut portion” of the channel opening, which undercut portion is defined along at least a lower tier of at least one of the decks of the stack.

Abstract: A method for forming a memory device is provided. The memory device includes a substrate; a stack including a plurality of conductive layers and a plurality of insulating layers being alternatively stacked on the substrate; a plurality of memory structures formed on the substrate and penetrating the stack; a plurality of isolation structures formed on the substrate and penetrating the stack, wherein the isolation structures dividing the memory structures into a plurality of first memory structures and a plurality of second memory structures; and a plurality of common source pillars formed on the substrate and penetrating the stack, wherein the common source pillars directly contact the isolation structures.

Abstract: Electronic devices and methods of forming the electronic devices are described. The electronic devices comprise a plurality of memory holes extending along a first direction through a plurality of alternating oxide and nitride layers. Each memory hole has a core oxide surrounded by a semiconductor material, the semiconductor material surrounded by a dielectric. The memory holes are staggered to provide a plurality of memory hole lines having spaced memory holes so that adjacent memory hole lines have the memory holes in a staggered configuration. A conductive material is on top of the stack of alternating oxide and nitride layers. A dielectric filled cut line extends through the conductive material in a direction across the plurality of memory hole lines. The dielectric filled cut line separates a first memory hole line from an adjacent second memory hole line without disabling the functionality of the memory holes.

Abstract: According to one embodiment, a semiconductor storage device includes a first memory cell, a second memory cell, a first transistor, a second transistor, and a third transistor. The first transistor includes a first portion electrically connected to a first circuit, a second portion electrically connected to the first memory cell, and a first gate electrode installed between the first portion and the second portion. The second transistor includes a third portion electrically connected to the first circuit, a fourth portion electrically connected to the second memory cell, and a first gate electrode installed between the third portion and the fourth portion. The third transistor includes the second portion, the fourth portion, a fifth portion electrically connected to a second circuit, and a second gate electrode installed between the second portion and the fifth portion and between the fourth portion and the fifth portion.

Abstract: A semiconductor device includes a lower structure; a stack structure including gate layers and interlayer insulating layers and having an opening; a vertical structure in the opening; a contact structure on the vertical structure; and a conductive line on the contact structure. The vertical structure includes an insulating core region, a channel semiconductor layer covering side and lower surfaces of the insulating core region, data storage patterns between the channel semiconductor layer and the gate layers and spaced apart from each other, a first dielectric layer, and a second dielectric layer. At least a portion of the first dielectric layer is between the data storage patterns and the gate layers, at least a portion of the second dielectric layer is between the data storage patterns and the channel semiconductor layer, and the insulating core region includes first convex portions having increased widths in regions facing the gate layers.

Abstract: Device, systems, and structures include a stack of vertically-alternating tiers of materials arranged in one or more decks of tiers. A channel opening, in which a channel pillar may be formed, extends through the stack. The pillar includes a “shoulder portion” extending laterally into an “undercut portion” of the channel opening, which undercut portion is defined along at least a lower tier of at least one of the decks of the stack.

Abstract: Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The method comprises: forming a recess region in a substrate including multiple protruding islands; forming a gate dielectric layer to cover top surfaces and sidewalls of the multiple protruding islands and a top surface of the recess region of the substrate; forming an underlying sacrificial layer on the gate dielectric layer to surround the sidewalls of the multiple protruding islands; forming an alternating dielectric stack including multiple alternatively stacked insulating layers and sacrificial layers on the underlying sacrificial layer and the multiple protruding islands; forming multiple channel holes penetrating the alternating dielectric stack, each channel hole is located corresponding to one of the multiple protruding islands; and forming a memory layer in each channel hole, wherein a channel layer of the memory layer is electrically connected with a corresponding protruding island.

Abstract: In a method of fabricating a nonvolatile memory device according an embodiment, a first tunnel oxide layer, a nitrogen supply layer, and a second tunnel oxide layer having a density lower than that of the first tunnel oxide layer are formed on a substrate. Nitrogen in the nitrogen supply layer is diffused into the second tunnel oxide layer to convert at least a portion of the second tunnel oxide layer into an oxynitride layer.

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

Abstract: A memory device includes a stack structure, a memory element, a channel element, and a semiconductor layer. The stack structure includes a source layer, an insulating layer and gate electrode layers. The insulating layer is on the source layer. The gate electrode layers are on the insulating layer. The memory element is on electrode sidewall surfaces of the gate electrode layers. Memory cells are defined in the memory element between the channel element and the gate electrode layers. The semiconductor layer is electrically connected between the source layer and the channel element. The semiconductor layer and the source layer have an interface therebetween. The interface is at a location on an inside of an insulating sidewall surface of the insulating layer with a lateral offset relative to the insulating sidewall surface.

Abstract: A memory device and an operation method thereof are provided. The memory device includes a semiconductor substrate and an oxide-nitride-oxide (ONO) gate structure located on the semiconductor substrate. The ONO gate structure includes a bottom oxide layer, a top oxide layer and a nitride layer. The nitride layer is located between the bottom oxide layer and the top oxide layer. The bottom oxide layer is located closer to the semiconductor substrate than the top oxide layer. The bottom oxide layer has a first thickness, and the top oxide layer has a second thickness smaller the first thickness. The operation method includes an erasing operation and a programming operation. Electrons are attracted into the ONO gate structure through the bottom oxide layer in the programming operation. Electrons trapped in the ONO gate structure escape from the ONO gate structure through the top oxide layer.

Abstract: Disclosed are data storage devices and methods of manufacturing the same. The methods may include providing a substrate including a cell region and a peripheral circuit region, forming a data storage layer on the cell region and the peripheral circuit region of the substrate, selectively forming a mask layer on a portion of the data storage layer that is formed on the peripheral circuit region, forming a top electrode layer on the data storage layer and the mask layer, patterning the top electrode layer to form a plurality of top electrodes on the cell region, and patterning the data storage layer using the plurality of top electrodes as an etch mask to form a plurality of data storage parts on the cell region. While patterning the top electrode layer, the mask layer on the peripheral circuit region may serve as an etch stop layer.

Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.

Abstract: A memory device includes a semiconductor substrate having a cell region and a peripheral region surrounding the cell region and a pair of control gate stacks on the cell region. Each of the control gate stacks includes a storage layer and a control gate on the storage layer. The memory device includes at least one high-? metal gate stack disposed on the substrate. The high-? metal gate stack has a metal gate and a high-? dielectric film wrapping around the metal gate, and a top surface of the control gate is lower than a top surface of the metal gate.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers and a plurality of inter-layer insulating layers each provided between the plurality of electrode layers; and a columnar portion penetrating the stacked body and extending in a stacking direction of the stacked body. The columnar portion includes a channel body extending in the stacking direction; and a charge storage film provided between the channel body and each of the electrode layers. Each of the electrode layers includes an edge portion provided closer on a central axis side of the columnar portion than the inter-layer insulating layers. The charge storage film covers the edge portion of each of the electrode layers and separated from each other in the stacking direction.

Abstract: According to one embodiment, a method is disclosed for manufacturing an integrated circuit device, the method can include forming a mask member on a first film, the mask member having a pattern, performing a first etching on the first film using the mask member as a mask to form a recessed section in the first film, forming a second film covering an inner side surface of the recessed section. The second film has a film thickness of preventing blockage of the recessed section, and performing a second etching on the second film and the first film via the recessed section. The performing of the second etching includes performing a third etching in a condition of an etching rate at a place smaller in curvature radius in the recessed section being lower than an etching rate at a place larger in curvature radius in the recessed section.

Abstract: A memory cell formed by forming a trench in the surface of a substrate. First and second spaced apart regions are formed in the substrate with a channel region therebetween. The first region is formed under the trench. The channel region includes a first portion that extends along a sidewall of the trench and a second portion that extends along the surface of the substrate. A charge trapping layer in the trench is adjacent to and insulated from the first portion of the channel region for controlling the conduction of the channel region first portion. An electrically conductive gate in the trench is adjacent to and insulated from the charge trapping layer and from the first region and is capacitively coupled to the charge trapping layer. An electrically conductive control gate is disposed over and insulated from the second portion of the channel region for controlling its conduction.

Abstract: The memory string comprises: a first semiconductor layer; a stacked body in which a plurality of conductive layers and a plurality of interlayer insulating layers are stacked along a first direction above the first semiconductor layer; and a second semiconductor layer having a longitudinal direction along the first direction and provided above the first semiconductor layer. The memory insulating layer includes a charge accumulation layer between the second semiconductor layer and the plurality of the conductive layers. The core insulating layer has a longitudinal direction along the first direction, and is provided in the second semiconductor layer. The oxide film layer is provided between the core insulating layer and the second semiconductor layer.

Abstract: A first insulating film in contact with an oxide semiconductor film and a second insulating film are stacked in this order over an electrode film of a transistor including the oxide semiconductor film, an etching mask is formed over the second insulating film, an opening portion exposing the electrode film is formed by etching a portion of the first insulating film and a portion of the second insulating film, the opening portion exposing the electrode film is exposed to argon plasma, the etching mask is removed, and a conductive film is formed in the opening portion exposing the electrode film. The first insulating film is an insulating film whose oxygen is partly released by heating. The second insulating film is less easily etched than the first insulating film and has a lower gas-permeability than the first insulating film.

Abstract: A split gate memory device includes a semiconductor substrate and a select gate over the substrate. The select gate has a bottom portion and a top portion over the bottom portion, wherein the top portion has a top sidewall and the bottom portion has a bottom sidewall, and wherein the bottom sidewall extends beyond the top sidewall. The devices also includes a control gate adjacent the select gate, a charge storage layer located between the select gate and the control gate and between the control gate and the substrate, and an isolation region over the bottom portion of the select gate and between the top sidewall of the select gate and the charge storage layer. The bottom sidewall of the bottom portion extends to the charge storage layer.

Abstract: Embodiments described herein relate to methods for patterning a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment on a spacer material, performing an etching process on a treated region of the spacer material, and repeating the inert plasma treatment and the etching process to form a desired spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as process gas ratios and pressures, may be controlled to influence a desired spacer profile.