Comprising Charge Trapping Insulator (epo) Patents (Class 257/E21.21)
  • Patent number: 10665726
    Abstract: A memory device and an operation method thereof are provided. The memory device includes a semiconductor substrate and an oxide-nitride-oxide (ONO) gate structure located on the semiconductor substrate. The ONO gate structure includes a bottom oxide layer, a top oxide layer and a nitride layer. The nitride layer is located between the bottom oxide layer and the top oxide layer. The bottom oxide layer is located closer to the semiconductor substrate than the top oxide layer. The bottom oxide layer has a first thickness, and the top oxide layer has a second thickness smaller the first thickness. The operation method includes an erasing operation and a programming operation. Electrons are attracted into the ONO gate structure through the bottom oxide layer in the programming operation. Electrons trapped in the ONO gate structure escape from the ONO gate structure through the top oxide layer.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Yu Yang, Chung-Jen Huang
  • Patent number: 10504902
    Abstract: Disclosed are data storage devices and methods of manufacturing the same. The methods may include providing a substrate including a cell region and a peripheral circuit region, forming a data storage layer on the cell region and the peripheral circuit region of the substrate, selectively forming a mask layer on a portion of the data storage layer that is formed on the peripheral circuit region, forming a top electrode layer on the data storage layer and the mask layer, patterning the top electrode layer to form a plurality of top electrodes on the cell region, and patterning the data storage layer using the plurality of top electrodes as an etch mask to form a plurality of data storage parts on the cell region. While patterning the top electrode layer, the mask layer on the peripheral circuit region may serve as an etch stop layer.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: December 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong Hyun Kim, Seung Pil Ko, Hyunchul Shin, Kilho Lee
  • Patent number: 10297606
    Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: May 21, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Youseok Suh, Sung-Yong Chung, Ya-Fen Lin, Yi-Ching Jean Wu
  • Patent number: 10290722
    Abstract: A memory device includes a semiconductor substrate having a cell region and a peripheral region surrounding the cell region and a pair of control gate stacks on the cell region. Each of the control gate stacks includes a storage layer and a control gate on the storage layer. The memory device includes at least one high-? metal gate stack disposed on the substrate. The high-? metal gate stack has a metal gate and a high-? dielectric film wrapping around the metal gate, and a top surface of the control gate is lower than a top surface of the metal gate.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Wen Tseng, Tsung-Yu Yang, Chung-Jen Huang
  • Patent number: 9917096
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers and a plurality of inter-layer insulating layers each provided between the plurality of electrode layers; and a columnar portion penetrating the stacked body and extending in a stacking direction of the stacked body. The columnar portion includes a channel body extending in the stacking direction; and a charge storage film provided between the channel body and each of the electrode layers. Each of the electrode layers includes an edge portion provided closer on a central axis side of the columnar portion than the inter-layer insulating layers. The charge storage film covers the edge portion of each of the electrode layers and separated from each other in the stacking direction.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: March 13, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takeshi Kamigaichi
  • Patent number: 9887098
    Abstract: According to one embodiment, a method is disclosed for manufacturing an integrated circuit device, the method can include forming a mask member on a first film, the mask member having a pattern, performing a first etching on the first film using the mask member as a mask to form a recessed section in the first film, forming a second film covering an inner side surface of the recessed section. The second film has a film thickness of preventing blockage of the recessed section, and performing a second etching on the second film and the first film via the recessed section. The performing of the second etching includes performing a third etching in a condition of an etching rate at a place smaller in curvature radius in the recessed section being lower than an etching rate at a place larger in curvature radius in the recessed section.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: February 6, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Katsunori Yahashi
  • Patent number: 9882033
    Abstract: A memory cell formed by forming a trench in the surface of a substrate. First and second spaced apart regions are formed in the substrate with a channel region therebetween. The first region is formed under the trench. The channel region includes a first portion that extends along a sidewall of the trench and a second portion that extends along the surface of the substrate. A charge trapping layer in the trench is adjacent to and insulated from the first portion of the channel region for controlling the conduction of the channel region first portion. An electrically conductive gate in the trench is adjacent to and insulated from the charge trapping layer and from the first region and is capacitively coupled to the charge trapping layer. An electrically conductive control gate is disposed over and insulated from the second portion of the channel region for controlling its conduction.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: January 30, 2018
    Assignee: Silicon Storage Technology, Inc.
    Inventor: Nhan Do
  • Patent number: 9825054
    Abstract: The memory string comprises: a first semiconductor layer; a stacked body in which a plurality of conductive layers and a plurality of interlayer insulating layers are stacked along a first direction above the first semiconductor layer; and a second semiconductor layer having a longitudinal direction along the first direction and provided above the first semiconductor layer. The memory insulating layer includes a charge accumulation layer between the second semiconductor layer and the plurality of the conductive layers. The core insulating layer has a longitudinal direction along the first direction, and is provided in the second semiconductor layer. The oxide film layer is provided between the core insulating layer and the second semiconductor layer.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: November 21, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kotaro Fujii, Hideaki Aochi
  • Patent number: 9818849
    Abstract: A first insulating film in contact with an oxide semiconductor film and a second insulating film are stacked in this order over an electrode film of a transistor including the oxide semiconductor film, an etching mask is formed over the second insulating film, an opening portion exposing the electrode film is formed by etching a portion of the first insulating film and a portion of the second insulating film, the opening portion exposing the electrode film is exposed to argon plasma, the etching mask is removed, and a conductive film is formed in the opening portion exposing the electrode film. The first insulating film is an insulating film whose oxygen is partly released by heating. The second insulating film is less easily etched than the first insulating film and has a lower gas-permeability than the first insulating film.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: November 14, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Hiroshi Fujiki, Yoshinori Ieda
  • Patent number: 9728410
    Abstract: A split gate memory device includes a semiconductor substrate and a select gate over the substrate. The select gate has a bottom portion and a top portion over the bottom portion, wherein the top portion has a top sidewall and the bottom portion has a bottom sidewall, and wherein the bottom sidewall extends beyond the top sidewall. The devices also includes a control gate adjacent the select gate, a charge storage layer located between the select gate and the control gate and between the control gate and the substrate, and an isolation region over the bottom portion of the select gate and between the top sidewall of the select gate and the charge storage layer. The bottom sidewall of the bottom portion extends to the charge storage layer.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: August 8, 2017
    Assignee: NXP USA, Inc.
    Inventors: Craig T. Swift, Asanga H. Perera
  • Patent number: 9721807
    Abstract: Embodiments described herein relate to methods for patterning a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment on a spacer material, performing an etching process on a treated region of the spacer material, and repeating the inert plasma treatment and the etching process to form a desired spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as process gas ratios and pressures, may be controlled to influence a desired spacer profile.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: August 1, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Qingjun Zhou, Jungmin Ko, Tom Choi, Sean Kang, Jeremiah Pender, Srinivas D. Nemani, Ying Zhang
  • Patent number: 9679762
    Abstract: A high electron mobility transistor (HEMT) device with enhanced conductivity in the transistor's non-gated access regions and a method for making the HEMT device is disclosed. In one embodiment, the HEMT device includes a heterojunction comprising a barrier layer formed on a channel layer. One or more intervening layers comprising a material suitable for increasing a fixed charge at the heterojunction is formed on a substantially planar surface of the barrier layer opposite the channel layer in the non-gated access region.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: June 13, 2017
    Assignee: Toshiba Corporation
    Inventors: Andrew Paul Edwards, Xinyu Zhang, Yan Zhu
  • Patent number: 9530678
    Abstract: A substrate carrier system for moving substrates in a vertical oven and a method for processing substrates are disclosed. In some embodiments, a method for oxidizing material or depositing material includes carrying a plurality of substrates by a substrate carrier and inserting the substrate carrier into a vertical oven, wherein the plurality of substrates are held by the substrate carrier in predefined positions, wherein an angle measured between a main surface of a substrate of the plurality of substrates at one of the predefined positions and a vertical direction is less than 20 degrees. The method further includes oxidizing a material on the plurality of substrates or depositing a material onto the plurality of substrates.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: December 27, 2016
    Assignee: Infineon Technologies AG
    Inventors: Andreas Stefaner, Heimo Schieder, Guenter Denifl, Roland Moennich, Anton Gernot Winkler
  • Patent number: 9443866
    Abstract: A tunneling dielectric layer for a vertical memory device is formed with a stack that provides a barrier height profile for high data retention tolerance. Memory stack structures extend through a stack of insulating layers and electrically conductive layers. Each memory stack structure comprises, from outside to inside, a blocking dielectric, memory elements, a tunneling dielectric layer, and a vertical semiconductor channel. The tunneling dielectric layer comprises, from outside to inside, an outer silicon oxide layer, a first silicon oxynitride layer having a first atomic nitrogen concentration, a second silicon oxynitride layer having a second atomic nitrogen concentration that is less than the first atomic nitrogen concentration, and an inner silicon oxide layer that contacts a vertical semiconductor channel. The reduced band gap of the first silicon oxynitride layer relative to the second silicon oxynitride layer provides additional energy barrier for relaxation of holes stored in the memory elements.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: September 13, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Kiyohiko Sakakibara
  • Patent number: 9209317
    Abstract: Nonvolatile memory devices including three transistor unit cells are provided. The nonvolatile memory device includes a selection transistor having a first terminal and a second terminal, a first charge trap transistor electrically connected in series to the first terminal of the selection transistor, a second charge trap transistor electrically connected in series to the second terminal of the selection transistor, and a word line electrically connected to gate electrodes of the selection transistor, the first charge trap transistor and the second charge trap transistor. Related methods are also provided.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: December 8, 2015
    Assignee: SK Hynix Inc.
    Inventor: Young Joon Kwon
  • Patent number: 9012322
    Abstract: Wet-etch solutions for conductive metals (e.g., copper) and metal nitrides (e.g., tantalum nitride) can be tuned to differentially etch the conductive metals and metal nitrides while having very little effect on nearby oxides (e.g., silicon dioxide hard mask materials), and etching refractory metals (e.g. tantalum) at an intermediate rate. The solutions are aqueous base solutions (e.g., ammonia-peroxide mixture or TMAH-peroxide mixture) with just enough hydrofluoric acid (HF) added to make the solution's pH about 8-10. Applications include metallization of sub-micron logic structures.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: April 21, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Anh Duong, Errol Todd Ryan
  • Patent number: 8981452
    Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing also are provided.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: March 17, 2015
    Assignee: SanDisk Corporation
    Inventors: Jian Chen, Xiangfeng Duan, Chao Liu, Madhuri Nallabolu, J. Wallace Parce, Srikanth Ranganathan
  • Patent number: 8946021
    Abstract: On a silicon substrate is formed a stacked body by alternately stacking a plurality of silicon oxide films and silicon films, a trench is formed in the stacked body, an alumina film, a silicon nitride film and a silicon oxide film are formed in this order on an inner surface of the trench, and a channel silicon crystalline film is formed on the silicon oxide film. Next, a silicon oxide layer is formed at an interface between the silicon oxide film and the channel silicon crystalline film by performing thermal treatment in an oxygen gas atmosphere.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: February 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshio Ozawa
  • Patent number: 8941171
    Abstract: Memory devices, methods for fabricating, and methods for adjusting flatband voltages are disclosed. In one such memory device, a pair of source/drain regions are formed in a semiconductor. A dielectric material is formed on the semiconductor between the pair of source/drain regions. A control gate is formed on the dielectric material. A charged species is introduced into the dielectric material. The charged species, e.g., mobile ions, has an energy barrier in a range of greater than about 0.5 eV to about 3.0 eV. A flatband voltage of the memory device can be adjusted by moving the charged species to different levels within the dielectric material, thus programming different states into the device.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: January 27, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Roy Meade
  • Patent number: 8912089
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a stacked body on a substrate. The stacked body includes a plurality of first conductive layers including a metallic element as a main component and a plurality of second conductive layers including a metallic element as a main component provided respectively between the first conductive layers. The method includes making a hole to pierce the stacked body. The method includes making a slit to divide the stacked body. The method includes making a gap between the first conductive layers by removing the second conductive layers by etching via the slit or the hole. The method includes forming a memory film including a charge storage film at a side wall of the hole. The method includes forming a channel body on an inner side of the memory film inside the hole.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: December 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiichi Omoto, Yoshihiro Uozumi, Tadashi Iguchi, Osamu Yamane, Kazuyuki Masukawa, Yoshihiro Yanai
  • Patent number: 8912593
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method includes forming a second stacked body on the planarized interlayer insulating film and on the uppermost stair. The second stacked body includes a second conductive film thicker than the first conductive film and a second insulating film stacked on the second conductive film. The method includes dividing the second stacked body into a select gate on the uppermost stair and a plurality of wall portions in a staircase region below the uppermost stair. The method includes forming a plurality of vias piercing the interlayer insulating film under a region between the wall portions and reaching the first conductive film of each of the stairs.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: December 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toru Matsuda
  • Patent number: 8907410
    Abstract: A through-the silicon via (TSV) structure providing a built-in TSV U-shaped FET that includes an annular gate shaped as a TSV partially embedded in a substrate, the annular gate having an inner and an outer surface bound by an oxide layer; a drain formed on an isolated epitaxial layer on top of the substrate conformally connecting the gate oxide layer surrounding the inner annular surface of the TSV; a source partially contacting said gate oxide layer conformally contacting gate oxide layer surrounding the outer surface of the TSV.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chandrasekharan Kothandaraman, Sami Rosenblatt, Geng Wang
  • Patent number: 8895393
    Abstract: In a semiconductor device and a method of forming such a device, the semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers is provided on the substrate. A plurality of gate patterns is provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel, the vertical channel being in contact with the substrate at a contact region that comprises a semiconducting region.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: November 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Sung Sim, Jung-Dal Choi
  • Patent number: 8853769
    Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: October 7, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Deepak Thimmegowda, Andrew R. Bicksler, Roland Awusie
  • Patent number: 8847300
    Abstract: A semiconductor device including a conductive layer, a diffusion barrier layer formed over the conductive layer, including a refractory metal compound, and acquired after a surface treatment, and a metal silicide layer formed over the diffusion barrier layer. The adhesion between a diffusion barrier layer and a metal silicide layer may be improved by increasing the surface energy of the diffusion barrier layer through a surface treatment. Therefore, although the metal silicide layer is fused in a high-temperature process, it is possible to prevent a void from being caused at the interface between the diffusion barrier layer and the metal silicide layer. Moreover, it is possible to increase the adhesion between a conductive layer and the diffusion barrier layer by increasing the surface energy of the conductive layer through the surface treatment.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: September 30, 2014
    Assignee: SK Hynix Inc.
    Inventors: Sung-Jin Whang, Moon-Sig Joo, Kwon Hong, Jung-Yeon Lim, Won-Kyu Kim, Bo-Min Seo, Kyoung-Eun Chang
  • Patent number: 8841183
    Abstract: On a silicon substrate is formed a stacked body by alternately stacking a plurality of silicon oxide films and silicon films, a trench is formed in the stacked body, an alumina film, a silicon nitride film and a silicon oxide film are formed in this order on an inner surface of the trench, and a channel silicon crystalline film is formed on the silicon oxide film. Next, a silicon oxide layer is formed at an interface between the silicon oxide film and the channel silicon crystalline film by performing thermal treatment in an oxygen gas atmosphere.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: September 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshio Ozawa
  • Patent number: 8836009
    Abstract: A MONOS Charge-Trapping flash (CTF), with record thinnest 3.6 nm ENT trapping layer, has a large 3.1 V 10-year extrapolated retention window at 125° C. and excellent 106 endurance at a fast 100 ?s and ±16 V program/erase. This is achieved using As+-implanted higher ? trapping layer with deep 5.1 eV work-function of As. In contrast, the un-implanted device only has a small 10-year retention window of 1.9 V at 125° C. A MoN—[SiO2—LaAlO3]—[Ge—HfON]—[LaAlO3—SiO2]—Si CTF device is also provided with record-thinnest 2.5-nm Equivalent-Si3N4-Thickness (ENT) trapping layer, large 4.4 V initial memory window, 3.2 V 10-year extrapolated retention window at 125° C., and 3.6 V endurance window at 106 cycles, under very fast 100 ?s and low ±16 V program/erase. These were achieved using Ge reaction with HfON trapping layer for better charge-trapping and retention.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: September 16, 2014
    Assignee: National Chiao Tung University
    Inventors: Albert Chin, Chun-Yang Tsai
  • Patent number: 8829595
    Abstract: A 3-dimensional non-volatile memory device, a memory system including the same, and a method of manufacturing the same comprise vertical channel layers protruding from a substrate, a plurality of interlayer insulating layers and a plurality of conductive layers alternately formed along the vertical channel layers, a charge trap layer surrounding the vertical channel layers, the charge trap layer having a smaller thickness in a plurality of first regions, interposed between the plurality of conductive layers and the vertical channel layers, than in a plurality of second regions, interposed between the plurality of interlayer insulating layers and the vertical channel layers and a blocking insulating layer formed in each of the plurality of first regions, between the plurality of conductive layers and the charge trap layer.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: September 9, 2014
    Assignee: SK Hynix Inc.
    Inventor: Dong Kee Lee
  • Patent number: 8829598
    Abstract: A method for fabricating a non-volatile memory device, the method includes alternately stacking inter-layer dielectric layers and sacrificial layers over a substrate, etching the inter-layer dielectric layers and the sacrificial layers to form trenches to expose a surface of the substrate, etching the inter-layer dielectric layers exposed by the trenches to a predetermined thickness, forming junction layers over etched portions of the inter-layer dielectric layers, and burying a layer for a channel within the trenches in which the junction layers have been formed to form a channel.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: September 9, 2014
    Assignee: SK Hynix Inc.
    Inventors: Se-Yun Lim, Sang-Hyun Oh, Gyo-Ji Kim, Eun-Seok Choi
  • Patent number: 8816424
    Abstract: A non-volatile memory includes a channel layer to extend from a substrate in a vertical direction; a plurality of interlayer dielectric layers and a plurality of gate electrodes to be alternately stacked along the channel layer; and a memory layer to be interposed between the channel layer and each of the gate electrodes, wherein the memory layer comprises a tunnel dielectric layer to contact the channel layer, a first charge trap layer to contact the tunnel dielectric layer and formed of an insulating material, a charge storage layer to contact the first charge trap layer and formed of a semiconducting material or a conductive material, a second charge trap layer to contact the charge storage layer and formed of an insulating material, and a charge blocking layer to contact the second charge trap layer.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: August 26, 2014
    Assignee: SK Hynix Inc.
    Inventors: Ki-Hong Lee, Kwon Hong
  • Patent number: 8803216
    Abstract: A memory cell system including providing a substrate, forming a charge-storing stack having silicon-rich nitride on the substrate, and forming a gate on the charge-storing stack.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: August 12, 2014
    Assignees: Spansion, LLC, Advanced Micro Devices, Inc.
    Inventors: Meng Ding, Lei Xue, Mark Randolph, Chi Chang, Robert Bertram Ogle, Jr.
  • Patent number: 8796129
    Abstract: Provided is an excellent nonvolatile storage device having advantageous in miniaturization and less variation in initial threshold value, and exhibiting a high writing efficiency, without an erasing failure and a retention failure. The nonvolatile storage device is characterized by including a film stack extending from between a semiconductor substrate and a gate electrode onto at least a surface of the gate electrode lying on a first impurity diffusion region side, the film stack including a charge accumulating layer and a tunnel insulating film sequentially from a gate electrode side.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: August 5, 2014
    Assignee: NEC Corporation
    Inventor: Yukihide Tsuji
  • Patent number: 8772852
    Abstract: Provided is a nonvolatile memory device including a common source. The device includes a first active region crossing a second active region, a common source disposed in the second active region, and a source conductive line disposed on the common source in parallel to the common source. The source conductive line is electrically connected to the common source.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: July 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Soo Kim, Keon-Soo Kim
  • Patent number: 8716119
    Abstract: Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: May 6, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Yongjun Jeff Hu
  • Patent number: 8697524
    Abstract: Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Kwan You, Kwang-Soo Seol, Young-Woo Park, Jin-Soo Lim
  • Patent number: 8691648
    Abstract: Non-volatile semiconductor memories and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the method includes: (i) forming a gate for a non-volatile memory transistor on a surface of a substrate overlaying a channel region formed therein, the gate including a charge trapping layer; and (ii) forming a strain inducing structure over the gate of the non-volatile memory transistor to increase charge retention of the charge trapping layer. Preferably, the memory transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) transistor comprising a SONOS gate stack. More preferably, the memory also includes a logic transistor on the substrate, and the step of forming a strain inducing structure comprises the step of forming the strain inducing structure over the logic transistor. Other embodiments are also disclosed.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: April 8, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Igor Polishchuk, Sagy Levy, Krishnaswamy Ramkumar, Jeong Soo Byun
  • Patent number: 8680601
    Abstract: A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source/drain regions. A gate stack is above the substrate over the channel region and between the pair of source/drain regions. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: March 25, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sagy Levy, Fredrick B. Jenne, Krishnaswamy Ramkumar
  • Patent number: 8669622
    Abstract: A non-volatile semiconductor device includes a memory cell in a first area of a substrate, a low voltage transistor in a second area of the substrate, and a high voltage transistor in a third area of the substrate. The memory cell includes a tunnel insulation layer formed on the substrate, a charge trapping layer pattern formed on the tunnel insulation layer in the first area of the substrate, a blocking layer pattern formed on the charge trapping layer pattern and a control gate formed on the blocking layer pattern. The control gate has a width substantially smaller than a width of the blocking layer pattern and the width of the control gate is substantially smaller than a width of the charge trapping layer pattern. In addition, an offset is formed between the control gate and the blocking layer pattern such that a spacer is not formed on a sidewall of the control gate.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: March 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hak-Sun Lee, Kyoung-Sub Shin
  • Patent number: 8669606
    Abstract: An embodiment of the invention includes a semiconductor device including a semiconductor substrate with a trench; a tunnel insulating film covering an inner surface of the trench; a trap layer in contact with the tunnel insulating film on an inner surface of an upper portion of the trench; a top insulating film in contact with the trap layer; a gate electrode embedded in the trench, and in contact with the tunnel insulating film at a lower portion of the trench and in contact with the top insulating film at the upper portion of the trench, in which the trap layer and the top insulating film, in between the lower portion of the trench and the upper portion of the trench, extend and protrude from both sides of the trench so as to be embedded in the gate electrode, and a method for manufacturing thereof.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: March 11, 2014
    Assignee: Spansion LLC
    Inventors: Fumiaki Toyama, Fumihiko Inoue
  • Patent number: 8637917
    Abstract: An insulating pattern is disposed on a surface of a semiconductor substrate and includes a silicon oxynitride film. A conductive pattern is disposed on the insulating pattern. A data storage pattern and a vertical channel pattern are disposed within a channel hole formed to vertically penetrate the insulating pattern and the conductive pattern. The data storage pattern and the vertical channel pattern are conformally stacked along sidewalls of the insulating pattern and the conductive pattern. A concave portion is formed in the semiconductor substrate adjacent to the insulating pattern. The concave portion is recessed relative to a bottom surface of the insulating pattern.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: January 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Yul Lee, Han-Mei Choi, Dong-Chul Yoo, Young-Jong Je, Ki-Hyun Hwang
  • Patent number: 8618603
    Abstract: A nonvolatile semiconductor memory device includes: a semiconductor member; a memory film provided on a surface of the semiconductor member and being capable of storing charge; and a plurality of control gate electrodes provided on the memory film, spaced from each other, and arranged along a direction parallel to the surface. Average dielectric constant of a material interposed between one of the control gate electrodes and a portion of the semiconductor member located immediately below the control gate electrode adjacent to the one control gate electrode is lower than average dielectric constant of a material interposed between the one control gate electrode and a portion of the semiconductor member located immediately below the one control gate electrode.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: December 31, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Ozawa, Fumiki Aiso
  • Patent number: 8603878
    Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: December 10, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoon Son, Jong-Wook Lee, Jong-Hyuk Kang
  • Patent number: 8604537
    Abstract: There is provided a nonvolatile memory device having a tunnel dielectric layer formed over a substrate, the charge capturing layer formed over the tunnel dielectric layer and including a combination of at least one charge storage layer and at least one charge trap layer, a charge blocking layer formed over the charge capturing layer, and a gate electrode formed over the charge blocking layer.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: December 10, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ki-Hong Lee, Kwon Hong
  • Patent number: 8598649
    Abstract: A nonvolatile semiconductor memory device according to embodiment includes: a semiconductor substrate having an upper portion being partitioned into a plurality of semiconductor portions extending in a first direction; a charge storage film provided on the semiconductor portion; a word-line electrode provided on the semiconductor substrate and extending in a second direction intersecting with the first direction; and a pair of selection gate electrodes provided on both sides of the word-line electrode in the first direction on the semiconductor substrate and extending in the second direction, a shortest distance between a corner portion of each of the semiconductor portions and each of the selection gate electrodes being longer than a shortest distance between the corner portion of the semiconductor portion and the word-line electrode in a cross section parallel to the second direction.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: December 3, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Okamura, Noboru Ooike, Wataru Sakamoto, Takashi Izumida
  • Patent number: 8575675
    Abstract: A nonvolatile memory device includes a first channel comprising a pair of first pillars vertically extending from a substrate and a first coupling portion positioned under the pair of first pillars and coupling the pair of first pillars, a second channel adjacent to the first channel comprising a pair of second pillars vertically extending from the substrate and a second coupling portion positioned under the pair of second pillars and coupling the pair of second pillars, a plurality of gate electrode layers and interlayer dielectric layers alternately stacked along the first and second pillar portions, and first and second trenches isolating the plurality of gate electrode layers between the pair of first pillar portions and between the pair of second pillar portions, respectively.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: November 5, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sun-Mi Park, Byung-Soo Park, Sang-Hyun Oh
  • Patent number: 8569822
    Abstract: A memory structure having a memory cell including a first dielectric layer, a gate, a semiconductor layer, a first doped region, a second doped region and a charge storage layer is provided. The first dielectric layer is on the substrate. The gate includes a base portion on the first dielectric layer and a protruding portion disposed on the base portion and partially exposing the base portion. The semiconductor layer is conformally disposed on the gate, and includes a top portion over the protruding portion, a bottom portion over the base portion exposed by the protruding portion and a side portion located at a sidewall of the protruding portion and connecting the top and bottom portions. The first and second doped regions are respectively in the top and bottom portions. The side portion serves as a channel region. The charge storage layer is between the gate and the semiconductor layer.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: October 29, 2013
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Jyun-Siang Huang, Wen-Jer Tsai, Shih-Guei Yan
  • Patent number: 8557695
    Abstract: According to an aspect of the present invention, there is provided, a nonvolatile semiconductor storage device including: a substrate; a stacked portion that includes a plurality of conductor layers and a plurality of insulation layers alternately stacked on the substrate, at least one layer of the plurality of conductor layers and the plurality of insulation layers forming a marker layer; a charge accumulation film that is formed on an inner surface of a memory plug hole that is formed in the stacked portion from a top surface to a bottom surface thereof; and a semiconductor pillar that is formed inside the memory plug hole through the charge accumulation film.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: October 15, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Mizukami, Fumitaka Arai
  • Patent number: 8552489
    Abstract: A mold stack including alternating insulation layers and sacrificial layers is formed on a substrate. Vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack are formed. Gate electrodes are formed between adjacent ones of the insulation layers and surrounding the vertical channel regions. The gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location further away from the sidewalls of the insulation layers.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: October 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Daehong Eom, Kyunghyun Kim, Kwangsu Kim, Jun-Youl Yang, Se-Ho Cha
  • Patent number: 8546867
    Abstract: A technique capable of improving the reliability of a non-volatile memory semiconductor device is provided and, in particular, a technique capable of supplying electricity without fail to a memory gate electrode of split gate transistor is provided. One end of an electricity supply line ESL is arranged over a terminal end TE1 and the other end thereof is arranged over a terminal end TE2, and further, the central portion of the electricity supply line ESL is arranged over a dummy part DMY. That is, the terminal end TE1, the terminal end TE2, and the dummy part DMY have substantially the same height, and therefore, most of the electricity supply line ESL arranged from over the terminal end TE1 to over the terminal end TE2 via the dummy part DMY is formed so as to have the same height.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: October 1, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hiraku Chakihara, Tsutomu Okazaki
  • Patent number: 8546216
    Abstract: A nonvolatile semiconductor memory device includes a first insulating layer, charge storage layers, element isolation insulating films, and a second insulating layer formed on the charge storage layers and the element isolation insulating films and including a stacked structure of a first silicon nitride film, first silicon oxide film, intermediate insulating film and second silicon oxide film. The first silicon nitride film has a nitrogen concentration of not less than 21×1015 atoms/cm2. Each element isolation insulating film includes a high-temperature oxide film formed along lower side surfaces of the charge storage layers between the charge storage layers and a coating type insulating film. The first silicon nitride film is formed on an upper surface of the high-temperature oxide film in upper surfaces of the element isolation insulating films and not on the upper surface of the coating type insulating film.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: October 1, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirofumi Iikawa, Masayuki Tanaka