Recoil-implantation (epo) Patents (Class 257/E21.338)
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Patent number: 10002930Abstract: Disclosed is a method. The method includes forming a metal layer on a first surface of a semiconductor body; irradiating the metal layer with particles to move metal atoms from the metal layer into the semiconductor body and form a metal atom containing region in the semiconductor body; and annealing the semiconductor body. The annealing includes heating at least the metal atom containing region to a temperature of less than 500° C.Type: GrantFiled: November 30, 2016Date of Patent: June 19, 2018Assignee: Infineon Technologies AGInventors: Roland Rupp, Jens Peter Konrath, Francisco Javier Santos Rodriguez, Carsten Schaeffer, Hans-Joachim Schulze, Werner Schustereder, Guenther Wellenzohn
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Patent number: 8497194Abstract: Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant.Type: GrantFiled: November 12, 2012Date of Patent: July 30, 2013Assignee: Micron Technology, Inc.Inventors: Lequn Jennifer Liu, Shu Qin, Allen McTeer, Yongjun Jeff Hu
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Publication number: 20130153917Abstract: A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region. The source includes a GaN-layer coupled to an InGaN layer. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.Type: ApplicationFiled: December 14, 2011Publication date: June 20, 2013Applicant: EPOWERSOFT, Inc.Inventors: Linda Romano, Andrew Edwards, Dave P. Bour, Isik C. Kizilyalli
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Patent number: 8329567Abstract: Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant.Type: GrantFiled: November 3, 2010Date of Patent: December 11, 2012Assignee: Micron Technology, Inc.Inventors: Jennifer Lequn Liu, Shu Qin, Allen McTeer, Yongjun Jeff Hu
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Patent number: 8237239Abstract: A Schottky diode device is provided, including a p-type semiconductor structure. An n drift region is disposed over the p-type semiconductor structure, wherein the n drift region comprises first and second n-type doping regions having different n-type doping concentrations, and the second n-type doping region is formed with a dopant concentration greater than that in the first n-type doping region. A plurality of isolation structures is disposed in the second n-type doping region of the n drift region, defining an anode region and a cathode region. A third n-type doping region is disposed in the second n-type doping region exposed by the cathode region. An anode electrode is disposed over the first n-type doping region in the anode region. A cathode electrode is disposed over the third n-type doping region in the cathode region.Type: GrantFiled: October 28, 2009Date of Patent: August 7, 2012Assignee: Vanguard International Semiconductor CorporationInventors: Huang-Lang Pai, Hung-Shern Tsai
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Patent number: 7915128Abstract: A transistor suitable for high-voltage applications and a method of manufacture is provided. A first device is formed by depositing a dielectric layer and a conductive layer over a substrate. A hard mask is deposited over the conductive layer and patterned using photolithography techniques. The photoresist material is removed prior to etching the underlying conductive layer and dielectric layer. The hard mask is also used as an implant mask. Another mask may be deposited and formed over the conductive layer to form other devices in other regions of the substrate. The other mask is preferably removed from over the hard mask prior to etching the conductive layer and the dielectric layer.Type: GrantFiled: February 29, 2008Date of Patent: March 29, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu Wen Chen, Fu-Hsin Chen, Ming-Ren Tsai, William Wei-Yuan Tien
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Patent number: 7749783Abstract: A method of forming a display panel includes providing a first substrate having a transparent electrode, and a second substrate having a pixel electrode. Subsequently, an alignment material is provided and covers on the transparent electrode and/or the pixel electrode, and a photoelectric twisting layer is provided between the first substrate and the second substrate. The alignment material is first in a non-aligned state, and is radiation-polymerizable. The photoelectric twisting layer does not include any radiation-polymerizable material. Thereafter, a voltage difference is applied to drive molecules of the photoelectric twisting layer, and a radiating process is performed on the alignment material. The twisted molecules of the photoelectric twisting layer induce the surface molecules of the alignment material to arrange in an ordered state, and the alignment material is polymerized according to the ordered state as a first alignment film.Type: GrantFiled: April 2, 2009Date of Patent: July 6, 2010Assignee: AU Optronics Corp.Inventors: Rong-Ching Yang, Ming-Hung Wu, Shih-Feng Hsu, Li-Ya Yeh, Kuo-Hwa Wu, Wei-Yi Chien
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Patent number: 7501333Abstract: A fully silicided gate with a selectable work function includes; a gate dielectric over the substrate; and a first metal silicide layer over the gate dielectric, and a second metal silicide layer wherein the first metal silicide has a different phase then the second metal silicide layer. The metal silicide layers comprises at least one alloy element. The concentration of the alloy element on the interface between the gate dielectric and the metal silicide layers influence the work function of the gate.Type: GrantFiled: July 19, 2006Date of Patent: March 10, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Jung Lin, Cheng-Tung Lin, Chih-Wei Chang, Shau-Lin Shue
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Publication number: 20080044955Abstract: An electrostatic discharge (ESD) device and method is provided. The ESD device can comprise a substrate doped to a first conductivity type, an epitaxial region doped to the second conductivity type, and a first well doped to the first conductivity type disposed in the substrate. The first well can comprise a first region doped to the first conductivity type, a second region doped to a second conductivity type, and a first isolation region disposed between the first region and the second region. The ESD device can also comprise a second well doped to a second conductivity type disposed in the substrate adjacent to the first well, where the second well can comprise a third region doped to the first conductivity type, a fourth region doped to the second conductivity type, and a second isolation region disposed between the third region and the fourth region.Type: ApplicationFiled: October 12, 2007Publication date: February 21, 2008Inventors: Javier Salcedo, Juin Liou, Joseph Bernier, Donald Whitney