Radiation Treatment (epo) Patents (Class 257/E21.328)
  • Patent number: 9023693
    Abstract: A multi-mode thin film deposition apparatus including a reaction chamber, a carrying seat, a showerhead, an inert gas supplying source, a first gas inflow system and a second gas inflow system is provided. The carrying seat is disposed in the reaction chamber. The showerhead has a gas mixing room and gas holes disposed at a side of the gas mixing room. The gas mixing room is connected to the reaction chamber through the plurality of gas holes which faces the carrying seat. The first gas inflow system is connected to the reaction chamber and supplies a first process gas during a first thin film deposition process mode. The inert gas supplying source is connected to the gas mixing room for supplying an inert gas. The second gas inflow system is connected to the gas mixing room to supply a second process gas during a second thin film deposition process mode.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: May 5, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Kung-Liang Lin, Chien-Chih Chen, Fu-Ching Tung, Chih-Yung Chen, Shih-Chin Lin, Kuan-Yu Lin, Chia-Hao Chang, Shieh-Sien Wu
  • Patent number: 8940639
    Abstract: A MEMS device with movable MEMS structure and electrodes is produced by fabricating electrodes and shielding the electrodes with diamond buttons during subsequent fabrication steps, such as the etching of sacrificial oxide using vapor HF. In some embodiments, the diamond buttons are removed after the movable MEMS structure is released.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: January 27, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Fang Liu, Kuang L. Yang
  • Patent number: 8937302
    Abstract: The present invention provides an organic light-emitting diode, which includes a light-transmitting substrate, an anode arranged on the light-transmitting substrate, a hole transporting layer arranged on the anode, a light emission layer arranged on the hole transporting layer, an electron transporting layer arranged on the light emission layer, and a cathode arranged on the electron transporting layer. The light emission layer includes a color light emission layer and an ultraviolet light emission layer spaced from the color light emission layer. The present invention integrates functions of color displaying and ultraviolet source together to allow the color displaying and the ultraviolet source to be simultaneously or individually activated.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: January 20, 2015
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventors: Yawei Liu, Yuanchun Wu
  • Patent number: 8927348
    Abstract: Provided are a method of manufacturing a group-III nitride semiconductor light-emitting device in which a light-emitting device excellent in the internal quantum efficiency and the light extraction efficiency can be obtained, a group-III nitride semiconductor light-emitting device and a lamp. Included are an epitaxial step of forming a semiconductor layer (30) so as to a main surface (20) of a substrate (2), a masking step of forming a protective film on the semiconductor layer (30), a semiconductor layer removal step of removing the protective film and the semiconductor layer (30) by laser irradiation to expose the substrate (2), a grinding step of reducing the thickness of the substrate (2), a polishing step of polishing the substrate (2), a laser processing step of providing processing marks to the inside of the substrate (2), a division step of creating a plurality of light-emitting devices (1) while forming a division surface of the substrate (2) to have a rough surface.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: January 6, 2015
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Susumu Sugano, Hisayuki Miki, Hironao Shinohara
  • Patent number: 8922003
    Abstract: A method for forming a device is disclosed. A substrate with a contact region is provided. Vacancy defects are formed in the substrate. The vacancy defects have a peak concentration at a depth DV. A metal based contact is formed in the contact region. The metal based contact has a depth DC which is equal to about DV. The vacancy defects lower the resistance of the metal based contact with the substrate.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: December 30, 2014
    Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd., Nanyang Technological University
    Inventors: Dexter Xueming Tan, Yoke King Chin, Kin Leong Pey
  • Patent number: 8912103
    Abstract: A method of fabricating a nanoimprint lithography template includes installing a reticle on a reticle stage of scanning lithography equipment having a light source, the reticle stage and a template stage, mounting a template substrate on the template stage, and scanning the template substrate with light from the light source in an exposure process in which the light passes through the reticle and impinges the template substrate at an oblique angle of incidence.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: December 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Seok Heo, Jeong-Ho Yeo
  • Patent number: 8895416
    Abstract: Systems and methods for semiconductor device PN junction fabrication are provided. In one embodiment, a method for fabricating an electrical device having a P-N junction comprises: depositing a layer of amorphous semiconductor material onto a crystalline semiconductor base, wherein the crystalline semiconductor base comprises a crystalline phase of a same semiconductor as the amorphous layer; and growing the layer of amorphous semiconductor material into a layer of crystalline semiconductor material that is epitaxially matched to the lattice structure of the crystalline semiconductor base by applying an optical energy that penetrates at least the amorphous semiconductor material.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: November 25, 2014
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Bhushan Sopori, Anikara Rangappan
  • Patent number: 8871609
    Abstract: A thin wafer handling structure includes a semiconductor wafer, a release layer that can be released by applying energy, an adhesive layer that can be removed by a solvent, and a carrier, where the release layer is applied on the carrier by coating or laminating, the adhesive layer is applied on the semiconductor wafer by coating or laminating, and the semiconductor wafer and the carrier is bonded together with the release layer and the adhesive layer in between. The method includes applying a release layer on a carrier, applying an adhesive layer on a semiconductor wafer, bonding the carrier and the semiconductor wafer, releasing the carrier by applying energy on the release layer, e.g. UV or laser, and cleaning the semiconductor's surface by a solvent to remove any residue of the adhesive layer.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Ching Hsu, Chen-Shien Chen, Ching-Wen Hsiao
  • Patent number: 8866271
    Abstract: A semiconductor device manufacturing method includes loading a substrate, on which a high-k film is formed, into a processing chamber, performing a reforming process by heating the high-k film through irradiation of a microwave on the substrate, and unloading the substrate from the processing chamber.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: October 21, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Katsuhiko Yamamoto, Yuji Takebayashi, Tatsuyuki Saito, Masahisa Okuno
  • Patent number: 8828260
    Abstract: A substrate processing method for forming a space extending along a predetermined line in a silicon substrate includes a first step of converging a laser light which is an elliptically-polarized light having an ellipticity other than 1 at the substrate so as to form a plurality of modified spots within the substrate along the line and produce a modified region including the modified spots, and a second step of anisotropically etching the substrate so as to advance an etching selectively along the modified region and form the space in the substrate. In the first step, the light is converged at the substrate such that a moving direction of the light with respect to the substrate and a direction of polarization of the light form an angle of 45° or greater therebetween, and the modified spots are made align in one row along the line.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: September 9, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Hideki Shimoi, Keisuke Araki
  • Patent number: 8815708
    Abstract: A method for improving the quality of a SiC layer by effectively reducing or eliminating the carrier trapping centers in the as-grown SiC crystal. The method includes the steps of: (a) carrying out ion implantation of carbon atoms, silicon atoms, hydrogen atoms, or helium atoms into a shallow surface layer of the SiC crystal layer to introduce carbon interstitials into the surface layer, and (b) growing the SiC layer upward from the edge face of the surface layer into which the carbon interstitials have been introduced, and diffusing out the carbon interstitials that have been introduced into the surface layer from the surface layer into the grown layer and combining the carbon interstitials and point defects to make the electrically active point defects in the grown layer inactive.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: August 26, 2014
    Assignee: Central Research Institute of Electric Power Industry
    Inventors: Hidekazu Tsuchida, Liutauras Storasta
  • Patent number: 8784699
    Abstract: An oxide including indium (In), gallium (Ga) and zinc (Zn), wherein diffraction peaks are observed at positions corresponding to incident angles (2?) of 7.0° to 8.4°, 30.6° to 32.0°, 33.8° to 35.8°, 53.5° to 56.5° and 56.5° to 59.5° in an X-ray diffraction measurement (CuK? rays), and one of diffraction peaks observed at positions corresponding to incident angles (2?) of 30.6° to 32.0° and 33.8° to 35.8° is a main peak and the other is a sub peak.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: July 22, 2014
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Koki Yano, Masayuki Itose, Hirokazu Kawashima
  • Patent number: 8778118
    Abstract: A manufacturing method of laser processed parts in which at least a pressure-sensitive adhesive layer is provided on a base material as a pressure-sensitive adhesive sheet for laser processing, using a material having specified physical properties. This method comprises adhering the pressure-sensitive adhesive sheet for laser processing to the laser beam exit side of the work by way of the pressure-sensitive adhesive layer, processing the work by irradiating the work with a laser beam of within 2 times of the irradiation intensity for forming a through-hole in the work, at higher than the irradiation intensity of threshold for inducing ablation of the work, and peeling the pressure-sensitive adhesive sheet for laser processing from the work after the machining. Therefore, contamination of the work surface by decomposition products can be effectively suppressed, and laser processed parts can be manufactured easily and at high production efficiency.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: July 15, 2014
    Assignee: Nitto Denko Corporation
    Inventors: Masakatsu Urairi, Atsushi Hino, Naoyuki Matsuo, Tomokazu Takahashi, Takeshi Matsumura, Syouji Yamamoto
  • Patent number: 8753985
    Abstract: Molecular layer deposition of silicon carbide is described. A deposition precursor includes a precursor molecule which contains silicon, carbon and hydrogen. Exposure of a surface to the precursor molecule results in self-limited growth of a single layer. Though the growth is self-limited, the thickness deposited during each cycle of molecular layer deposition involves multiple “atomic” layers and so each cycle may deposit thicknesses greater than typically found during atomic layer depositions. Precursor effluents are removed from the substrate processing region and then the surface is irradiated before exposing the layer to the deposition precursor again.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: June 17, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Brian Underwood, Abhijit Basu Mallick, Nitin K. Ingle
  • Patent number: 8748236
    Abstract: A method for manufacturing a semiconductor device includes irradiating light to an effective region of a semiconductor substrate. A wavelength of the light is a wavelength adapted so that light absorptance of the semiconductor substrate increases if an intensity of the light increases. The light is irradiated so that a focus point of the light is made within the semiconductor substrate in the irradiating.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: June 10, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Atsushi Tanida
  • Patent number: 8748256
    Abstract: A method for forming an integrated circuit (IC) including a silicide block poly resistor (SIBLK poly resistor) includes forming a dielectric isolation region in a top semiconductor surface of a substrate. A polysilicon layer is formed including patterned resistor polysilicon on the dielectric isolation region and gate polysilicon on the top semiconductor surface. Implanting is performed using a first shared metal-oxide-semiconductor (MOS)/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon and gate polysilicon of a MOS transistor with at least a first dopant. Implanting is then performed using a second shared MOS/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon, gate polysilicon and source and drain regions of the MOS transistor with at least a second dopant. A metal silicide is formed on a first and second portion of a top surface of the patterned resistor polysilicon to form the SIBLK poly resistor.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: June 10, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Song Zhao, Gregory Charles Baldwin, Shashank S. Ekbote, Youn Sung Choi
  • Patent number: 8741777
    Abstract: A substrate processing method for forming a space extending along a predetermined line in a silicon substrate includes a first step of converging a laser light which is an elliptically-polarized light having an ellipticity other than 1 at the substrate so as to form a plurality of modified spots within the substrate along the line and construct a modified region including the modified spots, and a second step of anisotropically etching the substrate so as to advance an etching selectively along the modified region and form the space in the substrate. In the first step, the light is converged at the substrate such that a moving direction of the light with respect to the substrate and a direction of polarization of the light form an angle of less than 45° therebetween, and the modified spots are made align in a plurality of rows along the line.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: June 3, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Hideki Shimoi, Keisuke Araki
  • Patent number: 8736055
    Abstract: One aspect of the present invention is a method of making an electronic device. According to one embodiment, the method comprises depositing a cap layer containing at least one dopant onto a gapfill metal and annealing so that the at least one dopant migrates to grain boundaries and/or interfaces of the gapfill metal. Another aspect of the present invention is an electronic device.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: May 27, 2014
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, Nalla Praveen
  • Publication number: 20140097521
    Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a first cavity within a substrate. The first cavity is disposed under a portion of the substrate. The method further includes forming a first pillar within the first cavity to support the portion of the substrate.
    Type: Application
    Filed: October 9, 2012
    Publication date: April 10, 2014
    Applicant: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventors: Thoralf Kautzsch, Alessia Scire, Steffen Bieselt
  • Patent number: 8685269
    Abstract: A laser processing method of converging laser light into an object to be processed made of silicon so as to form a modified region and etching the object along the modified region so as to form the object with a through hole comprises a laser light converging step of converging the laser light at the object so as to form the modified region along a part corresponding to the through hole in the object; an etch resist film producing step of producing an etch resist film resistant to etching on an outer surface of the object after the laser light converging step; and an etching step of etching the object so as to advance the etching selectively along the modified region and form the through hole after the etch resist film producing step; while the laser light converging step exposes the modified region to the outer surface of the object.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: April 1, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Hideki Shimoi, Keisuke Araki
  • Publication number: 20140084351
    Abstract: A replacement channel and a method for forming the same in a semiconductor device are provided. A channel area is defined in a substrate which is a surface of a semiconductor wafer or a structure such as a fin formed over the wafer. Portions of the channel region are removed and are replaced with a replacement channel material formed by an epitaxial growth/deposition process to include a first dopant concentration level less than a first dopant concentration level. A subsequent doping operation or operations is then used to boost the average dopant concentration to a level greater than the first dopant concentration level. The replacement channel material is formed to include a gradient in which the upper portion of the replacement channel material has a greater dopant concentration than the lower portion of replacement channel material.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Lien HUANG, Ming-Huan TSAI, Clement Hsingjen WANN
  • Patent number: 8664098
    Abstract: A plasma processing apparatus includes a process chamber, a platen for supporting a workpiece, a source configured to generate a plasma in the process chamber, and an insulating modifier. The insulating modifier has a gap, and a gap plane, where the gap plane is defined by portions of the insulating modifier closest to the sheath and proximate the gap. A gap angle is defined as the angle between the gap plane and a plane defined by the front surface of the workpiece. Additionally, a method of having ions strike a workpiece is disclosed, where the range of incident angles of the ions striking the workpiece includes a center angle and an angular distribution, and where the use of the insulating modifier creates a center angle that is not perpendicular to the workpiece.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: March 4, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, Timothy J. Miller, Svetlana B. Radovanov, Anthony Renau, Vikram Singh
  • Patent number: 8642488
    Abstract: A multi-step system and method for curing a dielectric film in which the system includes a drying system configured to reduce the amount of contaminants, such as moisture, in the dielectric film. The system further includes a curing system coupled to the drying system, and configured to treat the dielectric film with ultraviolet (UV) radiation and infrared (IR) radiation in order to cure the dielectric film.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: February 4, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Junjun Liu, Eric M. Lee, Dorel L. Toma
  • Patent number: 8643174
    Abstract: One or more heating elements are disposed on a semiconductor substrate proximate a temperature sensitive circuit disposed on the substrate (e.g., bandgap circuit, oscillator). The heater element(s) can be controlled to heat the substrate and elevate the temperature of the circuit to one or more temperature points. One or more temperature measurements can be made at each of the one or more temperature points for calibrating one or more reference values of the circuit (e.g., bandgap voltage).
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: February 4, 2014
    Assignee: Atmel Corporation
    Inventor: Terje Saether
  • Patent number: 8628993
    Abstract: Disclosed is a method for removing individual layers of a layer stack. The layer stack includes a semiconductor layer disposed onto an optically dense electrically conductive layer which in turn is disposed upon an optically transparent layer. A laser at a first power level is projected through the optically transparent layer and onto the optically dense electrically conductive layer. The semiconductor layer is removed through heat evaporation imparted by the laser at the first power level without removing the optically dense electrically conductive layer. Optionally, the laser at a second power level, which is greater than the first power level, is projected onto the optically dense electrically conductive layer through the optically transparent layer. The optically dense electrically conductive layer is removed through heat evaporation imparted by the laser at the second power level without removing the optically transparent layer.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: January 14, 2014
    Assignee: Manz AG
    Inventors: Vasile Raul Moldovan, Christoph Tobias Neugebauer
  • Publication number: 20130299939
    Abstract: Various embodiments disclosed include methods of performing a double exposure process on a level of an integrated circuit (IC) chip to form an IC chip having an embedded electrically measurable identifier. In some cases, the method includes: exposing a level of an integrated circuit (IC) chip using a first mask orientation; subsequently exposing the level of the IC chip using a second mask orientation distinct from the first mask orientation; and developing the level of the IC chip to form an electrically measurable identifier on the IC chip.
    Type: Application
    Filed: May 11, 2012
    Publication date: November 14, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yoba Amoah, John J. Ellis-Monaghan, Roger C. Kuo, Molly J. Leitch, Zhihong Zhang
  • Publication number: 20130280922
    Abstract: A method of orienting a semiconductor wafer. The method includes rotating a wafer about a central axis; exposing a plurality of edge portions of the rotating wafer to light having a predetermined wavelength from one or more light sources; detecting a subsurface mark in one of the plurality of edge portions of the rotating wafer; and orienting the wafer using the detected subsurface mark as a reference.
    Type: Application
    Filed: April 18, 2012
    Publication date: October 24, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Ming LIN, Wan-Lai CHEN, Chia-Hung HUANG, Chi-Ming YANG, Chin-Hsiang LIN
  • Patent number: 8558291
    Abstract: An apparatus for annealing a substrate includes a substrate stage having a substrate mounting portion configured to mount the substrate; a heat source having a plurality of heaters disposed under the substrate mounting portion, the heaters individually preheating a plurality areas defined laterally in the substrate through a bottom surface of the substrate; and a light source facing a top surface of the substrate, configured to irradiate a pulsed light at a pulse width of about 0.1 ms to about 100 ms on the entire top surface of the substrate.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: October 15, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takayuki Ito
  • Patent number: 8557719
    Abstract: A method for fabricating a semiconductor device, according to the present invention includes the steps of: preparing an SOI substrate, which comprises a semiconductor supporting layer, an oxide layer formed on the semiconductor supporting layer and an SOI layer formed on the oxide layer; forming a semiconductor device on the SOI layer; forming a passivation layer over the SOI substrate, the passivation layer allowing a UV light to pass through it; and applying a UV light to the SOI substrate after the step of forming the semiconductor device is completed.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: October 15, 2013
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventors: Wataru Shimizu, Ikuo Kurachi
  • Patent number: 8557669
    Abstract: MOSFETs having localized stressors are provided. The MOSFET has a stress-inducing layer formed in the source/drain regions, wherein the stress-inducing layer comprises a first semiconductor material and a second semiconductor material. A treatment is performed on the stress-inducing layer such that a reaction is caused with the first semiconductor material and the second semiconductor material is forced lower into the stress-inducing layer. The stress-inducing layer may be either a recessed region or non-recessed region. A first method involves forming a stress-inducing layer, such as SiGe, in the source/drain regions and performing a nitridation or oxidation process. A nitride or oxide film is formed in the top portion of the stress-inducing layer, forcing the Ge lower into the stress-inducing layer. Another method embodiment involves forming a reaction layer over the stress-inducing layer and performing a treatment process to cause the reaction layer to react with the stress-inducing layer.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: October 15, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hao Chen, Pang-Yen Tsai, Chie-Chien Chang, Tze-Liang Lee, Shih-Chang Chen
  • Patent number: 8552533
    Abstract: A method for manufacturing the compound semiconductor substrate having a reduced dislocation density at an interface between a Si substrate. Contaminants, such as organic matter and metal, on a surface of a Si substrate are removed whereby a flat oxide film is formed. The oxide film on the surface is removed by using an aqueous hydrogen fluoride solution, whereby hydrogen termination treatment is performed. Immediately after being subjected to the hydrogen termination treatment the temperature of the Si substrate is raised in a vacuum apparatus. If the substrate temperature is raised without any operation, the termination hydrogen is released. Before the hydrogen is released, pre-irradiation with As is performed. Thus, an interface between the Si substrate and the compound semiconductor layer is prepared. Several minutes later, irradiation with Ga and As is performed. Thereby, the compound semiconductor is formed.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: October 8, 2013
    Assignee: Asahi Kasei EMD Corporation
    Inventors: Yoshihiko Shibata, Masatoshi Miyahara, Takashi Ikeda, Yoshihisa Kunimi
  • Patent number: 8536052
    Abstract: When forming a metal silicide within contact openings in complex semiconductor devices, a silicidation of sidewall surface areas of the contact openings may be initiated by forming a silicon layer therein, thereby reducing unwanted diffusion of the refractory metal species into the laterally adjacent dielectric material. In this manner, superior reliability and electrical performance of the resulting contact elements may be achieved on the basis of a late silicide process.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: September 17, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jens Heinrich, Kai Frohberg, Katrin Reiche
  • Publication number: 20130228923
    Abstract: One aspect of the present invention is a method of making an electronic device. According to one embodiment, the method comprises depositing a cap layer containing at least one dopant onto a gapfill metal and annealing so that the at least one dopant migrates to grain boundaries and/or interfaces of the gapfill metal. Another aspect of the present invention is an electronic device.
    Type: Application
    Filed: March 1, 2012
    Publication date: September 5, 2013
    Inventors: ARTUR KOLICS, Nalla Praveen
  • Patent number: 8501638
    Abstract: Laser annealing scanning methods that result in reduced annealing non-uniformities in semiconductor device structures under fabrication are disclosed. The methods include defining a length of an annealing laser beam such that the tails of the laser beam resided only within scribe lines that separate the semiconductor device structures. The annealing laser beam tails from adjacent scan path segments can overlap or not overlap within the scribe lines. The cross-scan length of the annealing laser beam can be selected to simultaneously scan more than one semiconductor device structure, as long as annealing laser beam is configured such that the tails do not fall within a semiconductor device structure.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: August 6, 2013
    Assignee: Ultratech, Inc.
    Inventor: Arthur W. Zafiropoulo
  • Publication number: 20130187264
    Abstract: A method for forming a device is disclosed. A substrate with a contact region is provided. Vacancy defects are formed in the substrate. The vacancy defects have a peak concentration at a depth DV. A metal based contact is formed in the contact region. The metal based contact has a depth DC which is equal to about DV. The vacancy defects lower the resistance of the metal based contact with the substrate.
    Type: Application
    Filed: January 19, 2012
    Publication date: July 25, 2013
    Applicants: NANYANG TECHNOLOGICAL UNIVERSITY, GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Dexter Xueming TAN, Yoke King CHIN, Kin Leong PEY
  • Patent number: 8492295
    Abstract: A semiconductor structure fabrication method. A provided structure includes: a semiconductor substrate, a transistor on the semiconductor substrate, N interconnect layers on the semiconductor substrate, and a temporary filling region within the N layers. N is at least 2. The temporary filling region is heated at a high temperature sufficiently high to result in the temporary filling material being replaced by a cooling pipes system that does not include any solid or liquid material. A first portion and a second portion of the cooling pipes system are each in direct physical contact with a surrounding ambient at a first interface and a second interface respectively such that a first direction perpendicular to the first interface is perpendicular to a second direction perpendicular to the second interface. A totality of interfaces between the cooling pipes system and the ambient consists of the first interface and the second interface.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kaushik A. Kumar, Andres Fernando Munoz, Michael Ray Sievers, Richard Stephen Wise
  • Publication number: 20130164948
    Abstract: A method of improving temperature uniformity across a wafer or substrate is provided. The inventors have discovered that thermal radiation reflected from the showerhead injector affects the temperature uniformity across the wafer. Temperature uniformity across the wafer, particularly from the center to edge of the wafer, is improved by controlling the reflected energy from the showerhead. Control of the reflected energy from the showerhead is achieved by a variety of means, including changing the emissivity of the showerhead, creating different zones of emissivity of the showerhead, selectively heating the showerhead, varying the distance between the showerhead and the wafer, and increasing reflectivity of the showerhead in selected regions by employing an ring configured to emit thermal radiation to the showerhead which is then reflected back to the wafer.
    Type: Application
    Filed: December 22, 2011
    Publication date: June 27, 2013
    Applicant: Intermolecular, Inc.
    Inventors: Martin Romero, Jason Wright
  • Publication number: 20130137261
    Abstract: A dielectric layer having features etched thereon and a low dielectric constant, and that is carried by a semiconductor substrate. The etched dielectric layer is modified so its surface energy is reduced by at least one of: (a) applying thermal energy to the layer to cause the layer temperature to be between 100 C and 400 C; (b) irradiating the layer with electromagnetic energy; and/or (c) irradiating the layer with free ions.
    Type: Application
    Filed: November 29, 2011
    Publication date: May 30, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Joung-Wei LIOU, Chung-Chi KO, Chia-Cheng CHOU, Keng-Chu LIN
  • Publication number: 20130122723
    Abstract: An ultraviolet treatment method is provided for a metal oxide electrode. A metal oxide electrode is exposed to an ultraviolet (UV) light source in a humid environment. The metal oxide electrode is then treated with a moiety having at least one anchor group, where the anchor group is a chemical group capable of promoting communication between the moiety and the metal oxide electrode. As a result, the moiety is bound to the metal oxide electrode. In one aspect the metal oxide electrode is treated with a photoactive moiety. Exposing the metal oxide electrode to the UV light source in the humid environment induces surface defects in the metal oxide electrode in the form of oxygen vacancies. In response to the humidity, atmospheric water competes favorably with oxygen for dissociative adsorption on the metal oxide electrode surface, and hydroxylation of the metal oxide electrode surface is induced.
    Type: Application
    Filed: November 14, 2011
    Publication date: May 16, 2013
    Inventors: Sean Andrew VAIL, David R. EVANS, Wei PAN, Jong-Jan LEE
  • Publication number: 20130122611
    Abstract: The present invention generally relates to methods of controlling UV lamp output to increase irradiance uniformity. The methods generally include determining a baseline irradiance within a chamber, determining the relative irradiance on a substrate corresponding to a first lamp and a second lamp, and determining correction or compensation factors based on the relative irradiances and the baseline irradiance. The lamps are then adjusted via closed loop control using the correction or compensation factors to individually adjust the lamps to the desired output. The lamps may optionally be adjusted to equal irradiances prior to adjusting the lamps to the desired output. The closed loop control ensures process uniformity from substrate to substrate. The irradiance measurement and the correction or compensation factors allow for adjustment of lamp set points due to chamber component degradation, chamber component replacement, or chamber cleaning.
    Type: Application
    Filed: November 5, 2012
    Publication date: May 16, 2013
    Inventors: YAO-HUNG YANG, Abhijit Kangude, Sanjeev Baluja, Michael Martinelli, Liliya Krivulina, Thomas Nowak, Juan Carlos Rocha-Alvarez, Scott A. Hendrickson
  • Publication number: 20130115763
    Abstract: The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 9, 2013
    Applicant: ASM INTERNATIONAL. N.V.
    Inventor: ASM International. N.V.
  • Publication number: 20130105801
    Abstract: Display substrates including a capacitor, methods of repairing a display substrate, and display devices including the display substrate are disclosed. In one embodiment, the capacitor includes a first electrode layer, a dielectric layer, and a second electrode layer sequentially stacked. A portion of the second electrode layer is shorted to the first electrode layer. An opening penetrates the second electrode layer to expose a top surface of the dielectric layer. Due to the opening, the shorted portion is separated from the surrounding portions of the second electrode layer. The opening may be formed by irradiating a laser.
    Type: Application
    Filed: April 16, 2012
    Publication date: May 2, 2013
    Applicant: Samsung Mobile Display Co., Ltd.
    Inventors: Yul Kyu Lee, Sun Park, Joon Hoo Choi
  • Patent number: 8431419
    Abstract: A semiconductor growth system includes a chamber and a source of electromagnetic radiation. A detector is arranged to detect absorption of radiation from the source by a chloride- based chemical of the reaction chamber. A control system controls the operation of the chamber in response to the absorption of radiation by the chloride-based chemical. The control system controls the operation of the chamber by adjusting a parameter of the reaction chamber.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: April 30, 2013
    Assignee: Soitec
    Inventors: Ronald Thomas Bertram, Jr., Chantal Arena, Christiaan J. Werkhoven, Michael Albert Tischler, Vasil Vorsa, Andrew D. Johnson
  • Patent number: 8426297
    Abstract: A method of manufacturing a silicon wafer, an oxygen concentration in a surface layer to be maintained more than a predetermined value while promoting a defect-free layer. Strength of the surface layer can be made higher than that of an ordinary annealed sample as a COP free zone is secured. A method of manufacturing a silicon wafer doped with nitrogen and oxygen, includes growing a single crystal silicon doped with the nitrogen by Czochralski method, slicing the grown single crystal silicon to obtain a single crystal silicon wafer; heat treating the sliced single crystal silicon wafer in an ambient gas including a hydrogen gas and/or an inert gas; polishing the heat treated single crystal silicon wafer, after the heat treatment, such that an obtained surface layer from which COP defects have been removed by the heat treatment is polished away until an outermost surface has a predetermined oxygen concentration.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: April 23, 2013
    Assignee: Sumco Techxiv Corporation
    Inventor: Shinya Sadohara
  • Patent number: 8426262
    Abstract: In sophisticated semiconductor devices, an efficient adjustment of an intrinsic stress level of dielectric materials, such as contact etch stop layers, may be accomplished by selectively exposing the dielectric material to radiation, such as ultraviolet radiation. Consequently, different stress levels may be efficiently obtained without requiring sophisticated stress relaxation processes based on ion implantation, which typically leads to significant device failures.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: April 23, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Uwe Griebenow, Roman Boschke
  • Patent number: 8426285
    Abstract: An ion implantation is performed to implant ions into a silicon substrate, and a microwave irradiation is performed to irradiate the silicon substrate with microwaves after the ion implantation. After the microwave irradiation, the silicon substrate is transferred to a heat-treatment apparatus, where the silicon substrate is treated with heat by being irradiated with light having a pulse width ranging from 0.1 milliseconds to 100 milliseconds, both inclusive.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: April 23, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Yoshino, Kiyotaka Miyano, Tomonori Aoyama
  • Publication number: 20130078822
    Abstract: First flash irradiation from flash lamps is performed on an upper surface of a semiconductor wafer supported on a temperature equalizing ring of a holder to cause the semiconductor wafer to jump up from the temperature equalizing ring into midair. While the semiconductor wafer is in midair above the temperature equalizing ring, second flash irradiation from the flash lamps is performed on the upper surface of the semiconductor wafer to increase the temperature of the upper surface of the semiconductor wafer to a treatment temperature. Cracking in the semiconductor wafer is prevented because the second flash irradiation is performed while the semiconductor wafer is in midair and subject to no restraints.
    Type: Application
    Filed: September 5, 2012
    Publication date: March 28, 2013
    Inventor: Kenichi Yokouchi
  • Publication number: 20130078823
    Abstract: A method of manufacturing a semiconductor device including: mounting a substrate on a substrate mounting member that is disposed in a reaction container; heating the substrate at a predetermined processing temperature and supplying a first gas and a second gas to the substrate to process the substrate; stopping supply of the first gas and the second gas, and supplying an inert gas into the reaction container; and unloading the substrate to outside the reaction container.
    Type: Application
    Filed: September 25, 2012
    Publication date: March 28, 2013
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventor: Hitachi Kokusai Electric Inc.
  • Publication number: 20130075868
    Abstract: Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming a generally planar weakened zone within the first donor structure defined by implanted ions therein. At least one of a concentration of the implanted ions and an elemental composition of the implanted ions may be formed to vary laterally across the generally planar weakened zone. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods.
    Type: Application
    Filed: September 27, 2011
    Publication date: March 28, 2013
    Applicant: SOITEC
    Inventors: Mariam Sadaka, Ionut Radu
  • Patent number: 8394703
    Abstract: When the single crystal semiconductor layer is melted, the outward diffusion of oxygen is promoted. Specifically, an SOI substrate is formed in such a manner that an SOI structure having a bonding layer including oxygen provided over a base substrate and a single crystal semiconductor layer provided over the bonding layer including oxygen is formed, and part of the single crystal semiconductor layer is melted by irradiation with a laser beam in a state that the base substrate is heated at a temperature of higher than or equal to 500° C. and lower than a melting point of the base substrate.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: March 12, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Ohnuma, Junpei Momo, Shunpei Yamazaki