Abstract: The present invention is aimed at radiating a linear light beam without distortion regardless of an incident angle of the scanning light beam in an optical module that irradiates a target object with a light beam and detects the reflected light. In an optical module of the present invention, an optical scanning unit (150) causes the light beam to scan in a predetermined direction (perpendicular direction). An optical conversion unit (161) converts the scanning light beam into a linear light beam in a linear direction (horizontal direction) substantially orthogonal to the scanning direction. A light detection unit (180) detects reflected light, which is the linear light beam reflected from a target object.

Abstract: Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

Abstract: The present invention provides a method of manufacturing a graphene transistor 101, the method comprising: (a) providing a substrate having a substantially flat surface, wherein the surface comprises an insulating region 110 and an adjacent semiconducting region 105; (b) forming a graphene layer structure 115 on the surface, wherein the graphene layer structure is disposed on and across a portion of both the insulating region and the adjacent semiconducting region; (c) forming a layer of dielectric material 120 on a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and (d) providing: a source contact 125 on a portion of the graphene layer structure which is itself disposed on the insulating region 110; a gate contact 130 on the layer of dielectric material 120 and above a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and a drain contact 135 on the semiconducting region 105 of the substrate surface.

Abstract: A semiconductor device includes: an N? drift layer of a first conductivity type formed in the semiconductor substrate; a P base layer formed on the N? drift layer; and an N buffer layer of the first conductivity type formed under the N? drift layer and higher in peak impurity concentration than the N? drift layer. The N buffer layer includes: a first buffer layer in which a trap level derived from lattice defect is not detected by a photoluminescence method; and a second buffer layer provided between the first buffer layer and the N? drift layer and in which two types of trap levels derived from lattice defect are detected by the photoluminescence method.

Abstract: A method of manufacturing a semiconductor device packaging panel is provided. The method includes forming a panel having an active side and a backside. The panel includes a plurality of semiconductor die encapsulated with an encapsulant. An active surface of the semiconductor die is exposed on the active side of the panel. A warpage control carrier is attached onto the backside of the panel. The warpage control carrier includes an electroactive element configured for substantially flattening the panel while a control voltage is applied to the electroactive element.

Abstract: A semiconductor device includes a semiconductor substrate, a transistor section, a diode section, and a boundary section provided between the transistor section and the diode section in the semiconductor substrate. The transistor section has gate trench portions which are provided from an upper surface of the semiconductor substrate to a position deeper than that of an emitter region, and to each of which a gate potential is applied. An upper-surface-side lifetime reduction region is provided on the upper surface side of the semiconductor substrate in the diode section and a partial region of the boundary section, and is not provided in a region that is overlapped with the gate trench portion in the transistor section in a surface parallel to the upper surface of the semiconductor substrate.

Abstract: Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.

Abstract: A new method for fabricating a semiconductor device with high selection phosphoric acid solution and eliminating the step of oxide removal and thus reducing oxide loss to improve yield gain and cost saving.

Abstract: Provided is a method of accurately predicting the thermal donor formation behavior in a silicon wafer, a method of evaluating a silicon wafer using the prediction method, and a method of producing a silicon wafer using the evaluation method. The method of predicting the formation behavior of thermal donors, includes: a first step of setting an initial oxygen concentration condition before performing heat treatment on the silicon wafer for reaction rate equations based on both a bond-dissociation model of oxygen clusters associated with the diffusion of interstitial oxygen and a bonding model of oxygen clusters associated with the diffusion of oxygen dimers; a second step of calculating the formation rate of oxygen clusters formed through the heat treatment using the reaction rate equations; and a third step of calculating the formation rate of thermal donors formed through the heat treatment based on the formation rate of the oxygen clusters.

Abstract: Described herein is a technique capable of heating a substrate uniformly by electromagnetic waves. According to one aspect of the technique, there is provided a substrate processing apparatus including: a process chamber where a substrate is processed; a heating device configured to heat the substrate by electromagnetic waves; a gas supply mechanism including a hydrogen-containing gas supply system configured to supply a hydrogen-containing gas into the process chamber; a plasma generator configured to excite the hydrogen-containing gas by plasma; and a controller configured to control the heating device, the gas supply mechanism and the plasma generator to modify the substrate by performing: (a) adding hydrogen atom to a surface of the substrate by supplying the hydrogen-containing gas excited by the plasma generator onto the substrate; and (b) intermittently supplying the electromagnetic waves to heat the substrate after performing (a).

Abstract: A multi-mode thin film deposition apparatus including a reaction chamber, a carrying seat, a showerhead, an inert gas supplying source, a first gas inflow system and a second gas inflow system is provided. The carrying seat is disposed in the reaction chamber. The showerhead has a gas mixing room and gas holes disposed at a side of the gas mixing room. The gas mixing room is connected to the reaction chamber through the plurality of gas holes which faces the carrying seat. The first gas inflow system is connected to the reaction chamber and supplies a first process gas during a first thin film deposition process mode. The inert gas supplying source is connected to the gas mixing room for supplying an inert gas. The second gas inflow system is connected to the gas mixing room to supply a second process gas during a second thin film deposition process mode.

Abstract: A MEMS device with movable MEMS structure and electrodes is produced by fabricating electrodes and shielding the electrodes with diamond buttons during subsequent fabrication steps, such as the etching of sacrificial oxide using vapor HF. In some embodiments, the diamond buttons are removed after the movable MEMS structure is released.

Abstract: The present invention provides an organic light-emitting diode, which includes a light-transmitting substrate, an anode arranged on the light-transmitting substrate, a hole transporting layer arranged on the anode, a light emission layer arranged on the hole transporting layer, an electron transporting layer arranged on the light emission layer, and a cathode arranged on the electron transporting layer. The light emission layer includes a color light emission layer and an ultraviolet light emission layer spaced from the color light emission layer. The present invention integrates functions of color displaying and ultraviolet source together to allow the color displaying and the ultraviolet source to be simultaneously or individually activated.

Abstract: Provided are a method of manufacturing a group-III nitride semiconductor light-emitting device in which a light-emitting device excellent in the internal quantum efficiency and the light extraction efficiency can be obtained, a group-III nitride semiconductor light-emitting device and a lamp. Included are an epitaxial step of forming a semiconductor layer (30) so as to a main surface (20) of a substrate (2), a masking step of forming a protective film on the semiconductor layer (30), a semiconductor layer removal step of removing the protective film and the semiconductor layer (30) by laser irradiation to expose the substrate (2), a grinding step of reducing the thickness of the substrate (2), a polishing step of polishing the substrate (2), a laser processing step of providing processing marks to the inside of the substrate (2), a division step of creating a plurality of light-emitting devices (1) while forming a division surface of the substrate (2) to have a rough surface.

Abstract: A method for forming a device is disclosed. A substrate with a contact region is provided. Vacancy defects are formed in the substrate. The vacancy defects have a peak concentration at a depth DV. A metal based contact is formed in the contact region. The metal based contact has a depth DC which is equal to about DV. The vacancy defects lower the resistance of the metal based contact with the substrate.

Abstract: A method of fabricating a nanoimprint lithography template includes installing a reticle on a reticle stage of scanning lithography equipment having a light source, the reticle stage and a template stage, mounting a template substrate on the template stage, and scanning the template substrate with light from the light source in an exposure process in which the light passes through the reticle and impinges the template substrate at an oblique angle of incidence.

Abstract: Systems and methods for semiconductor device PN junction fabrication are provided. In one embodiment, a method for fabricating an electrical device having a P-N junction comprises: depositing a layer of amorphous semiconductor material onto a crystalline semiconductor base, wherein the crystalline semiconductor base comprises a crystalline phase of a same semiconductor as the amorphous layer; and growing the layer of amorphous semiconductor material into a layer of crystalline semiconductor material that is epitaxially matched to the lattice structure of the crystalline semiconductor base by applying an optical energy that penetrates at least the amorphous semiconductor material.

Abstract: A thin wafer handling structure includes a semiconductor wafer, a release layer that can be released by applying energy, an adhesive layer that can be removed by a solvent, and a carrier, where the release layer is applied on the carrier by coating or laminating, the adhesive layer is applied on the semiconductor wafer by coating or laminating, and the semiconductor wafer and the carrier is bonded together with the release layer and the adhesive layer in between. The method includes applying a release layer on a carrier, applying an adhesive layer on a semiconductor wafer, bonding the carrier and the semiconductor wafer, releasing the carrier by applying energy on the release layer, e.g. UV or laser, and cleaning the semiconductor's surface by a solvent to remove any residue of the adhesive layer.

Abstract: A semiconductor device manufacturing method includes loading a substrate, on which a high-k film is formed, into a processing chamber, performing a reforming process by heating the high-k film through irradiation of a microwave on the substrate, and unloading the substrate from the processing chamber.

Abstract: A substrate processing method for forming a space extending along a predetermined line in a silicon substrate includes a first step of converging a laser light which is an elliptically-polarized light having an ellipticity other than 1 at the substrate so as to form a plurality of modified spots within the substrate along the line and produce a modified region including the modified spots, and a second step of anisotropically etching the substrate so as to advance an etching selectively along the modified region and form the space in the substrate. In the first step, the light is converged at the substrate such that a moving direction of the light with respect to the substrate and a direction of polarization of the light form an angle of 45° or greater therebetween, and the modified spots are made align in one row along the line.

Abstract: A method for improving the quality of a SiC layer by effectively reducing or eliminating the carrier trapping centers in the as-grown SiC crystal. The method includes the steps of: (a) carrying out ion implantation of carbon atoms, silicon atoms, hydrogen atoms, or helium atoms into a shallow surface layer of the SiC crystal layer to introduce carbon interstitials into the surface layer, and (b) growing the SiC layer upward from the edge face of the surface layer into which the carbon interstitials have been introduced, and diffusing out the carbon interstitials that have been introduced into the surface layer from the surface layer into the grown layer and combining the carbon interstitials and point defects to make the electrically active point defects in the grown layer inactive.

Abstract: An oxide including indium (In), gallium (Ga) and zinc (Zn), wherein diffraction peaks are observed at positions corresponding to incident angles (2?) of 7.0° to 8.4°, 30.6° to 32.0°, 33.8° to 35.8°, 53.5° to 56.5° and 56.5° to 59.5° in an X-ray diffraction measurement (CuK? rays), and one of diffraction peaks observed at positions corresponding to incident angles (2?) of 30.6° to 32.0° and 33.8° to 35.8° is a main peak and the other is a sub peak.

Abstract: A manufacturing method of laser processed parts in which at least a pressure-sensitive adhesive layer is provided on a base material as a pressure-sensitive adhesive sheet for laser processing, using a material having specified physical properties. This method comprises adhering the pressure-sensitive adhesive sheet for laser processing to the laser beam exit side of the work by way of the pressure-sensitive adhesive layer, processing the work by irradiating the work with a laser beam of within 2 times of the irradiation intensity for forming a through-hole in the work, at higher than the irradiation intensity of threshold for inducing ablation of the work, and peeling the pressure-sensitive adhesive sheet for laser processing from the work after the machining. Therefore, contamination of the work surface by decomposition products can be effectively suppressed, and laser processed parts can be manufactured easily and at high production efficiency.

Abstract: Molecular layer deposition of silicon carbide is described. A deposition precursor includes a precursor molecule which contains silicon, carbon and hydrogen. Exposure of a surface to the precursor molecule results in self-limited growth of a single layer. Though the growth is self-limited, the thickness deposited during each cycle of molecular layer deposition involves multiple “atomic” layers and so each cycle may deposit thicknesses greater than typically found during atomic layer depositions. Precursor effluents are removed from the substrate processing region and then the surface is irradiated before exposing the layer to the deposition precursor again.

Abstract: A method for forming an integrated circuit (IC) including a silicide block poly resistor (SIBLK poly resistor) includes forming a dielectric isolation region in a top semiconductor surface of a substrate. A polysilicon layer is formed including patterned resistor polysilicon on the dielectric isolation region and gate polysilicon on the top semiconductor surface. Implanting is performed using a first shared metal-oxide-semiconductor (MOS)/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon and gate polysilicon of a MOS transistor with at least a first dopant. Implanting is then performed using a second shared MOS/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon, gate polysilicon and source and drain regions of the MOS transistor with at least a second dopant. A metal silicide is formed on a first and second portion of a top surface of the patterned resistor polysilicon to form the SIBLK poly resistor.

Abstract: A method for manufacturing a semiconductor device includes irradiating light to an effective region of a semiconductor substrate. A wavelength of the light is a wavelength adapted so that light absorptance of the semiconductor substrate increases if an intensity of the light increases. The light is irradiated so that a focus point of the light is made within the semiconductor substrate in the irradiating.

Abstract: A substrate processing method for forming a space extending along a predetermined line in a silicon substrate includes a first step of converging a laser light which is an elliptically-polarized light having an ellipticity other than 1 at the substrate so as to form a plurality of modified spots within the substrate along the line and construct a modified region including the modified spots, and a second step of anisotropically etching the substrate so as to advance an etching selectively along the modified region and form the space in the substrate. In the first step, the light is converged at the substrate such that a moving direction of the light with respect to the substrate and a direction of polarization of the light form an angle of less than 45° therebetween, and the modified spots are made align in a plurality of rows along the line.

Abstract: One aspect of the present invention is a method of making an electronic device. According to one embodiment, the method comprises depositing a cap layer containing at least one dopant onto a gapfill metal and annealing so that the at least one dopant migrates to grain boundaries and/or interfaces of the gapfill metal. Another aspect of the present invention is an electronic device.

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a first cavity within a substrate. The first cavity is disposed under a portion of the substrate. The method further includes forming a first pillar within the first cavity to support the portion of the substrate.

Abstract: A laser processing method of converging laser light into an object to be processed made of silicon so as to form a modified region and etching the object along the modified region so as to form the object with a through hole comprises a laser light converging step of converging the laser light at the object so as to form the modified region along a part corresponding to the through hole in the object; an etch resist film producing step of producing an etch resist film resistant to etching on an outer surface of the object after the laser light converging step; and an etching step of etching the object so as to advance the etching selectively along the modified region and form the through hole after the etch resist film producing step; while the laser light converging step exposes the modified region to the outer surface of the object.

Abstract: A replacement channel and a method for forming the same in a semiconductor device are provided. A channel area is defined in a substrate which is a surface of a semiconductor wafer or a structure such as a fin formed over the wafer. Portions of the channel region are removed and are replaced with a replacement channel material formed by an epitaxial growth/deposition process to include a first dopant concentration level less than a first dopant concentration level. A subsequent doping operation or operations is then used to boost the average dopant concentration to a level greater than the first dopant concentration level. The replacement channel material is formed to include a gradient in which the upper portion of the replacement channel material has a greater dopant concentration than the lower portion of replacement channel material.

Abstract: A plasma processing apparatus includes a process chamber, a platen for supporting a workpiece, a source configured to generate a plasma in the process chamber, and an insulating modifier. The insulating modifier has a gap, and a gap plane, where the gap plane is defined by portions of the insulating modifier closest to the sheath and proximate the gap. A gap angle is defined as the angle between the gap plane and a plane defined by the front surface of the workpiece. Additionally, a method of having ions strike a workpiece is disclosed, where the range of incident angles of the ions striking the workpiece includes a center angle and an angular distribution, and where the use of the insulating modifier creates a center angle that is not perpendicular to the workpiece.

Abstract: A multi-step system and method for curing a dielectric film in which the system includes a drying system configured to reduce the amount of contaminants, such as moisture, in the dielectric film. The system further includes a curing system coupled to the drying system, and configured to treat the dielectric film with ultraviolet (UV) radiation and infrared (IR) radiation in order to cure the dielectric film.

Abstract: One or more heating elements are disposed on a semiconductor substrate proximate a temperature sensitive circuit disposed on the substrate (e.g., bandgap circuit, oscillator). The heater element(s) can be controlled to heat the substrate and elevate the temperature of the circuit to one or more temperature points. One or more temperature measurements can be made at each of the one or more temperature points for calibrating one or more reference values of the circuit (e.g., bandgap voltage).

Abstract: Disclosed is a method for removing individual layers of a layer stack. The layer stack includes a semiconductor layer disposed onto an optically dense electrically conductive layer which in turn is disposed upon an optically transparent layer. A laser at a first power level is projected through the optically transparent layer and onto the optically dense electrically conductive layer. The semiconductor layer is removed through heat evaporation imparted by the laser at the first power level without removing the optically dense electrically conductive layer. Optionally, the laser at a second power level, which is greater than the first power level, is projected onto the optically dense electrically conductive layer through the optically transparent layer. The optically dense electrically conductive layer is removed through heat evaporation imparted by the laser at the second power level without removing the optically transparent layer.

Abstract: Various embodiments disclosed include methods of performing a double exposure process on a level of an integrated circuit (IC) chip to form an IC chip having an embedded electrically measurable identifier. In some cases, the method includes: exposing a level of an integrated circuit (IC) chip using a first mask orientation; subsequently exposing the level of the IC chip using a second mask orientation distinct from the first mask orientation; and developing the level of the IC chip to form an electrically measurable identifier on the IC chip.

Abstract: A method of orienting a semiconductor wafer. The method includes rotating a wafer about a central axis; exposing a plurality of edge portions of the rotating wafer to light having a predetermined wavelength from one or more light sources; detecting a subsurface mark in one of the plurality of edge portions of the rotating wafer; and orienting the wafer using the detected subsurface mark as a reference.

Abstract: MOSFETs having localized stressors are provided. The MOSFET has a stress-inducing layer formed in the source/drain regions, wherein the stress-inducing layer comprises a first semiconductor material and a second semiconductor material. A treatment is performed on the stress-inducing layer such that a reaction is caused with the first semiconductor material and the second semiconductor material is forced lower into the stress-inducing layer. The stress-inducing layer may be either a recessed region or non-recessed region. A first method involves forming a stress-inducing layer, such as SiGe, in the source/drain regions and performing a nitridation or oxidation process. A nitride or oxide film is formed in the top portion of the stress-inducing layer, forcing the Ge lower into the stress-inducing layer. Another method embodiment involves forming a reaction layer over the stress-inducing layer and performing a treatment process to cause the reaction layer to react with the stress-inducing layer.

Abstract: An apparatus for annealing a substrate includes a substrate stage having a substrate mounting portion configured to mount the substrate; a heat source having a plurality of heaters disposed under the substrate mounting portion, the heaters individually preheating a plurality areas defined laterally in the substrate through a bottom surface of the substrate; and a light source facing a top surface of the substrate, configured to irradiate a pulsed light at a pulse width of about 0.1 ms to about 100 ms on the entire top surface of the substrate.

Abstract: A method for fabricating a semiconductor device, according to the present invention includes the steps of: preparing an SOI substrate, which comprises a semiconductor supporting layer, an oxide layer formed on the semiconductor supporting layer and an SOI layer formed on the oxide layer; forming a semiconductor device on the SOI layer; forming a passivation layer over the SOI substrate, the passivation layer allowing a UV light to pass through it; and applying a UV light to the SOI substrate after the step of forming the semiconductor device is completed.

Abstract: A method for manufacturing the compound semiconductor substrate having a reduced dislocation density at an interface between a Si substrate. Contaminants, such as organic matter and metal, on a surface of a Si substrate are removed whereby a flat oxide film is formed. The oxide film on the surface is removed by using an aqueous hydrogen fluoride solution, whereby hydrogen termination treatment is performed. Immediately after being subjected to the hydrogen termination treatment the temperature of the Si substrate is raised in a vacuum apparatus. If the substrate temperature is raised without any operation, the termination hydrogen is released. Before the hydrogen is released, pre-irradiation with As is performed. Thus, an interface between the Si substrate and the compound semiconductor layer is prepared. Several minutes later, irradiation with Ga and As is performed. Thereby, the compound semiconductor is formed.

Abstract: When forming a metal silicide within contact openings in complex semiconductor devices, a silicidation of sidewall surface areas of the contact openings may be initiated by forming a silicon layer therein, thereby reducing unwanted diffusion of the refractory metal species into the laterally adjacent dielectric material. In this manner, superior reliability and electrical performance of the resulting contact elements may be achieved on the basis of a late silicide process.

Abstract: One aspect of the present invention is a method of making an electronic device. According to one embodiment, the method comprises depositing a cap layer containing at least one dopant onto a gapfill metal and annealing so that the at least one dopant migrates to grain boundaries and/or interfaces of the gapfill metal. Another aspect of the present invention is an electronic device.

Abstract: Laser annealing scanning methods that result in reduced annealing non-uniformities in semiconductor device structures under fabrication are disclosed. The methods include defining a length of an annealing laser beam such that the tails of the laser beam resided only within scribe lines that separate the semiconductor device structures. The annealing laser beam tails from adjacent scan path segments can overlap or not overlap within the scribe lines. The cross-scan length of the annealing laser beam can be selected to simultaneously scan more than one semiconductor device structure, as long as annealing laser beam is configured such that the tails do not fall within a semiconductor device structure.

Abstract: A method for forming a device is disclosed. A substrate with a contact region is provided. Vacancy defects are formed in the substrate. The vacancy defects have a peak concentration at a depth DV. A metal based contact is formed in the contact region. The metal based contact has a depth DC which is equal to about DV. The vacancy defects lower the resistance of the metal based contact with the substrate.

Abstract: A semiconductor structure fabrication method. A provided structure includes: a semiconductor substrate, a transistor on the semiconductor substrate, N interconnect layers on the semiconductor substrate, and a temporary filling region within the N layers. N is at least 2. The temporary filling region is heated at a high temperature sufficiently high to result in the temporary filling material being replaced by a cooling pipes system that does not include any solid or liquid material. A first portion and a second portion of the cooling pipes system are each in direct physical contact with a surrounding ambient at a first interface and a second interface respectively such that a first direction perpendicular to the first interface is perpendicular to a second direction perpendicular to the second interface. A totality of interfaces between the cooling pipes system and the ambient consists of the first interface and the second interface.

Abstract: A method of improving temperature uniformity across a wafer or substrate is provided. The inventors have discovered that thermal radiation reflected from the showerhead injector affects the temperature uniformity across the wafer. Temperature uniformity across the wafer, particularly from the center to edge of the wafer, is improved by controlling the reflected energy from the showerhead. Control of the reflected energy from the showerhead is achieved by a variety of means, including changing the emissivity of the showerhead, creating different zones of emissivity of the showerhead, selectively heating the showerhead, varying the distance between the showerhead and the wafer, and increasing reflectivity of the showerhead in selected regions by employing an ring configured to emit thermal radiation to the showerhead which is then reflected back to the wafer.

Abstract: A dielectric layer having features etched thereon and a low dielectric constant, and that is carried by a semiconductor substrate. The etched dielectric layer is modified so its surface energy is reduced by at least one of: (a) applying thermal energy to the layer to cause the layer temperature to be between 100 C and 400 C; (b) irradiating the layer with electromagnetic energy; and/or (c) irradiating the layer with free ions.

Abstract: An ultraviolet treatment method is provided for a metal oxide electrode. A metal oxide electrode is exposed to an ultraviolet (UV) light source in a humid environment. The metal oxide electrode is then treated with a moiety having at least one anchor group, where the anchor group is a chemical group capable of promoting communication between the moiety and the metal oxide electrode. As a result, the moiety is bound to the metal oxide electrode. In one aspect the metal oxide electrode is treated with a photoactive moiety. Exposing the metal oxide electrode to the UV light source in the humid environment induces surface defects in the metal oxide electrode in the form of oxygen vacancies. In response to the humidity, atmospheric water competes favorably with oxygen for dissociative adsorption on the metal oxide electrode surface, and hydroxylation of the metal oxide electrode surface is induced.

Abstract: The present invention generally relates to methods of controlling UV lamp output to increase irradiance uniformity. The methods generally include determining a baseline irradiance within a chamber, determining the relative irradiance on a substrate corresponding to a first lamp and a second lamp, and determining correction or compensation factors based on the relative irradiances and the baseline irradiance. The lamps are then adjusted via closed loop control using the correction or compensation factors to individually adjust the lamps to the desired output. The lamps may optionally be adjusted to equal irradiances prior to adjusting the lamps to the desired output. The closed loop control ensures process uniformity from substrate to substrate. The irradiance measurement and the correction or compensation factors allow for adjustment of lamp set points due to chamber component degradation, chamber component replacement, or chamber cleaning.