With High-energy Radiation (epo) Patents (Class 257/E21.331)
  • Patent number: 8859331
    Abstract: Methods of forming an oxide material layer are provided. The method includes mixing a precursor material with a peroxide material to form a precursor solution, coating the precursor solution on a substrate, and baking the coated precursor solution.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: October 14, 2014
    Assignee: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Hyun Jae Kim, Dong Lim Kim, Joohye Jung, You Seung Rim
  • Patent number: 8399342
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of bodies isolated by trenches by etching a substrate, forming a buried bit line gap-filling a portion of each trench, forming an etch stop layer on an upper surface of the buried bit line; and forming a word line extended in a direction crossing the buried bit line over the etch stop layer.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: March 19, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Tae-Kyun Kim
  • Publication number: 20130034970
    Abstract: A method for forming a fluorocarbon layer using a plasma reaction process includes the step of applying a microwave power and an RF bias. The microwave power and the RF bias are applied under a pressure ranging from 20 mTorr to 60 mTorr.
    Type: Application
    Filed: August 2, 2011
    Publication date: February 7, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Hiroyuki Takaba
  • Publication number: 20120319121
    Abstract: A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.
    Type: Application
    Filed: June 1, 2012
    Publication date: December 20, 2012
    Applicant: SOITEC
    Inventors: Patrick Reynaud, Sébastien Kerdiles, Daniel Delprat
  • Publication number: 20120270383
    Abstract: Provided is a method for manufacturing a semiconductor device, in which a degradation of characteristics of a thin film transistor can be suppressed by performing plasma oxidation treatment on a gate insulating film containing nitrogen. An embodiment of the present invention is a method for manufacturing a semiconductor device comprising a thin film transistor including a gate electrode, a gate insulating film containing nitrogen, and a channel region in microcrystalline semiconductor films. The method includes the steps of performing plasma treatment on the gate insulating film in an oxidizing gas atmosphere containing hydrogen and an oxidizing gas containing an oxygen atom, and forming the microcrystalline semiconductor film over the gate insulating film. Formula (1), a/b?2, and Formula (2), b>0, are satisfied, where the amount of hydrogen and the amount of the oxidizing gas in the oxidizing gas atmosphere are a and b, respectively.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 25, 2012
    Applicants: SHARP KABUSHIKI KAISHA, SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kanta ABE, Hidekazu MIYAIRI, Tetsuhiro TANAKA, Takashi IENAGA, Yoshitaka YAMAMOTO
  • Patent number: 8288864
    Abstract: In a microwave module with at least one semiconductor chip, which provides on its upper side a connecting-line structure formed in particular as a coplanar line, which is connected to at least one adjacent incoming and/or outgoing line structure formed on the upper side of the substrate, the chip is glued with its underside and all lateral surfaces, on which no high-frequency connecting lines lead to the chip, within a recess of a metal part with good thermal conduction.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: October 16, 2012
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Werner Perndl, Thomas Reichel
  • Publication number: 20120211879
    Abstract: A manufacturing method of a semiconductor device includes exposing a wiring layer which is formed of an alloy including two or more types of metals having different standard electrode potentials, on one surface side of a semiconductor substrate and performing a plasma process of allowing plasma generated by a mixture gas of a gas including nitrogen and an inert gas or plasma generated by a gas including nitrogen to irradiate a range which includes an exposed surface of the wiring layer.
    Type: Application
    Filed: January 26, 2012
    Publication date: August 23, 2012
    Applicant: Sony Corporation
    Inventors: Kazuto WATANABE, Atsushi MATSUSHITA, Hiroshi HORIKOSHI, Iwao SUGIURA, Yuuji NISHIMURA, Syota YAMABATA
  • Patent number: 8216919
    Abstract: A substrate carrier structure includes a tray and a secondary electron absorbing material. The tray holds a semiconductor substrate having a first surface on which semiconductor device elements are formed. The secondary electron absorbing material is interposed between the tray and this first surface of the semiconductor substrate. When the semiconductor substrate is irradiated with charged particles to form lattice defects, the secondary electron absorbing material prevents unwanted trapping of secondary electrons emitted from the tray, and thereby reduces the variability of electrical characteristics of semiconductor device elements formed on the semiconductor substrate.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: July 10, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Yuichi Kaneko
  • Patent number: 8216922
    Abstract: Plasma doping is performed using a plasma made of a gas containing an impurity which will serve as a dopant. In this case, at least one of plasma generation high-frequency power and biasing high-frequency power is supplied in the form of pulses.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: July 10, 2012
    Assignee: Panasonic Corporation
    Inventors: Shigenori Hayashi, Masafumi Kubota, Yuichiro Sasaki
  • Publication number: 20120164845
    Abstract: The present invention generally provides apparatus and method for processing a substrate. Particularly, the present invention provides apparatus and methods to obtain a desired distribution of a process gas. One embodiment of the present invention provides an apparatus for processing a substrate comprising an injection nozzle having a first fluid path including a first inlet configured to receive a fluid input, and a plurality of first injection ports connected with the first inlet, wherein the plurality of first injection ports are configured to direct a fluid from the first inlet towards a first region of a process volume, and a second fluid path including a second inlet configured to receive a fluid input, and a plurality of second injection ports connected with the second inlet, wherein the second injection ports are configured to direct a fluid from the second inlet towards a second region of the process volume.
    Type: Application
    Filed: March 8, 2012
    Publication date: June 28, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Wei Liu, Johanes S. Swenberg, Hanh D. Nguyen, Son T. Nguyen, Roger Curtis, Philip A. Bottini
  • Patent number: 8207068
    Abstract: Example embodiments relate to a method of fabricating a memory device and a memory device. The method of fabricating a memory device comprises forming a lower electrode and an oxide layer on a lower structure and radiating an energy beam on a region of the oxide layer. The memory device comprises a lower structure and an oxide layer and a lower structure formed on the lower structure, the oxide layer including an electron beam radiation region that received radiation from an electron beam source creating an artificially formed current path through the oxide layer to the lower electrode. A reset current of the memory device may be decreased and stabilized.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: June 26, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-eon Ahn, Hye-young Kim, Byoung-ho Park, Jung-bin Yun, You-seon Kim
  • Patent number: 8138573
    Abstract: An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Ethan H. Cannon, Alvin W. Strong
  • Publication number: 20120064704
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of bodies isolated by trenches by etching a substrate, forming a buried bit line gap-filling a portion of each trench, forming an etch stop layer on an upper surface of the buried bit line; and forming a word line extended in a direction crossing the buried bit line over the etch stop layer.
    Type: Application
    Filed: April 5, 2011
    Publication date: March 15, 2012
    Inventor: Tae-Kyun KIM
  • Publication number: 20110300711
    Abstract: A method of patterning a substrate comprises providing an array of resist features defined by a first pitch and a first gap width between adjacent resist features. Particles are introduced into the array of resist features, wherein the array of resist features becomes hardened. The introduction of particles may cause a reduction in critical dimension of the resist features. Sidewalls are provided on side portions of hardened resist features. Subsequent to the formation of the sidewalls, the hardened resist features are removed, leaving an array of isolated sidewalls disposed on the substrate. The sidewall array provides a mask for double patterning of features in the substrate layers disposed below the sidewalls, wherein an array of features formed in the substrate has a second pitch equal to half that of the first pitch.
    Type: Application
    Filed: August 19, 2010
    Publication date: December 8, 2011
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Patrick M. Martin, Steven Carlson, Choong-Young Oh, Jung-Wook Park
  • Publication number: 20110294306
    Abstract: A method for forming a multi-material thin film includes providing a multi-material donor substrate comprising single crystal silicon and an overlying film comprising GaN or SiC. Energetic particles are introduced through a surface of the multi-material donor substrate to a selected depth within the single crystal silicon. The method includes providing energy to a selected region of the donor substrate to initiate a controlled cleaving action in the donor substrate. Then, a cleaving action is made using a propagating cleave front to free a multi-material film from a remaining portion of the donor substrate, the multi-material film comprising single crystal silicon and the overlying film.
    Type: Application
    Filed: August 10, 2011
    Publication date: December 1, 2011
    Applicant: Silicon Genesis Corporation
    Inventors: Francois J. Henley, Nathan W. Cheung
  • Publication number: 20110230038
    Abstract: Plasma doping is performed using a plasma made of a gas containing an impurity which will serve as a dopant. In this case, at least one of plasma generation high-frequency power and biasing high-frequency power is supplied in the form of pulses.
    Type: Application
    Filed: March 18, 2011
    Publication date: September 22, 2011
    Inventors: Shigenori Hayashi, Masafumi Kubota, Yuichiro Sasaki
  • Patent number: 8003498
    Abstract: Several examples of a method for processing a substrate are disclosed. In a particular embodiment, the method may include: introducing a plurality of first particles to a first region of the substrate so as to form at least one crystal having a grain boundary in the first region without forming another crystal in a second region, the second region adjacent to the first region; and extending the grain boundary of the at least one crystal formed in the first region to the second region after stopping the introducing the plurality of first particles.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: August 23, 2011
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Jonathan G. England, Frank Sinclair, John (Bon-Woong) Koo, Rajesh Dorai, Ludovic Godet
  • Publication number: 20110086518
    Abstract: A method for ashing hardened resist from a photoresist patterned chromium alloy post etch using a plasma ashing chemistry which contains no gaseous source of hydrogen and contains a gaseous source of oxygen and a gaseous source of nitrogen with an oxygen to nitrogen atomic ratio of at least 5.
    Type: Application
    Filed: October 12, 2009
    Publication date: April 14, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Abbas ALI
  • Patent number: 7910458
    Abstract: A method for fabricating free standing thickness of materials using one or more semiconductor substrates, e.g., single crystal silicon, polysilicon, silicon germanium, germanium, group III/IV materials, and others. In a specific embodiment, the present method includes providing a semiconductor substrate having a surface region and a thickness. The method includes subjecting the surface region of the semiconductor substrate to a first plurality of high energy particles provided at a first implant angle generated using a linear accelerator to form a region of a plurality of gettering sites within a cleave region, the cleave region being provided beneath the surface region to defined a thickness of material to be detached, the semiconductor substrate being maintained at a first temperature.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: March 22, 2011
    Assignee: Silicon Genesis Corporation
    Inventor: Francois J. Henley
  • Publication number: 20110031590
    Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a liquid on a region of a die, and then forming an identification mark through the liquid on the die.
    Type: Application
    Filed: August 4, 2009
    Publication date: February 10, 2011
    Inventors: George P. Vakanas, Sergei L. Voronov, Luey Chon Ng, George E. Malouf
  • Patent number: 7879634
    Abstract: A process for easy production of a liquid crystal cell substrate having a TFT driver element which contributes to reducing viewing angle dependence of color of a liquid crystal display device is provided: a process using a transfer material, more preferably, a process which comprises the following steps [1] to [4] in this order: [1] transferring on a TFT substrate a transfer material having a photosensitive polymer layer and an optically anisotropic layer on a temporary support; [2] separating the temporary support from the transfer material on the TFT substrate; [3] subjecting the transfer material to light exposure on the TFT substrate; and [4] removing unnecessary parts of the photosensitive polymer layer and the optically anisotropic layer on the substrate.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: February 1, 2011
    Assignee: FUJIFILM Corporation
    Inventors: Wakahiko Kaneko, Ichiro Amimori, Hideki Kaneiwa
  • Publication number: 20100317140
    Abstract: Embodiments of the present invention relate to the use of a particle accelerator beam to form thin films of material from a bulk substrate. In particular embodiments, a bulk substrate having a top surface is exposed to a beam of accelerated particles. Then, a thin film of material is separated from the bulk substrate by performing a controlled cleaving process along a cleave region formed by particles implanted from the beam. To improve uniformity of depth of implantation, channeling effects are reduced by one or more techniques. In one technique, a miscut bulk substrate is subjected to the implantation, such that the lattice of the substrate is offset at an angle relative to the impinging particle beam. According to another technique, the substrate is tilted at an angle relative to the impinging particle beam. In still another technique, the substrate is subjected to a dithering motion during the implantation. These techniques may be employed alone or in combination.
    Type: Application
    Filed: May 12, 2010
    Publication date: December 16, 2010
    Applicant: Silicon Genesis Corporation
    Inventors: ADAM BRAILOVE, Zuqin Liu, Francois J. Henley, Albert J. Lamm
  • Publication number: 20100273277
    Abstract: Rapid thermal processing systems and associated methods are disclosed herein. In one embodiment, a method for heating a microelectronic substrate include generating a plasma, applying the generated plasma to a surface of the microelectronic substrate, and raising a temperature of the microelectronic substrate with the generated plasma applied to the surface of the microelectronic substrate. The method further includes continuing to apply the generated plasma until the microelectronic substrate reaches a desired temperature.
    Type: Application
    Filed: April 23, 2009
    Publication date: October 28, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Shu Qin
  • Publication number: 20100216264
    Abstract: A method of manufacturing a substrate for a liquid discharge head, the substrate being a silicon substrate having a first surface opposed to a second surface, the method comprising the steps of providing a layer on the second surface of the silicon substrate, wherein the layer has a lower etch rate than silicon when exposed to an etchant of silicon, partially removing the layer so as to expose part of the second surface of the silicon substrate, wherein the exposed part surrounds at least one part of the layer; and wet etching the layer and the exposed part of the second surface of the silicon substrate, using the etchant of silicon, to form a liquid supply port extending from the second surface to the first surface of the silicon substrate.
    Type: Application
    Filed: February 22, 2010
    Publication date: August 26, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Keiji Matsumoto, Shuji Koyama, Hiroyuki Abo, Keiji Watanabe
  • Patent number: 7772595
    Abstract: There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: August 10, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Yih-Der Guo, Chih-Ming Lai, Jenq-Dar Tsay, Po-Chun Liu
  • Publication number: 20100173484
    Abstract: A method of preventing toxic gas formation after an implantation process is disclosed. Certain dopants, when implanted into films disposed on a substrate, may react when exposed to moisture to form a toxic gas and/or a flammable gas. By in-situ exposing the doped film to an oxygen containing compound, dopant that is shallowly implanted into the layer stack reacts to form a dopant oxide, thereby reducing potential toxic gas and/or flammable gas formation. Alternatively, a capping layer may be formed in-situ over the implanted film to reduce the potential generation of toxic gas and/or flammable gas.
    Type: Application
    Filed: March 23, 2010
    Publication date: July 8, 2010
    Inventors: Majeed A. Foad, Manoj Vellaikal, Kartik Santhanam
  • Publication number: 20100167508
    Abstract: A method for introducing impurities includes a step for forming an amorphous layer at a surface of a semiconductor substrate, and a step for forming a shallow impurity-introducing layer at the semiconductor substrate which has been made amorphous, and an apparatus used therefore. Particularly, the step for forming the amorphous layer is a step for irradiating plasma to the surface of the semiconductor substrate, and the step for forming the shallow impurity-introducing layer is a step for introducing impurities into the surface which has been made amorphous.
    Type: Application
    Filed: March 5, 2010
    Publication date: July 1, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Yuichiro Sasaki, Bunji Mizuno, Cheng-Guo Jin
  • Publication number: 20100167509
    Abstract: A method for producing a buried n-doped semiconductor zone in a semiconductor body. In one embodiment, the method includes producing an oxygen concentration at least in the region to be doped in the semiconductor body. The semiconductor body is irradiated via one side with nondoping particles for producing defects in the region to be doped. A thermal process is carried out. The invention additionally relates to a semiconductor component with a field stop zone.
    Type: Application
    Filed: March 8, 2010
    Publication date: July 1, 2010
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Hans-Joachim Schulze, Josef Lutz, Franz-Josef Niedernostheide, Ralf Siemieniec
  • Publication number: 20100159712
    Abstract: A method of modifying the heat transfer coefficient profile of an electrostatic chuck by configuring the areal density of a mesa configuration of an insulating layer of the chuck is provided. A method of modifying the capacitance profile of an electrostatic chuck by adjustment or initial fabrication of the height of a mesa configuration of an insulating layer of the chuck is further provided. The heat transfer coefficient at a given site can be measured by use of a heat flux probe, whereas the capacitance at a given site can be measured by use of a capacitance probe. The probes are placed on the insulating surface of the chuck and may include a plurality of mesas in a single measurement. A plurality of measurements made across the chuck provide a heat transfer coefficient profile or a capacitance profile, from which a target mesa areal density and a target mesa height are determined.
    Type: Application
    Filed: November 30, 2005
    Publication date: June 24, 2010
    Inventor: Robert Steger
  • Patent number: 7727791
    Abstract: A semiconductor layer contains, as a principal constituent, a Group III-V semiconductor compound, which may be represented by the general formula: AlxGayInzN, wherein x represents a number satisfying the condition 0?x<1, y represents a number satisfying the condition 0<y<1, and z represents a number satisfying the condition 0<z<1, with the proviso that x+y+z=1. The semiconductor layer is formed with a laser assisted metalorganic vapor phase epitaxy technique. A semiconductor light emitting device comprises the semiconductor layer and may be constituted as a semiconductor laser or a light emitting diode.
    Type: Grant
    Filed: April 2, 2007
    Date of Patent: June 1, 2010
    Assignee: FUJIFILM Corporation
    Inventor: Hideki Asano
  • Patent number: 7719050
    Abstract: A memory cell comprises a body of a semiconductor material having a first conductivity type. A conductor-filter system includes a first conductor having thermal charge carriers, and a filter contacting the first conductor and including dielectrics for providing a filtering function on the charge carriers of one polarity. The filter includes a first set of electrically alterable potential barriers. A conductor-insulator system includes a second conductor and a first insulator contacting the second conductor at an interface and having a second set of electrically alterable potential barriers. A first region is spaced-apart from the second conductor. A channel of the body is defined therebetween. A second insulator is adjacent to the first region. A charge storage region is disposed in between the first and the second insulators. A word-line has a first portion and a second portion comprising the first conductor disposed over and insulated from the body.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: May 18, 2010
    Inventor: Chih-Hsin Wang
  • Publication number: 20100055882
    Abstract: Methods for producing a junction termination extension surrounding the edge of a cathode or anode junction in a semiconductor substrate, where the junction termination extension has a controlled arbitrary lateral doping profile and a controlled arbitrary lateral width, are provided. A photosensitive material is illuminated through a photomask having a pattern of opaque and clear spaces therein, the photomask being separated from the photosensitive material so that the light diffuses before striking the photosensitive material. After processing, the photosensitive material so exposed produces a laterally tapered implant mask. Dopants are introduced into the semiconductor material and follow a shape of the laterally tapered implant mask to create a controlled arbitrary lateral doping profile and a controlled lateral width in the junction termination extension in the semiconductor.
    Type: Application
    Filed: July 6, 2009
    Publication date: March 4, 2010
    Applicant: The Government of the United States of America, as rpresented by the Secretary of the Navy
    Inventors: Eugene A. Imhoff, Francis J. Kub, Karl D. Hobart
  • Publication number: 20100015818
    Abstract: A method for producing a buried stop zone in a semiconductor body and a semiconductor component having a stop zone, the method including providing a semiconductor body having a first and a second side and a basic doping of a first conduction type. The method further includes irradiating the semiconductor body via one of the sides with protons, as a result of which protons are introduced into a first region of the semiconductor body situated at a distance from the irradiation side. The method also includes carrying out a thermal process in which the semiconductor body is heated to a predetermined temperature for a predetermined time duration, the temperature and the duration being chosen such that hydrogen-induced donors are generated both in the first region and in a second region adjacent to the first region in the direction of the irradiation side.
    Type: Application
    Filed: August 31, 2009
    Publication date: January 21, 2010
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Reiner Barthelmess, Anton Mauder, Franz-Josef Niedernostheide, Hans-Joachim Schulze
  • Publication number: 20090286340
    Abstract: A process for easy production of a liquid crystal cell substrate having a TFT driver element which contributes to reducing viewing angle dependence of color of a liquid crystal display device is provided: a process using a transfer material, more preferably, a process which comprises the following steps [1] to [4] in this order: [1] transferring on a TFT substrate a transfer material having a photosensitive polymer layer and an optically anisotropic layer on a temporary support; [2] separating the temporary support from the transfer material on the TFT substrate; [3] subjecting the transfer material to light exposure on the TFT substrate; and [4] removing unnecessary parts of the photosensitive polymer layer and the optically anisotropic layer on the substrate.
    Type: Application
    Filed: September 15, 2006
    Publication date: November 19, 2009
    Applicant: FUJIFILM CORPORATION
    Inventors: Wakahiko Kaneko, Ichiro Amimori, Hideki Kaneiwa
  • Patent number: 7615466
    Abstract: The invention relates to a process of treating a structure for electronics or optoelectronics, wherein the structure that has a substrate, a dielectric layer having a thermal conductivity substantially higher than thermal conductivity of an oxide layer made of an oxide of a semiconductor material, an oxide layer made of an oxide of the semiconductor material, and a thin semiconductor layer made of the semiconductor material. The process includes a heat treatment of the structure in an inert or reducing atmosphere with a temperature and a duration chosen for inciting an amount of oxygen of the second oxide layer to diffuse through the semiconductor layer so that the thickness of the second oxide layer decreases by a determined value. The invention also relates to a process of manufacturing a structure for electronics or optoelectronics applications through the use of this type of heat treatment.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: November 10, 2009
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventor: Oleg Kononchuk
  • Publication number: 20090258507
    Abstract: In order to solve the problem of contamination caused by static electricity on the surface of a substrate after plasma treatment, the invention provides a substrate treatment device comprising a standby chamber in which is arranged a transfer device for loading a substrate out of/into a cassette rack accommodating a substrate, said substrate treatment device capable of retaining said substrate transferred by the transfer device in a boat and loading, by way of a boat elevator, the boat into/out of a treatment furnace capable of applying plasma treatment to said substrate, wherein a static eliminator for eliminating static electricity of said substrate is arranged in said standby chamber.
    Type: Application
    Filed: March 2, 2007
    Publication date: October 15, 2009
    Inventors: Takeshi Itoh, Kazuyuki Toyoda, Yuji Takebayashi
  • Patent number: 7579654
    Abstract: Systems and methods for and products of a semiconductor-on-insulator (SOI) structure including subjecting at least one unfinished surface to a laser annealing process. Production of the SOI structure further may include subjecting an implantation surface of a donor semiconductor wafer to an ion implantation process to create an exfoliation layer in the donor semiconductor wafer; bonding the implantation surface of the exfoliation layer to an insulator substrate; separating the exfoliation layer from the donor semiconductor wafer, thereby exposing at least one cleaved surface; and subjecting the at least one cleaved surface to the laser annealing process.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: August 25, 2009
    Assignee: Corning Incorporated
    Inventors: James Gregory Couillard, Philippe Lehuede, Sophie A Vallon
  • Publication number: 20090181552
    Abstract: An SOI substrate having a single crystal semiconductor layer the surface of which has high planarity is manufactured. A semiconductor substrate is doped with hydrogen to form a damaged region containing a large amount of hydrogen. After a single crystal semiconductor substrate and a supporting substrate are bonded to each other, the semiconductor substrate is heated to separate the single crystal semiconductor substrate in the damaged region. While a heated high-purity nitrogen gas is sprayed on a separation surface of a single crystal semiconductor layer which is separated from the single crystal semiconductor substrate and irradiation with a microwave is performed from the back side of the supporting substrate, the separation surface is irradiated with a laser beam. The single crystal semiconductor layer is melted by irradiation with the laser beam, so that the surface of the single crystal semiconductor layer is planarized and re-single-crystallization thereof is performed.
    Type: Application
    Filed: January 14, 2009
    Publication date: July 16, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Akihisa Shimomura, Naoki Tsukamoto
  • Publication number: 20090098710
    Abstract: An SOI substrate having a single crystal semiconductor layer with high surface planarity is manufactured. A semiconductor substrate is doped with hydrogen, whereby a damaged region which contains large quantity of hydrogen is formed. After a single crystal semiconductor substrate and a supporting substrate are bonded together, the semiconductor substrate is heated, whereby the single crystal semiconductor substrate is separated in the damaged region. While a heated high-purity nitrogen gas is sprayed on a separation plane of the single crystal semiconductor layer separated from the single crystal semiconductor substrate, laser beam irradiation is performed. By irradiation with a laser beam, the single crystal semiconductor layer is melted, whereby planarity of the surface of the single crystal semiconductor layer is improved and re-single-crystallization is performed.
    Type: Application
    Filed: October 7, 2008
    Publication date: April 16, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20090042369
    Abstract: A method for fabricating free standing thickness of materials using one or more semiconductor substrates, e.g., single crystal silicon, polysilicon, silicon germanium, germanium, group III/IV materials, and others. In a specific embodiment, the present method includes providing a semiconductor substrate having a surface region and a thickness. The method includes subjecting the surface region of the semiconductor substrate to a first plurality of high energy particles provided at a first implant angle generated using a linear accelerator to form a region of a plurality of gettering sites within a cleave region, the cleave region being provided beneath the surface region to defined a thickness of material to be detached, the semiconductor substrate being maintained at a first temperature.
    Type: Application
    Filed: January 25, 2008
    Publication date: February 12, 2009
    Applicant: Silicon Genesis Corporation
    Inventor: Francois J. Henley
  • Patent number: 7410907
    Abstract: A method of fabricating a device using a multi-layered wafer that has an embedded etch mask adapted to map a desired device structure onto an adjacent (poly)silicon layer. Due to the presence of the embedded mask, it becomes possible to delay the etching that forms the mapped structure in the (poly)silicon layer until a relatively late fabrication stage. As a result, flatness of the (poly)silicon layer is preserved for the deposition of any necessary over-layers, which substantially obviates the need for filling the voids created by the structure formation with silicon oxide.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: August 12, 2008
    Assignee: Lucent Technologies Inc.
    Inventor: Dennis S. Greywall
  • Patent number: 7410878
    Abstract: A method of forming a polysilicon film having smooth surface using a lateral growth and a step-and-repeat laser process. Amorphous silicon formed in a first irradiation region of a substrate is crystallized to form a first polysilicon region by a first laser shot. Then, the substrate is moved a predetermined distance, and irradiated by a second laser shot. The polysilicon region is then recrystallized and locally planarized by subsequent laser shots. After multiple repetitions of the irradiation procedure, the amorphous silicon film formed on a substrate is completely transformed into a polysilicon film. The polysilicon film includes lateral growth crystal grains and nano-trenches formed in parallel on the surface of the polysilicon film. A longitudinal direction of the nano-trenches is substantially perpendicular to a lateral growth direction of the crystal grains.
    Type: Grant
    Filed: October 9, 2006
    Date of Patent: August 12, 2008
    Assignee: AU Optronics Corp.
    Inventors: Chih-Wei Gordon Chao, Ming-Wei Sun
  • Publication number: 20080079119
    Abstract: A p-n junction is formed at the interface of a low-concentration n-type impurity layer 3 and a p-type diffusion region 5 in the vicinity of the upper major surface of an n-type semiconductor substrate 2 of a semiconductor device 1. A mask 15 composed of an absorber is placed on the upper major surface of the semiconductor device 1, and electron beams are radiated. Thereafter, heat treatment is conducted. As a result, the peak of the crystal lattice defect densities is present in the vicinity of the upper major surface of the n-type semiconductor substrate 2, and the crystal lattice defect densities are decreasingly distributed toward the lower major surface. Thereby, a semiconductor device that can minimize the variation of the breakdown voltage characteristics of the p-n junction of the diode, and can control the optimum carrier lifetime can be obtained.
    Type: Application
    Filed: February 23, 2007
    Publication date: April 3, 2008
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Masanori INOUE