Abstract: A method of forming an integrated circuit includes forming a gate structure over a semiconductor body, and forming a shadowing structure over the semiconductor body laterally spaced from the gate structure, thereby defining an active area in the semiconductor body therebetween. The method further includes performing an angled implant into the gate structure, wherein the shadowing structure substantially blocks dopant from the angled implant from implanting into the active area, and performing a source/drain implant into the gate structure and the active area.

Abstract: An integrated circuit system that includes: providing a PFET device including a PFET gate and a PFET gate dielectric; forming a source/drain extension from a first epitaxial layer aligned to a first PFET gate sidewall spacer; and forming a source/drain from a second epitaxial layer aligned to a second PFET gate sidewall spacer.

Abstract: Provided is a method for fabricating a semiconductor device. In the method, a poly layer on a semiconductor substrate is etched to a predetermined depth. Ions are implanted into the poly layer at a predetermined angle. The poly layer is etched again to expose a portion of the semiconductor substrate. Therefore, stress is applied to the poly gate instead of the barrier layer, so that the barrier layer is not opened during contact etching because effects of the barrier layer thickness can be solved. Also, stress is applied to a poly gate directly contacting a channel region of the semiconductor substrate to allow tensile force caused by the stress of the poly gate to directly induce tensile force to the channel region, and thus increase mobility, so that device characteristics can be remarkably enhanced.

Abstract: The present invention is related to semiconductor device and method for manufacturing the same. In accordance with the semiconductor device and method for manufacturing the same, at least one opening extending between LDD regions and exposing a buried insulating layer is formed so that a gate electrode surrounds the surface of a channel region. This structure allows the formation of a relatively a thick channel region and decreases the sensitivity of characteristics of the device dependent upon the thickness of the channel region.

Abstract: In one aspect there is provided a method of manufacturing a semiconductor device comprising forming gate electrodes over a semiconductor substrate, forming source/drains adjacent the gate electrodes, depositing a stress inducing layer over the gate electrodes. A laser anneal is conducted on at least the gate electrodes subsequent to depositing the stress inducing layer at a temperature of at least about 1100° C. for a period of time of at least about 300 microseconds, and the semiconductor device is subjected to a thermal anneal subsequent to conducting the laser anneal.

Abstract: The present invention provides a transistor 100 having a germanium implant region 170 located therein, a method of manufacture therefor, and an integrated circuit including the aforementioned transistor. The transistor 100, in one embodiment, includes a polysilicon gate electrode 140 located over a semiconductor substrate 110, wherein a sidewall of the polysilicon gate electrode 140 has a germanium implanted region 170 located therein. The transistor 100 further includes source/drain regions 160 located within the semiconductor substrate 110 proximate the polysilicon gate electrode 140.

Abstract: Aspects of the invention can provide a transistor that can include a supporting substrate, a semiconductor film formed on an underlying insulating film provided on the supporting substrate and including a channel region and source and drain regions, and a gate electrode provided above the channel region. The semiconductor film can include a lightly doped region in which an impurity is injected at a low concentration between the channel region and the source and drain regions. The source and drain regions can include a heavily doped region in which an impurity is injected at a higher concentration than the lightly doped region. At least part of the lightly doped region provided along an inner wall of a groove can be provided on the supporting substrate.

Abstract: A semiconductor structure includes a semiconductor mesa located upon an isolating substrate. The semiconductor mesa includes a first end that includes a first doped region separated from a second end that includes a second doped region by an isolating region interposed therebetween. The first doped region and the second doped region are of different polarity. The semiconductor structure also includes a channel stop dielectric layer located upon a horizontal surface of the semiconductor mesa over the second doped region. The semiconductor structure also includes a first device located using a sidewall and a top surface of the first end as a channel region, and a second device located using the sidewall and not the top surface of the second end as a channel. A related method derives from the foregoing semiconductor structure. Also included is a semiconductor circuit that includes the semiconductor structure.

Abstract: A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer for integrating components of the device, and forming at least one contact trench extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.

Abstract: A method of fabricating a semiconductor transistor device is provided. The fabrication method begins by forming a gate structure overlying a layer of semiconductor material, such as silicon. Then, spacers are formed about the sidewalls of the gate structure. Next, ions of an amorphizing species are implanted into the semiconductor material at a tilted angle toward the gate structure. The gate structure and the spacers are used as an ion implantation mask during this step. The ions form amorphized regions in the semiconductor material. Thereafter, the amorphized regions are selectively removed, resulting in corresponding recesses in the semiconductor material. In addition, the recesses are filled with stress inducing semiconductor material, and fabrication of the semiconductor transistor device is completed.

Abstract: A micro-optic device including a complicate structure and a movable mirror is made to be manufactured in a reduced length of time. A silicon substrate and a single crystal silicon device layer with an intermediate layer of silicon dioxide interposed therebetween defines a substrate on which a layer of mask material is formed and is patterned to form a mask having the same pattern as the configuration of the intended optical device as viewed in plan view. A surface which is to be constricted as a mirror surface is chosen to be in a plane of the silicon crystal. Using the mask, the device layer is vertically etched by a reactive ion dry etching until the intermediate layer is exposed. Subsequently, using KOH solution, a wet etching which is anisotropic to the crystallographic orientation is performed with an etching rate which is on the order of 0.1 ?m/min for a time interval on the order of ten minutes is performed to convert the sidewall surface of the mirror into a smooth crystallographic surface.

Abstract: An integrated semiconductor device containing semiconductor elements that have respective desired on-resistances and breakdown voltages achieves appropriate characteristics as a whole of the integrated semiconductor element. The integrated semiconductor device includes a plurality of semiconductor elements formed in a semiconductor layer and each having a source of an n type semiconductor, a drain of the n type semiconductor and a back gate of a p type semiconductor between the source and the drain. At least a predetermined part of the drain of one semiconductor element and a predetermined part of the drain of another semiconductor element have respective impurity concentrations different from each other.

Abstract: The present invention provides an improved amorphization/templated recrystallization (ATR) method for forming hybrid orientation substrates and semiconductor device structures. A direct-silicon-bonded (DSB) silicon layer having a (011) surface crystal orientation is bonded to a base silicon substrate having a (001) surface crystal orientation to form a DSB wafer in which the in-plane <110> direction of the (011) DSB layer is aligned with an in-plane <110> direction of the (001) base substrate. Selected regions of the DSB layer are amorphized down to the base substrate to form amorphized regions aligned with the mutually orthogonal in-plane <100> directions of the (001) base substrate, followed by recrystallization using the base substrate as a template.

Abstract: A fabrication method for a semiconductor device includes a step of forming a gate insulating film on a semiconductor layer, and a step of forming a first gate electrode layer on the gate insulating film. The fabrication method also includes a step of forming a pocket ion region under the first gate electrode layer, and a step of forming a second gate electrode layer overlaying the first gate electrode layer after forming the pocket ion region.

Abstract: A method for forming fin structures for a semiconductor device that includes a substrate and a dielectric layer formed on the substrate is provided. The method includes etching the dielectric layer to form a first structure, depositing an amorphous silicon layer over the first structure, and etching the amorphous silicon layer to form second and third fin structures adjacent first and second side surfaces of the first structure. The second and third fin structures may include amorphous silicon material. The method further includes depositing a metal layer on upper surfaces of the second and third fin structures, performing a metal-induced crystallization operation to convert the amorphous silicon material of the second and third fin structures to a crystalline silicon material, and removing the first structure.

Abstract: In the ion implantation method and semiconductor device manufacturing method relating to the present invention, a disc on which multiple semiconductor substrates are mounted is positioned in the manner that a first angle ?1 is made between an X-Y plane perpendicular to an ion beam and a line perpendicular to the Y-axis in a disc rotation plane. In this state, an ion beam is emitted to implant a first conductivity type impurity in the semiconductor substrates while the disc is rotated about a disc rotation axis. Then, the disc is positioned in the manner that a second angle ?2 is made between the X-Y plane and a line perpendicular to the Y-axis in the disc rotation plane. In this state, an ion beam is emitted to implant a second conductivity type impurity in the semiconductor substrates while the disc is rotated about the disc rotation axis.

Abstract: A method of manufacturing a device includes doping a low voltage threshold area and a high voltage threshold area. Gate structures are formed over the low voltage threshold and high voltage threshold areas while protecting the gate structure over the low voltage threshold area. A silicidation process is performed over the high voltage threshold area while the gate structure over the low voltage threshold area remains protected. Siliciding includes depositing metal on the gate of the high voltage threshold area and annealing the metal, the metal is deposited either by CVD or sputtering followed by anneal to fully suicide the gate structure of the high voltage threshold area. The metal, preferably cobalt or nickel is deposited to a thickness of approximately 500 ?, annealed for about 3 minutes at about 400° C.

Abstract: A method for forming a semiconductor device includes defining a sacrificial layer (108) over a single crystalline substrate (106). The sacrificial layer (108) is implanted with a dopant species in a manner that prevents the single crystalline substrate (106) from becoming substantially amorphized. The sacrificial layer (108) is annealed so as to drive said dopant species from said sacrificial layer (108) into said single crystalline substrate (106).

Abstract: A vertical semiconductor power device includes a plurality of semiconductor power cells connected to a bottom electric terminal disposed on a bottom surface of a semiconductor substrate and at least a top electrical terminal disposed on a top surface of the substrate and connected to the semiconductor power cells. The top electrical terminal further includes a solderable front metal for soldering to a conductor for providing an electric connection therefrom. In an exemplary embodiment, the conductor soldering to the solderable front metal includes a conductor of a high-heat-conductivity metal plate. In another exemplary embodiment, the conductor soldering to the solderable front metal includes a copper plate. In another exemplary embodiment, the solderable front metal includes a Ti/Ni/Au front metal. In another exemplary embodiment, the solderable front metal includes a Ti/Ni/Ag front metal.

Abstract: Ion sources and methods for generating molecular ions in a cold operating mode and for generating atomic ions in a hot operating mode are provided. In some embodiments, first and second electron sources are located at opposite ends of an arc chamber. The first electron source is energized in the cold operating mode, and the second electron source is energized in the hot operating mode. In other embodiments, electrons are directed through a hole in a cathode in the cold operating mode and are directed at the cathode in the hot operating mode. In further embodiments, an ion beam generator includes a molecular ion source, an atomic ion source and a switching element to select the output of one of the ion sources.

Abstract: A method of manufacturing a plurality of MOS transistors includes forming gate structures in first and second regions on a substrate and forming mask portions only between adjacent drain sides of the respective gate structures only in the first region. Dopant of a first conductivity type that is the same as that of the substrate, is implanted at first and second angles in both the first and second regions to form halo regions only in source sides under the gate structures in the first region and in both source and drain sides under the gate structures in the second region.

Abstract: A method for making a semiconductor device, comprising (a) providing a structure comprising a gate electrode (207) disposed on a substrate (203); (b) creating first (213) and second (214) pre-amorphization implant regions in the substrate such that the first and second pre-amorphization implant regions are asymmetrically disposed with respect to said gate electrode; (c) creating first (219) and second (220) spacer structures adjacent to first and second sides of the gate electrode, wherein the first and second spacer structures overlap the first and second pre-amorphization implant regions; and (d) creating source (217) and drain (218) regions in the substrate adjacent, respectively, to the first and second spacer structures.

Abstract: Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric (520) faces the ion stream, but damage to the gate dielectric is annealed in subsequent thermal steps. In some embodiments, the dopant implantation is an angled implant. The implant is performed from the opposite sides of the wafer, and thus from the opposite sides of each active area. Each active area includes a region implanted from one side and a region implanted from the opposite side. The two regions overlap to facilitate threshold voltage adjustment.

Abstract: Some embodiments of the invention relate to manufacturing a semiconductor device with an implantation layer on a semiconductor substrate including a method of manufacturing such an implantation layer, wherein said implantation layer is formed in an implantation step at a predetermined depth of penetration, determined from a top surface of said semiconductor substrate, using a particle beam, by increasing its path distance to a main implantation peak and correspondingly increasing the energy level of said particle beam for producing an undamaged implantation layer having a thickness that is increased significantly compared with the thickness of an implantation layer that would be produced at said predetermined depth of penetration using a particle beam with non-increased path distance and energy level.

Abstract: A gate electrode is formed on a substrate with a gate insulating layer therebetween. A liner is then deposited on sidewalls of the gate electrode. Source/drain extensions are implanted into the substrate. A first spacer is then formed on the liner. Deep source/drain are implanted into the substrate. A second spacer is formed at the foot of the first spacer. A tilt-angle pre-amorphization implant (PAI) is conducted to form an amorphized layer next to the second spacer. A metal layer is then sputtered on the amorphized layer. The metal layer reacts with the amorphized layer to form a metal silicide layer thereto.

Abstract: The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a substrate, implanting an atom selected from the group consisting of fluorine, silicon, or germanium into the substrate proximate the gate structure to cause at least a portion of the substrate to be in a sub-amorphous state, and implanting a dopant into the substrate having the implanted atom therein, thereby forming source/drain regions in the substrate, wherein the transistor device does not have a halo/pocket implant.

Abstract: A method of forming a channel in a semiconductor device including forming an opening in a masking layer to expose a portion of an underlying semiconductor layer through the opening is provided. The method further includes disposing a screening layer and implanting a first type of ions in the portion of the underlying semiconductor layer through the screening layer and through the opening in the masking layer. A second type of ions are implanted in the portion of the underlying semiconductor layer through the screening layer and through the opening in the masking layer at an oblique ion implantation angle wherein a lateral spread of second type ions is greater than a lateral spread of first type ions. Semiconductor devices fabricated in accordance to above said method is also provided.

Abstract: Disclosed herein is a method of manufacturing a semiconductor device via gate-through ion implantation, comprising forming a gate stack on a semiconductor substrate and performing ion implantation for control of the threshold voltage and junction ion implantation for formation of source/drain regions, on the entire surface of the semiconductor substrate having the gate stack formed thereon. In accordance with the present invention, since ion implantation is carried out after formation of the gate stack involving a thermal process, there are no changes in concentrations of implanted dopants due to heat treatment upon formation of the gate stack.

Abstract: There is proposed an apparatus for doping a material to be doped by generating plasma (ions) and accelerating it by a high voltage to form an ion current is proposed, which is particularly suitable for processing a substrate having a large area. The ion current is formed to have a linear sectional configuration, and doping is performed by moving a material to be doped in a direction substantially perpendicular to the longitudinal direction of a section of the ion current.

Abstract: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.

Abstract: A surface emitting semiconductor device comprises: a semiconductor region including an active layer; a first DBR having first layers and second layers; and a second DBR. The first and second layers are alternately arranged, and the first layers are made of dielectric material. The first DBR, semiconductor region and second DBR are sequentially arranged along a predetermined axis, and the semiconductor region is provided between the first DBR and the second DBR. The cross section of the first DBR is taken along a reference plane perpendicular to the predetermined axis. The distance between two points on an edge of the cross section takes a first value in a direction of an X-axis of a two-dimensional XY orthogonal coordinate system defined on the reference plane, and the distance between two points on the edge takes a second value in a direction of a Y-axis of the above coordinate system. The first value is different from the second value.

Abstract: An n-type drift region includes an active element region and a peripheral region. A p-type base region is formed at least in the active element region. A trench-type gate electrode is formed in each of the active element region and the peripheral region. An n-type source region formed in the base region. A plurality of p-type column regions is selectively formed separately from one another in each of the active element region and the peripheral region. In a peripheral region, a p-type guard region is formed below the gate electrode. In the active element region, the p-type guard region is not formed below the gate electrode. As a result, it is possible to hold the breakdown voltage in the peripheral region at a higher level than in the active element region while maintaining the low ON resistance due to a superjunction structure and to raise the breakdown voltage performance of the semiconductor device.

Abstract: A method of doping fins of a semiconductor device that includes a substrate includes forming multiple fin structures on the substrate, each of the fin structures including a cap formed on a fin. The method further includes performing a first tilt angle implant process to dope a first pair of the multiple fin structures with n-type impurities and performing a second tilt angle implant process to dope a second pair of the multiple fin structures with p-type impurities.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a semiconductor region of a first conductive type on a semiconductor wafer; forming a gate electrode on the semiconductor region; on the semiconductor region, forming a first insulating film over the whole surface including the upper surface of the gate electrode; by removing the formed first insulating film through etching from the top surface side, forming first sidewalls, covering the side surfaces of the gate electrode, from the first insulating film; and by implanting first impurity ions of a second conductive type to the semiconductor region by using an ion implantation device capable of processing a plurality of semiconductor wafers collectively, forming first impurity diffusion regions on both sides of the gate electrode in the semiconductor region.

Abstract: This invention concerns semiconductor devices of the general type comprising a counted number of dopant atoms (142) implanted in regions of a substrate (158) that are substantially intrinsic semiconductor. One or more doped surface regions (152) of the substrate (158) are metallised to form electrodes (150) and a counted number of dopant ions (142) are implanted in a region of the substantially intrinsic semiconductor.

Abstract: A semiconductor device with strain enhancement is formed by providing a semiconductor substrate and an overlying control electrode having a sidewall. An insulating layer is formed adjacent the sidewall of the control electrode. The semiconductor substrate and the control electrode are implanted to form first and second doped current electrode regions, a portion of each of the first and second doped current electrode regions being driven to underlie both the insulating layer and the control electrode in a channel region of the semiconductor device. The first and second doped current electrode regions are removed from the semiconductor substrate except for underneath the control electrode and the insulating layer to respectively form first and second trenches. An insitu doped material containing a different lattice constant relative to the semiconductor substrate is formed within the first and second trenches to function as first and second current electrodes of the semiconductor device.

Abstract: A method for ion implanting a tip source and drain region and halo region for a tri-gate field-effect transistor is described. A silicon body is implanted, in one embodiment, from six different angles to obtain ideal regions.

Abstract: A semiconductor device having a field effect transistor and a method of fabricating the same. In-situ doped epitaxial patterns are respectively formed at both sidewalls of a protruded channel pattern from a substrate by performing an in-situ doped epitaxial growth process. The in-situ doped epitaxial pattern has a conformal impurity concentration throughout. Accordingly, source/drain regions with a conformal impurity concentration are connected throughout a channel width of a channel region including both sidewalls of a protruded channel pattern. As a result, it is possible to maximize a driving current of the filed effect transistor, and an on-off characteristic can be highly stabilized.

Abstract: A one time programmable (OTP) electrically programmable read only memory (EPROM) transistor (100) having an increased breakdown voltage (BVdss) is disclosed. The increased breakdown voltage reduces the probability that the OTP EPROM (100) will breakdown during a programming operation by maintaining a breakdown voltage above a programming voltage. The breakdown voltage is, at least partially, increased by forming a p-doped region (140) within a semiconductor substrate (102), and forming a drain region (166) of the OTP EPROM (100) within the p-doped region (140).

Abstract: A method of forming a doped semiconductor portion includes providing a semiconductor substrate with a surface, and providing protruding portions of a covering layer on the substrate surface, where the portions are arranged in a pattern of lines or segments of lines extending in a first direction. Portions of a resist layer are provided on the substrate surface, where the portions of the resist layer are arranged in a pattern of lines or segments of lines extending in a second direction, and the second direction intersects the first direction. The portions of the resist layer have a thickness d, the thickness d being measured perpendicularly with respect to the substrate surface. A tilted ion implantation step is then performed.

Abstract: An insulated gate field effect transistor having reduced gate-drain overlap and a method for manufacturing the insulated gate field effect transistor. A gate structure is formed on a major surface of a semiconductor substrate. A source extension region and a drain extension region are formed in a semiconductor material using an angled implant. The source extension region extends under the gate structure, whereas the drain extension region is laterally spaced apart from the gate structure. A source region is formed in the semiconductor substrate and a drain region is formed in the semiconductor substrate, where the source and drain regions are laterally spaced apart from the gate structure. A source-side halo region is formed in the semiconductor substrate adjacent the source extension region.