Avalanche Diode (epo) Patents (Class 257/E21.357)
  • Patent number: 10056451
    Abstract: Hydrogen atoms and crystal defects are introduced into an n? semiconductor substrate by proton implantation. The crystal defects are generated in the n? semiconductor substrate by electron beam irradiation before or after the proton implantation. Then, a heat treatment for generating donors is performed. The amount of crystal defects is appropriately controlled during the heat treatment for generating donors to increase a donor generation rate. In addition, when the heat treatment for generating donors ends, the crystal defects formed by the electron beam irradiation and the proton implantation are recovered and controlled to an appropriate amount of crystal defects. Therefore, for example, it is possible to improve a breakdown voltage and reduce a leakage current.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: August 21, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Yoshimura, Masayuki Miyazaki, Hiroshi Takishita, Hidenao Kuribayashi
  • Patent number: 9018729
    Abstract: An avalance diode including, between two heavily-doped regions of opposite conductivity types arranged at the surface of a semiconductor region, a lightly-doped region, with length L of the lightly-doped region between the heavily-doped regions approximately ranging between 50 and 200 nm.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: April 28, 2015
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Raul Andres Bianchi, Pascal Fonteneau
  • Patent number: 8592247
    Abstract: A method includes: forming an epitaxy wafer by growing a light absorbing layer, a grading layer, an electric field buffer layer, and an amplifying layer on the front surface of a substrate in sequence; forming a diffusion control layer on the amplifying layer; forming a protective layer for protecting the diffusion control layer on the diffusion control layer; forming an etching part by etching from the protective layer to a predetermined depth of the amplifying layer; forming a first patterning part by patterning the protective layer; forming a junction region and a guardring region at the amplifying layer by diffusing a diffusion material to the etching part and the first patterning part; removing the diffusion control layer and the protective layer and forming a first electrode connected to the junction region on the amplifying layer; and forming a second electrode on the rear surface of the substrate.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: November 26, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jae Sik Sim, Ki Soo Kim, Bong Ki Mheen, Myoung Sook Oh, Yong Hwan Kwon, Eun Soo Nam
  • Patent number: 8574945
    Abstract: An embodiment of an array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type, housing a first cathode region, of the second conductivity type, and facing a surface of the body, an anode region, having the first conductivity type and a higher doping level than the body, extending inside the body, and facing the surface laterally to the first cathode region and at a distance therefrom, and an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the first cathode region and the anode region. The insulation region is formed by a mirror region of metal material, a channel-stopper region having the second conductivity type, surrounding the mirror region, and a coating region, of dielectric material, arranged between the mirror region and the channel-stopper region.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: November 5, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Delfo Nunziato Sanfilippo, Emilio Antonio Sciacca, Piero Giorgio Fallica, Salvatore Antonio Lombardo
  • Patent number: 8530953
    Abstract: A transistor power switch device comprising an array of vertical transistor elements for carrying current between the first and second faces of a semiconductor body and a vertical avalanche diode electrically in parallel with the array of vertical transistors. The array of transistor elements includes at the first face an array of source regions of a first semiconductor type, at least one p region of a second semiconductor type opposite to the first type interposed between the source regions and the second face, at least one control electrode for switchably controlling flow of the current through the p region, and a conductive layer contacting the source regions and insulated from the control electrode.
    Type: Grant
    Filed: November 27, 2008
    Date of Patent: September 10, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jean Michel Reynes, Beatrice Bernoux, Rene Escoffier, Pierre Jalbaud, Ivana Deram
  • Patent number: 8492866
    Abstract: Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vb of the diode (e.g., increasing the length reduces Vb of the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Frederick G. Anderson, Natalie B. Feilchenfeld, David L. Harmon, Richard A. Phelps, Yun Shi, Michael J. Zierak
  • Patent number: 8471293
    Abstract: An embodiment of an array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type, housing a first cathode region, of the second conductivity type, and facing a surface of the body, an anode region, having the first conductivity type and a higher doping level than the body, extending inside the body, and facing the surface laterally to the first cathode region and at a distance therefrom, and an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the first cathode region and the anode region. The insulation region is formed by a mirror region of metal material, a channel-stopper region having the second conductivity type, surrounding the mirror region, and a coating region, of dielectric material, arranged between the mirror region and the channel-stopper region.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: June 25, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Delfo Nunziato Sanfilippo, Emilio Antonio Sciacca, Piero Giorgio Fallica, Salvatore Antonio Lombardo
  • Patent number: 8314002
    Abstract: A semiconductor device is formed in a thin float zone wafer. Junctions are diffused into the top surface of the wafer and the wafer is then reduced in thickness by removal of material from its bottom surface. A weak collector is then formed in the bottom surface by diffusion of boron (for a P type collector). The weak collector is then formed or activated only over spaced or intermittent areas. This is done by implant of the collector impurity through a screening mask; or by activating only intermittent areas by a laser beam anneal in which the beam is directed to anneal only preselected areas. The resulting device has an effective very low implant dose, producing a reduced switching energy and increased switching speed, as compared to prior art weak collector/anodes and life time killing technologies.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: November 20, 2012
    Assignee: International Rectifier Corporation
    Inventors: Richard Francis, Chiu Ng
  • Patent number: 8076173
    Abstract: A semiconductor substrate and a method of its manufacture has a semiconductor substrate having a carbon concentration in a range of 6.0×1015 to 2.0×1017 atoms/cm3, both inclusively. One principal surface of the substrate is irradiated with protons and then heat-treated to thereby form a broad buffer structure, namely a region in a first semiconductor layer where a net impurity doping concentration is locally maximized. Due to the broad buffer structure, lifetime values are substantially equalized in a region extending from an interface between the first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer to the region where the net impurity doping concentration is locally maximized. In addition, the local minimum of lifetime values of the first semiconductor layer becomes high.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: December 13, 2011
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Michio Nemoto
  • Patent number: 7964435
    Abstract: A method for controlling dopant diffusion is disclosed. Using certain control parameters that are not used in the prior art, the method provides an unprecedented measure of control over the dopant diffusion process. The control parameters include, among others, the size of the diffusion windows in the diffusion mask and the proximity of the diffusion windows to a dopant sink. In some embodiments, the diffusion process is conducted in an epi-reactor.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: June 21, 2011
    Assignee: Princeton Lightware, Inc.
    Inventors: Rafael Ben-Michael, Mark Allen Itzler, Xudong Jiang
  • Patent number: 7928533
    Abstract: An avalanche photodiode with a nano-scale reach-through structure comprising n-doped and p-doped regions, formed on a silicon island on an insulator, so that the avalanche photodiode may be electrically isolated from other circuitry on other silicon islands on the same silicon chip as the avalanche photodiode. For some embodiments, multiplied holes generated by an avalanche reduces the electric field in the depletion region of the n-doped and p-doped regions to bring about self-quenching of the avalanche photodiode. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: April 19, 2011
    Assignee: California Institute of Technology
    Inventors: Xinyu Zheng, Bedabrata Pain, Thomas J. Cunningham
  • Patent number: 7888251
    Abstract: Apparatus and method are provided for hydrogenating semiconductor or other materials by ultraviolet (UV) radiation in the presence of hydrogen. Hydrogen uptake may be optimized by selection of temperature and wavelength of the UV radiation. Patterned areas may be selectively hydrogenated, such as mesas in Avalanche Photodiode Arrays.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: February 15, 2011
    Assignee: Amethyst Research, Inc.
    Inventors: Terry D. Golding, Ronald Paul Hellmer
  • Patent number: 7851823
    Abstract: A transmitted light absorption/recombination layer, a barrier layer, a wavelength selection/absorption layer, and an InP window layer having a p-type region are supported by an n-type substrate and arranged in that order. Light with a wavelength of 1.3 ?m reaches the wavelength selection/absorption layer through the InP window layer. Then, the light is absorbed by the wavelength selection/absorption layer and drawn from the device as an electric current signal. Light with a wavelength of 1.55 ?m reaches the transmitted light absorption/recombination layer through the barrier layer. Then, the light is absorbed by the transmitted light absorption/recombination layer, generating electrons and holes. These electrons and holes recombine with each other and, hence, disappear.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: December 14, 2010
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Eitaro Ishimura
  • Patent number: 7719029
    Abstract: A single-photon avalanche detector is disclosed that is operable at wavelengths greater than 1000 nm and at operating speeds greater than 10 MHz. The single-photon avalanche detector comprises a thin-film resistor and avalanche photodiode that are monolithically integrated such that little or no additional capacitance is associated with the addition of the resistor.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: May 18, 2010
    Assignee: Princeton Lightwave, Inc.
    Inventor: Mark Allen Itzler
  • Patent number: 7612431
    Abstract: Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: November 3, 2009
    Assignee: Vishay-Siliconix
    Inventors: Qufei Chen, Robert Xu, Kyle Terrill, Deva Pattanayak
  • Publication number: 20090185316
    Abstract: The invention relates to an avalanche diode that can be employed as an ESD protection device. An avalanche ignition region is formed at the p-n junction of the diode and includes an enhanced defect concentration level to provide rapid onset of avalanche current. The avalanche ignition region is preferably formed wider than the diode depletion zone, and is preferably created by placement, preferably by ion implantation, of an atomic specie different from that of the principal device structure. The doping concentration of the placed atomic specie should be sufficiently high to ensure substantially immediate onset of avalanche current when the diode breakdown voltage is exceeded. The new atomic specie preferably comprises argon or nitrogen, but other atomic species can be employed. However, other means of increasing a defect concentration level in the diode depletion zone, such as an altered annealing program, are also contemplated.
    Type: Application
    Filed: January 21, 2008
    Publication date: July 23, 2009
    Inventors: Jens Schneider, Kai Esmark, Martin Wendel
  • Patent number: 7544545
    Abstract: Embodiments of the present invention include a method of manufacturing a trench polysilicon diode. The method includes forming a N?(P?) type epitaxial region on a N+(P+) type substrate and forming a trench in the N?(P?) type epitaxial region. The method further includes forming a insulating layer in the trench and filling the trench with polysilicon forming a top surface of the trench. The method further includes forming P+(N+) type doped polysilicon region and N+(P+) type doped polysilicon region in the trench and forming a diode in the trench wherein a portion of the diode is lower than the top surface of the trench.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: June 9, 2009
    Assignee: Vishay-Siliconix
    Inventors: Qufei Chen, Robert Xu, Kyle Terrill, Deva Pattanayak
  • Patent number: 7510903
    Abstract: A bi-directional transient voltage suppression (“TVS”) device (101) includes a semiconductor die (201) that has a first avalanche diode (103) in series with a first rectifier diode (104) connected cathode to cathode, electrically coupled in an anti-parallel configuration with a second avalanche diode (105) in series with a second rectifier diode (106) also connected cathode to cathode. All the diodes of the TVS device are on a single semiconductor substrate (301). The die has a low resistivity buried diffused layer (303) having a first conductivity type disposed between a semiconductor substrate (301) having the opposite conductivity type and a high resistivity epitaxial layer (305) having the first conductivity type. The buried diffused layer shunts most of a transient current away from a portion of the epitaxial layer between the first avalanche diode and the first rectifier diode, thereby reducing the clamping voltage relative to the breakdown voltage.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: March 31, 2009
    Assignee: Protek Devices LP
    Inventors: Fred Matteson, Venkatesh P. Pai, Donald K. Cartmell
  • Publication number: 20080315260
    Abstract: An open-base semiconductor diode device has an emitter, base, and collector layers. The layers are configured and doped such that the device has an IV characteristic with: i. a punchthrough region beginning at a voltage Vpt with positive resistance, followed by, and ii. an avalanche region including a positive resistance stage beginning with conductivity modulation at Vcrit and Icrit and having a resistance Rcrit, iii. wherein the values of Vcrit, Icrit and Rcrit are set according to the layer configuration and doping. The device may have a double-base structure, and the width of a lower-doped base region may be minimised such that current density Jcrit at which the conductivity modulation occurs due to avalanche is increased. In one example, the device comprises a N-N+ or a P-P+ double-emitter. Thickness of N? or P? layers may be minimised such that the current-carrying capability is maximised and the doping of this layer does not affect the current-carrying capability of the device.
    Type: Application
    Filed: March 22, 2006
    Publication date: December 25, 2008
    Inventor: Russell Duane
  • Publication number: 20080290466
    Abstract: A semiconductor element includes a semiconductor layer having a first doping density, a metallization, and a contact area located between the semiconductor layer and the metallization. The contact area includes at least one first semiconductor area that has a second doping density higher than the first doping density, and at least one second semiconductor area in the semiconductor layer. The second semiconductor area is in contact with the metallization and provides lower ohmic resistance to the metallization than a direct contact between the semiconductor layer and the metallization provides or would provide.
    Type: Application
    Filed: May 23, 2008
    Publication date: November 27, 2008
    Inventors: Franz Josef Niedernostheide, Manfred Pfaffenlehner, Hans-Joachim Schulze
  • Publication number: 20080283868
    Abstract: A semiconductor device includes a first layer having a first conductivity type, a second layer having a second conductivity type, a third layer having the second conductivity type, one or more first zones having the first conductivity type and located within the second layer, wherein each one of the one or more first zones is adjacent to the third layer, and one or more second zones having the second conductivity type and located within the second layer, wherein each one of the one or more second zones is adjacent to one or more of the one or more first zones.
    Type: Application
    Filed: May 14, 2007
    Publication date: November 20, 2008
    Inventors: Hans-Joachim Schulze, Hans-Peter Felsl
  • Patent number: 7361942
    Abstract: A bi-directional transient voltage suppression (“TVS”) device (101) includes a semiconductor die (201) that has a first avalanche diode (103) in series with a first rectifier diode (104) connected cathode to cathode, electrically coupled in an anti-parallel configuration with a second avalanche diode (105) in series with a second rectifier diode (106) also connected cathode to cathode. All the diodes of the TVS device are on a single semiconductor substrate (301). The die has a low resistivity buried diffused layer (303) having a first conductivity type disposed between a semiconductor substrate (301) having the opposite conductivity type and a high resistivity epitaxial layer (305) having the first conductivity type. The buried diffused layer shunts most of a transient current away from a portion of the epitaxial layer between the first avalanche diode and the first rectifier diode, thereby reducing the clamping voltage relative to the breakdown voltage.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: April 22, 2008
    Assignee: Protek Devices, LP
    Inventors: Fred Matteson, Venkatesh Panemangalore Pai, Donald K. Cartmell
  • Patent number: 7279390
    Abstract: A Schottky diode capable of sustaining a breakdown voltage of greater than about 250 volts and a method for its manufacture. An epitaxial layer disposed on a semiconductor substrate has a thickness of at least about 15 micrometers and an impurity concentration ranging from about 1×1014 atoms per cubic centimeter to about 1×1015 atoms per cubic centimeter. A guard ring extends from about 3 micrometers to about 15 micrometers into the epitaxial layer. A dielectric material is formed over the epitaxial layer and a portion of the dielectric material is removed to expose a portion of the guard ring and a portion of the epitaxial layer within the guard ring. An electrically conductive material is formed over the exposed portion of the epitaxial layer and an electrically conductive material is formed in contact with a bottom surface of the semiconductor substrate.
    Type: Grant
    Filed: March 21, 2005
    Date of Patent: October 9, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Mark Duskin, Blanca Estela Kruse