Abstract: Forming a semiconductor device includes forming a first conductive line on a substrate, forming a memory cell including a switching device and a data storage element on the first conductive line, and forming a second conductive line on the memory cell. Forming the switching device includes forming a first semiconductor layer, forming a first doped region by injecting a n-type impurity into the first semiconductor layer, forming a second semiconductor layer thicker than the first semiconductor layer, on the first semiconductor layer having the first doped region, forming a second doped region by injecting a p-type impurity into an upper region of the second semiconductor layer, and forming a P-N diode by performing a heat treatment process to diffuse the n-type impurity and the p-type impurity in the first doped region and the second doped region to form a P-N junction of the P-N diode in the second semiconductor layer.

Abstract: A method for producing a semiconductor device is provided. The method includes providing a semiconductor substrate, providing at least one semiconductor device on the substrate, having a back face opposite the semiconductor substrate and a front face towards the semiconductor substrate, providing a contact layer on the back face of the semiconductor device, bonding the contact layer to an auxiliary carrier, and separating the at least one semiconductor device from the substrate. Further, a semiconductor device produced according to the method and an intermediate product are provided.

Abstract: A process for manufacturing a semiconductor device, wherein a semiconductor layer is formed on a body of semiconductor material; a first mask is formed on the semiconductor layer; a first conductive region is implanted in the body using the first mask; a second mask is formed laterally and complementarily to the first mask, at least in a projection in a plane parallel to the surface of the body; a second conductive region is implanted in the body using the second mask, in an adjacent and complementary position to the first conductive region; spacers are formed on the sides of the second mask region, to form a third mask aligned to the second mask; and, using the third mask, portions of the semiconductor layer are removed to form a gate region.

Abstract: A rectifying antenna device is disclosed. The device comprises a pair of electrode structures, and at least one nanostructure diode contacting at least a first electrode structure of the pair and being at least in proximity to a second electrode structure of the pair. At least one electrode structure of the pair receives AC radiation, and the nanostructure diode(s) at least partially rectifies a current generated by the AC radiation.

Abstract: Semiconductor elements deteriorate or are destroyed due to electrostatic discharge damage. The present invention provides a semiconductor device in which a protecting means is formed in each pixel. The protecting means is provided with one or a plurality of elements selected from the group consisting of resistor elements, capacitor elements, and rectifying elements. Sudden changes in the electric potential of a source electrode or a drain electrode of a transistor due to electric charge that builds up in a pixel electrode is relieved by disposing the protecting means between the pixel electrode of the light-emitting element and the source electrode or the drain electrode of the transistor. Deterioration or destruction of the semiconductor element due to electrostatic discharge damage is thus prevented.

Abstract: An SCR includes a first doped region of a first type having a first doping concentration. A first well of the first type and a first well of a second type are disposed in upper areas of the first doped region of the first type such that the first well of the second type is laterally spaced from the first well of the first type by a non-zero distance. A second doped region of the first type has a second doping concentration that is greater than the first doping concentration and is disposed in the first well of the second type to form an anode of the SCR. A first doped region of the second type is disposed in the first well of the first type and forms a cathode of the SCR.

Abstract: The present invention provides a rectifier element that has a titanium oxide layer interposed between first and second electrodes containing a transition metal with an electronegativity larger than that of Ti, wherein, in the titanium oxide layer, only the interface on the side facing any one of the electrodes has a stoichiometric composition, and wherein the average composition of the whole layer is represented by the formula TiOx (wherein x satisfies the relationship 1.6?x<2), and wherein the rectifying characteristics can be reversed by applying a reverse electrical signal that exceeds the critical reverse electric power between the first and second electrodes in an opposite direction. The present invention also provides a process for producing a rectifier element, which includes the steps of depositing a first electrode that contains a transition metal with an electronegativity larger than that of Ti on a substrate; depositing a layer of titanium oxide (TiOx, wherein x satisfies the relationship 1.

Abstract: A diode and memory device including the diode, where the diode includes a conductive portion and another portion formed of a first material that has characteristics allowing a first decrease in a resistivity of the material upon application of a voltage to the material, thereby allowing current to flow there through, and has further characteristics allowing a second decrease in the resistivity of the first material in response to an increase in temperature of the first material.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a P+-N body diode and an N+-P body diode. The P+-N body diode and the N+-P body diode are laterally integrated.

Abstract: A serially-connected diode pair made of diodes having a high withstand voltage and a low on-resistance is formed based on a high withstand voltage vertical PNP bipolar transistor process technology. Two of the diode pairs are connected in parallel to form a bridge so that there is formed a high-efficiency full-wave rectifier circuit that is free from a leakage current due to a parasitic transistor. The serially-connected diode pair is formed by connecting a diode composed of a P type semiconductor substrate, that makes an anode, and an N type buried layer, that makes a cathode, and a diode composed of a P+ type conductive layer, that makes an anode, and an N type epitaxial layer, that makes a cathode, in series with an electrode AC1.

Abstract: In one embodiment, a Schottky diode is formed on a semiconductor substrate with other semiconductor devices and is also formed with a high breakdown voltage and a low forward resistance.

Abstract: This invention provides a lateral high-voltage semiconductor device, which is a three-terminal one with two types of carriers for conduction and consists of a highest voltage region and a lowest voltage region referring to the substrate and a surface voltage-sustaining region between the highest voltage region and the lowest voltage region. The highest voltage region and the lowest region have an outer control terminal and an inner control terminal respectively, where one terminal is for controlling the flow of majorities of one conductivity type and another for controlling the flow of majorities of the other conductivity type. The potential of the inner control terminal is regulated by the voltage applied to the outer control terminal.

Abstract: A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions.

Abstract: A rectifying antenna device is disclosed. The device comprises a pair of electrode structures, and at least one nanostructure diode contacting at least a first electrode structure of the pair and being at least in proximity to a second electrode structure of the pair. At least one electrode structure of the pair receives AC radiation, and the nanostructure diode(s) at least partially rectifies a current generated by the AC radiation.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a P+-N body diode and an N+-P body diode. The P+-N body diode and the N+-P body diode are laterally integrated.

Abstract: A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions.

Abstract: Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.

Abstract: Semiconductor elements deteriorate or are destroyed due to electrostatic discharge damage. The present invention provides a semiconductor device in which a protecting means is formed in each pixel. The protecting means is provided with one or a plurality of elements selected from the group consisting of resistor elements, capacitor elements, and rectifying elements. Sudden changes in the electric potential of a source electrode or a drain electrode of a transistor due to electric charge that builds up in a pixel electrode is relieved by disposing the protecting means between the pixel electrode of the light-emitting element and the source electrode or the drain electrode of the transistor. Deterioration or destruction of the semiconductor element due to electrostatic discharge damage is thus prevented.

Abstract: An SOI semiconductor component comprises a semiconductor substrate having a basic doping, a dielectric layer arranged on the semiconductor substrate, and a semiconductor layer arranged on the dielectric layer. The semiconductor layer includes a drift zone of a first conduction type, a junction between the drift zone and a further component zone which is configured in such a way that a space charge zone is formed in the drift zone when a reverse voltage is applied to the junction, and a terminal zone adjacent to the drift zone. A first terminal electrode is connected to the further component zone, and a second terminal electrode is connected to the terminal zone. In the semiconductor substrate a first semiconductor zone is doped complementarily with respect to a basic doping of the semiconductor substrate, and the first terminal electrode is connected to the first semiconductor zone. A rectifier element is connected between the first terminal electrode and the first semiconductor zone.

Abstract: Embodiments of the present invention include a method of manufacturing a trench polysilicon diode. The method includes forming a N?(P?) type epitaxial region on a N+(P+) type substrate and forming a trench in the N?(P?) type epitaxial region. The method further includes forming a insulating layer in the trench and filling the trench with polysilicon forming a top surface of the trench. The method further includes forming P+(N+) type doped polysilicon region and N+(P+) type doped polysilicon region in the trench and forming a diode in the trench wherein a portion of the diode is lower than the top surface of the trench.

Abstract: A Schottky diode exhibiting low series resistance is efficiently fabricated using a substantially standard CMOS process flow by forming the Schottky diode using substantially the same structures and processes that are used to form a field effect transistor (FET) of a CMOS IC device. Polycrystalline silicon, which is used to form the gate structure of the FET, is utilized to form an isolation structure between the Schottky barrier and backside structure of the Schottky diode. Silicide (e.g., cobalt silicide (CoSi2)) structures, which are utilized to form source and drain metal-to-silicon contacts in the FET, are used to form the Schottky barrier and backside Ohmic contact of the Schottky diode. Heavily doped drain (HDD) diffusions and lightly doped drain (LDD) diffusions, which are used to form source and drain diffusions of the FET, are utilized to form a suitable contact diffusion under the backside contact silicide.

Abstract: A method for annealing a diode formed of a silicon-germanium alloy that minimizes leakage current is disclosed. The method includes the steps of forming semiconductor pillars of an alloy of silicon and germanium; heating the pillars at a first temperature for at least 30 minutes, and then heating the pillars at a second temperature higher than the first temperature of the alloy for up to 120 seconds. The invention further includes a monolithic three dimensional memory array of a plurality of p-i-n diodes, the p-i-n diodes being formed of a silicon-germanium alloy that have been subjected to a two-stage heating process.

Abstract: A system for protecting a high-speed input/output pad of an integrated circuit. The system includes a preferably parasitic silicon controlled rectifier (SCR) and a triggering mechanism that preferably includes an NMOS triggering FET. The SCR includes an anode connected to the input/output pad and a trigger input. The anode and the trigger input form a reverse-biased junction that, during normal operation of the integrated circuit, isolates the triggering mechanism from the input/output pad when power is applied to the integrated circuit.

Abstract: A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.

Abstract: A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.

Abstract: A surface-emitting type device includes a substrate including a first face, a second face that is tilted with respect to the first face and has a plane index different from a plane index of the first face, and a third face that is tilted with respect to the second face and has a plane index equal to the plane index of the first face, an emission section formed above the first face, and a rectification section formed above each of the second face and the third face, wherein the emission section includes a first semiconductor layer of a first conductivity type, an active layer formed above the first semiconductor layer, and a second semiconductor layer of a second conductivity type formed above the active layer, the rectification section includes a first semiconductor layer of the second conductivity type formed above the second face, and a second semiconductor layer of the first conductivity type formed continuously with the first semiconductor layer above the third face, at least a portion of the first semico