Abstract: A solid-state imaging element including: a sensor substrate in which a photoelectric conversion section is arranged and formed; a circuit substrate in which a circuit for driving the photoelectric conversion section is formed, the circuit substrate being laminated to the sensor substrate; a sensor side electrode drawn out to a surface of the sensor substrate on a side of the circuit substrate and formed as one of a projection electrode and a depression electrode; and a circuit side electrode drawn out to a surface of the circuit substrate on a side of the sensor substrate, formed as one of the depression electrode and the projection electrode, and joined to the sensor side electrode in a state of the circuit side electrode and the sensor side electrode being fitted together.

Abstract: A diode is defined on a die. The diode includes a substrate of P conductivity having an upper surface and a lower surface, the substrate having first and second ends corresponding to first and second edges of the die. An anode contacts the lower surface of the substrate. A layer of N conductivity is provided on the upper surface of the substrate, the layer having an upper surface and a lower surface. A doped region of N conductivity is formed at an upper portion of the layer. A cathode contacts the doped region. A passivation layer is provided on the upper surface of the layer and proximate to the cathode.

Abstract: A FinFET diode and method of fabrication are disclosed. In one embodiment, the diode comprises, a semiconductor substrate, an insulator layer disposed on the semiconductor substrate, a first silicon layer disposed on the insulator layer, a plurality of fins formed in a diode portion of the first silicon layer. A region of the first silicon layer is disposed adjacent to each of the plurality of fins. A second silicon layer is disposed on the plurality of fins formed in the diode portion of the first silicon layer. A gate ring is disposed on the first silicon layer. The gate ring is arranged in a closed shape, and encloses a portion of the plurality of fins formed in the diode portion of the first silicon layer.

Abstract: A FinFET diode and method of fabrication are disclosed. In one embodiment, the diode comprises, a semiconductor substrate, an insulator layer disposed on the semiconductor substrate, a first silicon layer disposed on the insulator layer, a plurality of fins formed in a diode portion of the first silicon layer. A region of the first silicon layer is disposed adjacent to each of the plurality of fins. A second silicon layer is disposed on the plurality of fins formed in the diode portion of the first silicon layer. A gate ring is disposed on the first silicon layer. The gate ring is arranged in a closed shape, and encloses a portion of the plurality of fins formed in the diode portion of the first silicon layer.

Abstract: A high voltage ESD protective diode having high avalanche withstand capability and capable of being formed by using manufacturing steps identical with those for a high voltage transistor to be protected, the device having a structure in which a gate oxide film is formed over a substrate surface at a PN junction formed of an N type low concentration semiconductor substrate constituting a cathode region and a P type low concentration diffusion region constituting an anode region, and a gate electrode which is disposed overriding the gate oxide film and a field oxide film is connected electrically by way of a gate plug with an anode electrode, whereby an electric field at the PN junction is moderated upon avalanche breakdown to obtain a high avalanche withstand capability. Further, the withstand voltage can be adjusted by changing the length of the field oxide film.

Abstract: The present invention relates to a technology for reducing dark current noise by discharging electrons accumulated on a surface of an image sensor photodiode. In an N-type or P-type photodiode, a channel is formed between the photodiode and a power voltage terminal, so that electrons (or holes) accumulated on a surface of the photodiode are discharged to the power voltage terminal through the channel.

Abstract: A diode assembly comprising first and second diodes each having a different breakdown voltage, each of the first and second diodes comprising a semiconductor substrate; an electrically conducting channel layer on the semiconductor substrate; an upper semiconductor layer on the channel layer, the upper semiconductor layer comprising a recess; first and second ohmic contacts on the upper semiconductor layer on opposite sides of the recess, the ohmic contacts being connected together to form a first diode contact; a gate electrode within the recess, the gate electrode forming a second diode contact; wherein the area of the recess of the first diode covered by the first gate electrode is different to the area of the recess of the second diode covered by the second gate electrode.

Abstract: A diode assembly comprising first and second diodes each having a different breakdown voltage, each of the first and second diodes comprising a semiconductor substrate; an electrically conducting channel layer on the semiconductor substrate; an upper semiconductor layer on the channel layer, the upper semiconductor layer comprising a recess; first and second ohmic contacts on the upper semiconductor layer on opposite sides of the recess, the ohmic contacts being connected together to form a first diode contact; a gate electrode within the recess, the gate electrode forming a second diode contact; wherein the area of the recess of the first diode covered by the first gate electrode is different to the area of the recess of the second diode covered by the second gate electrode.

Abstract: An image sensing circuit and method is disclosed, wherein a photodiode is formed in a substrate through a series of angled implants. The photodiode is formed by a first, second and third implant, wherein at least one of the implants are angled so as to allow the resulting photodiode to extend out beneath an adjoining gate. Under an alternate embodiment, a fourth implant is added, under an increased implant angle, in the region of the second implant. The resulting photodiode structure substantially reduces or eliminates transfer gate subthreshold leakage.

Abstract: The invention relates to a semiconductor element used for a nonvolatile semiconductor storage device or the like, a semiconductor storage device using the same, a data writing method thereof, a data reading method thereof and a manufacturing method of those, and has an object to provide a semiconductor element in which scaling and integration of cells are possible, storage characteristics of data are excellent, and reduction in power consumption is possible, a semiconductor storage device using the same, a data writing method thereof, a data reading method thereof, and a manufacturing method of those.

Abstract: In one embodiment, a mandrel and an outer dummy spacer may be employed to form a first conductivity type region. The mandrel is removed to form a recessed region wherein a second conductivity type region is formed. In another embodiment, a mandrel is removed from within shallow trench isolation to form a recessed region, in which an inner dummy spacer is formed. A first conductivity type region and a second conductivity region are formed within the remainder of the recessed region. An anneal is performed so that the first conductivity type region and the second conductivity type region abut each other by diffusion. A gate electrode is formed in self-alignment to the p-n junction between the first and second conductivity regions. The p-n junction controlled by the gate electrode, which may be sublithographic, constitutes an inventive tunneling effect transistor.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Adjacent memory devices are electrically isolated. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A gated resonant tunneling diode (GRTD) is disclosed including a metal oxide semiconductor (MOS) gate over a gate dielectric layer which is biased to form an inversion layer between two barrier regions, resulting in a quantum well less than 15 nanometers wide. Source and drain regions adjacent to the barrier regions control current flow in and out of the quantum well. The GRTD may be integrated in CMOS ICs as a quantum dot or a quantum wire device. The GRTD may be operated in a negative conductance mode, in a charge pump mode and in a radiative emission mode.

Abstract: An area-efficient gated diode includes a semiconductor layer of a first conductivity type, an active region of a second conductivity type formed in the semiconductor layer proximate an upper surface thereof, and at least one trench electrode extending vertically through the active region and at least partially into the semiconductor layer. A first terminal of the gated diode is connected to the trench electrode, and a second terminal is connected to the active region. The gated diode is operative in one of at least first an second modes as a function of a voltage potential applied between the first and second terminals. The first mode is characterized by the creation of an inversion layer in the semiconductor layer surrounding the trench electrode. The gated diode has a first capacitance in the first mode and a second capacitance in the second mode, the first capacitance being greater than the second capacitance.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal and a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A light emitting device includes a first semiconductor layer of a first conductivity type, an active region, and a second semiconductor layer of a second conductivity type. First and second contacts are connected to the first and second semiconductor layers. In some embodiments at least one of the first and second contacts has a thickness greater than 3.5 microns. In some embodiments, a first heat extraction layer is connected to one of the first and second contacts. In some embodiments, one of the first and second contacts is connected to a submount by a solder interconnect having a length greater than a width. In some embodiments, an underfill is disposed between a submount and one of the first and second interconnects.

Abstract: A method for forming a photodiode that is self-aligned to a transfer gate while being compatible with a metal silicide process is disclosed. The method comprises forming a gate stack of gate oxide, polysilicon, and a sacrificial/disposable cap insulator over the polysilicon. The insulator may be a combination of silicon oxynitride and silicon dioxide. After formation of the photodiode, the cap insulator layer is removed.

Abstract: A two-terminal barrier controlled TVS diode has a depletion region barrier blocking majority carrier flow through the channel region at the vicinity of the cathode region at bias levels below the predetermined clamping voltage applied between the anode electrode and the cathode electrode, and may be arranged such that the anode region provides conductivity modulation by injecting minority carriers into the channel region during conduction of the semiconductor structure. In presently preferred form the majority carriers are electrons and the minority carriers are holes. Fabrication methods are described.

Abstract: A non-gated diode structure of a silicon-on-insulator, having a silicon-on-insulator substrate, a pair of isolating structures, a first type doped region and a second type doped region. The silicon-on-insulation substrate has a stack of a substrate, an insulation layer and a silicon layer. The isolating structures are located in the silicon layer to define a well region. The first and second type doped regions are located in the well and are adjacent to the isolating structures. Such a non-gated diode structure can be applied to an electrostatic discharge protection circuit to increase the electrostatic discharge protection voltage or current. In addition, a fabrication method of the non-gated diode is also introduced. This non-gated diode can be also fabricated in the general bulk CMOS process, and used in the on-chip ESD protection circuits.