Heterojunction Transistor (epo) Patents (Class 257/E21.371)
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Publication number: 20130092939Abstract: Disclosed are example bipolar transistors capable of reducing the area of a collector, reducing the distance between a base and a collector, and/or reducing the number of ion implantation processes. A bipolar transistor may includes a trench formed by etching a portion of a semiconductor substrate. A first collector may be formed on the inner wall of the trench. A second collector may be formed inside the semiconductor substrate in the inner wall of the trench. A first isolation film may be formed on the sidewall of the first collector. An intrinsic base may be connected to the third collector. An extrinsic base may be formed on the intrinsic base and inside the first isolation film. A second isolation film may be formed on the inner wall of the extrinsic base. An emitter may be formed by burying a conductive material inside the second isolation film.Type: ApplicationFiled: July 6, 2012Publication date: April 18, 2013Applicant: Dongbu HiTek Co., Ltd.Inventor: Nam Joo KIM
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Patent number: 8415762Abstract: The external base electrode has a two-layered structure where a p-type polysilicon film doped with a medium concentration of boron is laminated on a p-type polysilicon film doped with a high concentration of boron. Therefore, since the p-type polysilicon film doped with a high concentration of boron is in contact with an intrinsic base layer at a junction portion between the external base electrode and the intrinsic base layer, the resistance of the junction portion can be reduced. In addition, since the resistance of the external base electrode becomes a parallel resistance of the two layers of the p-type polysilicon films, the resistance of the p-type polysilicon film whose boron concentration is relatively lower is dominant.Type: GrantFiled: October 31, 2007Date of Patent: April 9, 2013Assignee: Hitachi, Ltd.Inventors: Yoshinori Yoshida, Tatsuya Tominari, Toshio Ando
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Publication number: 20130005108Abstract: A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.Type: ApplicationFiled: September 11, 2012Publication date: January 3, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wade J. Hodge, Alvin J. Joseph, Rajendran Krishnasamy, Qizhi Liu, Bradley A. Orner
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Publication number: 20130001647Abstract: In an embodiment, a bipolar transistor structure is formed on a silicon-on-insulator (SOI) structure that includes a semiconductor substrate, a buried oxide layer formed on the semiconductor substrate and a top silicon layer formed on the buried oxide layer.Type: ApplicationFiled: June 28, 2011Publication date: January 3, 2013Inventor: Steven J. Adler
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Patent number: 8338863Abstract: Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening.Type: GrantFiled: May 9, 2012Date of Patent: December 25, 2012Assignee: International Business Machines CorporationInventors: Renata Camillo-Castillo, Erik M. Dahlstrom, Qizhi Liu
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Publication number: 20120289018Abstract: A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.Type: ApplicationFiled: July 24, 2012Publication date: November 15, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tak H. Ning, Kevin K. Chan, Marwan H. Khater
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Patent number: 8304302Abstract: A photovoltaic device and methods for forming the same. In one embodiment, the photovoltaic device has a silicon substrate, and a film comprising a plurality of single wall carbon nanotubes disposed on the silicon substrate, wherein the plurality of single wall carbon nanotubes forms a plurality of heterojunctions with the silicon in the substrate.Type: GrantFiled: April 1, 2010Date of Patent: November 6, 2012Assignee: Board of Trustees of the University of ArkansasInventors: Alexandru S. Biris, Zhongrui Li
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Patent number: 8298901Abstract: An improved method for manufacturing bipolar transistors is disclosed. The method for forming a PNP transistor comprises the steps of forming a P type collector on a substrate, forming a PNP epitaxial base on the P type collector, forming a PNP extrinsic base in the PNP epitaxial base, and forming a PNP emitter in contact with the PNP extrinsic base. The method for forming an NPN transistor comprises the steps of forming an N type collector on a substrate, forming a NPN epitaxial base on the N type collector, forming an NPN extrinsic base in the NPN epitaxial base, and forming an NPN emitter in contact with the NPN extrinsic base. The PNP and NPN transistors may be manufactured in the same control flow process.Type: GrantFiled: May 26, 2006Date of Patent: October 30, 2012Assignee: National Semiconductor CorporationInventors: Richard W. Foote, Edward F. Pressley, Joseph A. DeSantis, Alexei Sadovnikov, Christoher J. Knorr
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Publication number: 20120248573Abstract: Embodiments of the invention include a method for forming a tunable semiconductor device and the resulting structure. The invention comprises forming a semiconductor substrate. Next, pattern a first mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the first mask to form a first discontinuous subcollector. Remove the first mask. Pattern a second mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the second mask and on top of the first discontinuous subcollector to form a second discontinuous subcollector. Remove the second mask and form a collector above the second discontinuous subcollector. Breakdown voltage of the device may be tuned by varying the gaps separating doped regions within the first and second discontinuous subcollectors. Doped regions of the first and second discontinuous subcollectors may be formed in a mesh pattern.Type: ApplicationFiled: March 31, 2011Publication date: October 4, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Louis Harame, Alvin Jose Joseph, Qizhi Liu, Ramana Murty Malladi
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Publication number: 20120235143Abstract: A vertical heterojunction bipolar transistor (HBT) includes doped polysilicon having a doping of a first conductivity type as a wide-gap-emitter with an energy bandgap of about 1.12 eV and doped single crystalline Ge having a doping of the second conductivity type as the base having the energy bandgap of about 0.66 eV. Doped single crystalline Ge having of doping of the first conductivity type is employed as the collector. Because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. Further, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.Type: ApplicationFiled: March 15, 2011Publication date: September 20, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jin Cai, Kevin K. Chan, Wilfried E. Haensch, Tak H. Ning
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Publication number: 20120235151Abstract: A horizontal heterojunction bipolar transistor (HBT) includes doped single crystalline Ge having a doping of the first conductivity type as the base having an energy bandgap of about 0.66 eV, and doped polysilicon having a doping of a second conductivity type as a wide-gap-emitter having an energy bandgap of about 1.12 eV. In one embodiment, doped polysilicon having a doping of the second conductivity type is employed as the collector. In other embodiments, a single crystalline Ge having a doping of the second conductivity type is employed as the collector. In such embodiments, because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. In both embodiments, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.Type: ApplicationFiled: March 15, 2011Publication date: September 20, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jin Cai, Kevin K. Chan, Wilfried W. Haensch, Tak H. Ning
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Patent number: 8242500Abstract: Disclosed is a method of forming a heterojunction bipolar transistor (HBT), comprising depositing a first stack comprising an polysilicon layer (16) and a sacrificial layer (18) on a mono-crystalline silicon substrate surface (10); patterning the first stack to form a trench (22) extending to the substrate; depositing a silicon layer (24) over the resultant structure; depositing a silicon-germanium-carbon layer (26) over the resultant structure; selectively removing the silicon-germanium-carbon layer (26) from the sidewalls of the trench (22); depositing a boron-doped silicon-germanium-carbon layer (28) over the resultant structure; depositing a further silicon-germanium-carbon layer (30) over the resultant structure; depositing a boron-doped further silicon layer (32) over the resultant structure; forming dielectric spacers (34) on the sidewalls of the trench (22); filling the trench (22) with an emitter material (36); exposing polysilicon regions (16) outside the side walls of the trench by selectively remoType: GrantFiled: January 12, 2011Date of Patent: August 14, 2012Assignee: NXP B.V.Inventors: Philippe Meunier-Beillard, Johannes Josephus Theodorus Marinus Donkers, Hans Mertens, Tony Vanhoucke
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Publication number: 20120199881Abstract: High frequency performance of (e.g., silicon) bipolar devices (100) is improved by reducing the extrinsic base resistance Rbx. Emitter (160), intrinsic base (161, 163) and collector (190) are formed in a semiconductor body (115). An emitter contact (154) has a region (1541) that overlaps a portion (1293, 1293?) of an extrinsic base contact (129). A sidewall (1294) is formed in the extrinsic base contact (129) proximate a lateral edge (1543) of the overlap region (1541) of the emitter contact (154). The sidewall (1294) is amorphized during or after formation so that when the emitter contact (154) and the extrinsic base contact (129) are, e.g., silicided, some of the metal atoms forming the silicide penetrate into the sidewall (1294) so that part (183) of the highly conductive silicided extrinsic base contact (182, 183) extends under the edge (1543) of the overlap region (1541) of the emitter contact (154) closer to the intrinsic base (161, 163), thereby reducing Rbx.Type: ApplicationFiled: February 9, 2011Publication date: August 9, 2012Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Jay P. John, James A. Kirchgessner, Vishal P. Trivedi
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Publication number: 20120181579Abstract: A vertical parasitic PNP device in a SiGe HBT process is disclosed which comprises a collector region, a base region, an emitter region, P-type pseudo buried layers and N-type polysilicons. The pseudo buried layers are formed at bottom of shallow trench field oxide regions around the collector region and contact with the collector region; deep hole contacts are formed on top of the pseudo buried layers to pick up collector electrodes. The N-type polysilicons are formed on top of the base region and are used to pick up base electrodes. The emitter region comprises a P-type SiGe epitaxial layer and a P-type polysilicon both of which are formed on top of the base region. A manufacturing method of a vertical parasitic PNP device in a SiGe HBT process is also disclosed.Type: ApplicationFiled: December 19, 2011Publication date: July 19, 2012Inventors: Fan Chen, Xiongbin Chen
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Patent number: 8212288Abstract: A compound semiconductor substrate which inhibits the generation of a crack or a warp and is preferable for a normally-off type high breakdown voltage device, arranged that a multilayer buffer layer 2 in which AlxGa1-xN single crystal layers (0.6?X?1.0) 21 containing carbon from 1×1018 atoms/cm3 to 1×1021 atoms/cm3 and AlyGa1-yN single crystal layers (0.1?y?0.5) 22 containing carbon from 1×1017 atoms/cm3 to 1×1021 atoms/cm3 are alternately and repeatedly stacked in order, and a nitride active layer 3 provided with an electron transport layer 31 having a carbon concentration of 5×1017 atoms/cm3 or less and an electron supply layer 32 are deposited on a Si single crystal substrate 1 in order. The carbon concentrations of the AlxGa1-xN single crystal layers 21 and that of the AlGa1-yN single crystal layers 22 respectively decrease from the substrate 1 side towards the above-mentioned active layer 3 side. In this way, the compound semiconductor substrate is produced.Type: GrantFiled: September 10, 2010Date of Patent: July 3, 2012Assignee: Covalent Materials CorporationInventors: Jun Komiyama, Kenichi Eriguchi, Hiroshi Oishi, Yoshihisa Abe, Akira Yoshida, Shunichi Suzuki
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Publication number: 20120139009Abstract: A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.Type: ApplicationFiled: December 2, 2010Publication date: June 7, 2012Applicant: International Business Machine CorporationInventors: Tak H. Ning, Kevin K. Chan, Marwan H. Khater
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Publication number: 20120119262Abstract: A SiGe heterojunction bipolar transistor is fabricated by etching an epitaxially-formed structure to form a mesa that has a collector region, a cap region, and a notched SiGe base region that lies in between. A protective plug is formed in the notch of the SiGe base region so that thick non-conductive regions can be formed on the sides of the collector region and the cap region. Once the non-conductive regions have been formed, the protective plug is removed. An extrinsic base is then formed to lie in the notch and touch the base region, followed by the formation of isolation regions and an emitter region.Type: ApplicationFiled: November 15, 2010Publication date: May 17, 2012Inventors: Wibo Van Noort, Jamal Ramdani, Andre Labonte, Donald Robertson Getchell
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Publication number: 20120112244Abstract: Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening.Type: ApplicationFiled: November 4, 2010Publication date: May 10, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Renata Camillo-Castillo, Erik M. Dahlstrom, Qizhi Liu
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Publication number: 20120098039Abstract: A SiGe HBT having low collector-base capacitance is disclosed, which includes: a silicon substrate, including isolation trenches, a collector region situated between the isolation trenches, and lateral trenches; a SiGe base layer formed on the silicon substrate; and an emitter region formed on the SiGe base layer. Each lateral trench is situated in the collector region on one side of an isolation trench, and is connected to the isolation trench. Moreover, a manufacturing method of a SiGe HBT having low collector-base capacitance is disclosed, which includes: performing ion implantation to predetermined regions in a silicon substrate before trench isolations are formed; forming lateral trenches by etching ion implantation regions after the trench isolations are formed; then forming a SiGe HBT device by an ordinary semiconductor process. The present invention can reduce the collector-base capacitance and therefore improve high-frequency characteristics of the device.Type: ApplicationFiled: October 24, 2011Publication date: April 26, 2012Inventors: Yan Miu, Changwa Yao, Hu Peng
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Patent number: 8159287Abstract: A field-effect transistor device, including: a semiconductor heterostructure comprising, in a vertically stacked configuration, a semiconductor gate layer between semiconductor source and drain layers, the layers being separated by heterosteps; the gate layer having a thickness of less than about 100 Angstroms; and source, gate, and drain electrodes respectively coupled with said source, gate, and drain layers. Separation of the gate by heterosteps, rather than an oxide layer, has very substantial advantages.Type: GrantFiled: October 10, 2008Date of Patent: April 17, 2012Assignee: The Board of Trustees of the University of IllinoisInventors: Milton Feng, Nick Holonyak, Jr.
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Patent number: 8148737Abstract: Disclosed are a light emitting device, a light emitting device package and a lighting system. The light emitting device of the embodiment includes a light emitting structure including a first conductive semiconductor layer, an active layer over the first conductive semiconductor layer, and a second conductive semiconductor layer over the active layer; a dielectric layer over a first region of the first conductive semiconductor layer; a second electrode over the dielectric layer; and a first electrode over a second region of the first conductive semiconductor layer.Type: GrantFiled: October 21, 2010Date of Patent: April 3, 2012Assignee: LG Innotek Co., Ltd.Inventor: Sung Min Hwang
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Publication number: 20120064688Abstract: A manufacturing method of a SiGe HBT is disclosed. Alter an emitter region is formed, an ion implantation is performed with a tilt angle to a base region by using an extrinsic base ion implantation process; boron ions are implanted during the extrinsic base ion implantation with an implantation dose from 1e15 to 1e16 cm?2, an implantation energy from 5 to 30 KeV, and a tilt angle from 5 to 30 degrees. The tilt angle enables the implantation of P-type impurities into the part of the intrinsic base region at the bottom of the emitter window dielectric layer as well as the extrinsic base region, so that the base region excluding the part of the intrinsic base region in contact with the emitter region is entirely doped with P-type impurities, thus reducing the base resistance and improving the frequency characteristic of a transistor without needing to reduce its size.Type: ApplicationFiled: September 9, 2011Publication date: March 15, 2012Inventors: Fan Chen, Xionbing Chen, Zhengliang Zhou
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Patent number: 8133791Abstract: The invention relates to a method according to the part of the surface of the semiconductor body adjoining the opening and which is to be kept free is provided with a cover layer after which the high-crystalline layer is formed by means of a deposition process. The material of the cover layer can then easily be chosen such that it can be selectively etched relative to the silicon underneath. In addition, the cover layer can easily be selectively deposited on the relevant part of the surface because use can be made of an anisotropic deposition process. In such a process the cover layer is not deposited in the hollow and on the bottom of the hollow. It will be apparent that for the high-crystalline layer also other materials can be chosen such as SiGe having such low Ge contents that the SiGe cannot be etched selectively very well compared to the Silicon.Type: GrantFiled: June 12, 2007Date of Patent: March 13, 2012Assignee: NXP B.V.Inventors: Erwin B. Hijzen, Philippe Meunier-Bellard, Johannes J. T. M. Donkers
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Publication number: 20120037914Abstract: A method of manufacturing a heterojunction bipolar transistor, including providing a substrate comprising an active region bordered by shallow trench insulation regions; depositing a stack of a dielectric layer and a polysilicon layer over the substrate; forming a base window in the stack, the base window extending over the active region and part of the shallow trench insulation regions, the base window having a trench extending vertically between the active region and one of the shallow trench insulation regions; growing an epitaxial base material inside the base window; forming a spacer on the exposed side walls of the base material; and filling the base window with an emitter material. A HBT manufactured in this manner and an IC including such an HBT.Type: ApplicationFiled: August 9, 2011Publication date: February 16, 2012Applicant: NXP B.V.Inventors: Tony Vanhoucke, Johannes Josephus Theodorus Marinus Donkers, Hans Mertens, Blandine Duriez, Evelyne Marie Josephe Fabienne Gridelet
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Publication number: 20120001192Abstract: A semiconductor device, comprising a substrate layer made of a semiconductor material of a first conductivity type and having a first insulation region, and a vertical bipolar transistor having a first vertical portion of a collector made of monocrystalline semiconductor material of a second conductivity type and disposed in an opening of the first insulation region, a second insulation region lying partly on the first vertical portion of the collector and partly on the first insulation region and having an opening in the region of the collector, in which opening a second vertical portion of the collector made of monocrystalline material is disposed, said portion including an inner region of the second conductivity type, a base made of monocrystalline semiconductor material of the first conductivity type, a base connection region surrounding the base in the lateral direction, a T-shaped emitter made of semiconductor material of the second conductivity type and overlapping the base connection region, wherein tType: ApplicationFiled: December 3, 2009Publication date: January 5, 2012Inventors: Alexander Fox, Bernd Heinemann, Steffen Marschmeyer
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Publication number: 20110269289Abstract: A method of manufacturing a transistor device (600), wherein the method comprises forming a trench (106) in a substrate (102), only partially filling the trench (106) with electrically insulating material (202), and implanting a collector region (304) of a bipolar transistor (608) of the transistor device (600) through the only partially filled trench (106).Type: ApplicationFiled: July 8, 2009Publication date: November 3, 2011Applicant: NXP B.V.Inventors: Philippe Meunier-Beillard, Hans Mertens
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Patent number: 8026146Abstract: The invention provides for an alternative and less complex method of manufacturing a bipolar transistor comprising a field plate (17) in a trench (7) adjacent to a collector region (21), which field plate (17) employs a reduced surface field (Resurf) effect. The Resurf effect reshapes the electric field distribution in the collector region (21) such that for the same collector-base breakdown voltage the doping concentration of the collector region (21) can effectively be increased resulting in a reduced collector resistance and hence an increased bipolar transistor speed. The method comprises a step of forming a base window (6) in a first base layer (4) thereby exposing a top surface of the collector region (21) and a part of an isolation region (3). The trench (7) is formed by removing the exposed part of the isolation region (3), after which isolation layers (9,10) are formed on the surface of the trench (7).Type: GrantFiled: August 29, 2007Date of Patent: September 27, 2011Assignee: NXP B.V.Inventors: Johannes J. T. M. Donkers, Sebastien Nuttinck, Guillaume L. R. Boccardi, Francois Neuilly
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Publication number: 20110230031Abstract: A method for forming a germanium-enriched region in a heterojunction bipolar transistor and a heterojunction bipolar transistor comprising a germanium-enriched region. A base having a silicon-germanium portion is formed over a collector. Thermal oxidation of the base causes a germanium-enriched region to form on a surface of the silicon-germanium portion subjected to the thermal oxidation. An emitter is formed overlying the germanium-enriched portion region. The germanium-enriched region imparts advantageous operating properties to the heterojunction bipolar transistor, including improved high-frequency/high-speed operation.Type: ApplicationFiled: March 22, 2010Publication date: September 22, 2011Inventor: Michelle D. Griglione
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Patent number: 8017975Abstract: A semiconductor device and manufacturing method satisfies both of the trade-off characteristic advantages of the HBT and the HFET. The semiconductor device is an HBT and HFET integrated circuit. The HBT includes a sub-collector layer, a GaAs collector layer, a GaAs base layer, and an InGaP emitter layer that are sequentially stacked. The sub-collector layer includes a GaAs external sub-collector region, and a GaAs internal sub-collector region disposed on the GaAs external sub-collector region. A mesa-shaped collector part and a collector electrode are separately formed on the GaAs external sub-collector region. The HFET includes a GaAs cap layer, a source electrode, and a drain electrode. The GaAs cap layer includes a portion of the GaAs external sub-collector region. The source electrode and the drain electrode are formed on the GaAs cap layer.Type: GrantFiled: March 9, 2009Date of Patent: September 13, 2011Assignee: Panasonic CorporationInventors: Keiichi Murayama, Akiyoshi Tamura, Hirotaka Miyamoto, Kenichi Miyajima
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Publication number: 20110198671Abstract: The invention relates to a semiconductor device (30) comprising a substrate (1), a semiconductor body (25) comprising a bipolar transistor that comprises a collector region (3), a base region (4), and an emitter region (15), wherein at least a portion of the collector region (3) is surrounded by a first isolation region (2, 8), the semiconductor body (25) further comprises an extrinsic base region (35) arranged in contacting manner to the base region (4). In this way, a fast semiconductor device with reduced impact of parasitic components is obtained.Type: ApplicationFiled: August 5, 2009Publication date: August 18, 2011Applicants: NXP B.V., INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZWInventors: Guillaume Boccardi, Mark C. J. C. M. Kramer, Johannes J. T. M. Donkers, Li Jen Choi, Stefaan Decoutere, Arturo Sibaja-Hernandez, Stefaan Van Huylenbroeck, Rafael Venegas
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Publication number: 20110198591Abstract: Disclosed is a method of forming a heterojunction bipolar transistor (HBT), comprising depositing a first stack comprising an polysilicon layer (16) and a sacrificial layer (18) on a mono-crystalline silicon substrate surface (10); patterning the first stack to form a trench (22) extending to the substrate; depositing a silicon layer (24) over the resultant structure; depositing a silicon-germanium-carbon layer (26) over the resultant structure; selectively removing the silicon-germanium-carbon layer (26) from the sidewalls of the trench (22); depositing a boron-doped silicon-germanium-carbon layer (28) over the resultant structure; depositing a further silicon-germanium-carbon layer (30) over the resultant structure; depositing a boron-doped further silicon layer (32) over the resultant structure; forming dielectric spacers (34) on the sidewalls of the trench (22); filling the trench (22) with an emitter material (36); exposing polysilicon regions (16) outside the side walls of the trench by selectively remoType: ApplicationFiled: January 12, 2011Publication date: August 18, 2011Applicant: NXP B.V.Inventors: Philippe MEUNIER-BEILLARD, Johannes Josephus Theodorus Marinus DONKERS, Hans MERTENS, Tony VANHOUCKE
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Publication number: 20110121364Abstract: According to an example embodiment, a heterostructure bipolar transistor, HBT, includes shallow trench isolation, STI, structures around a buried collector drift region in contact with a buried collector. A gate stack including a gate oxide and a gate is deposited and etched to define a base window over the buried collector drift region and overlapping the STI structures. The etching process is continued to selectively etch the buried collector drift region between the STI structures to form a base well. SiGeC may be selectively deposited to form epitaxial silicon-germanium in the base well in contact with the buried collector drift region and poly silicon-germanium on the side walls of the base well and base window. Spacers are then formed as well as an emitter.Type: ApplicationFiled: October 26, 2010Publication date: May 26, 2011Applicant: NXP B.V.Inventors: Johannes Josephus Theodorus Marinus DONKERS, Tony VANHOUCKE, Hans MERTENS
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Patent number: 7923340Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device. In one aspect, the method provides for a dual implantation of a tub of a bipolar transistor. The tub in bipolar region is implanted by implanting the tub through separate implant masks that are also used to implant tubs associated with MOS fabricate different voltage devices in a non-bipolar region during the fabrication of MOS transistors.Type: GrantFiled: February 14, 2007Date of Patent: April 12, 2011Assignee: Agere Systems Inc.Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh, Xiaojun Yuan
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Publication number: 20110073907Abstract: A method for pseudomorphic growth and integration of an in-situ doped, strain-compensated metastable compound base into an electronic device, such as, for example, a SiGe NPN HBT, by substitutional placement of strain-compensating atomic species. The invention also applies to strained layers in other electronic devices such as strained SiGe, Si in MOS applications, vertical thin film transistors (VTFT), and a variety of other electronic device types. Devices formed from compound semiconductors other than SiGe, such as, for example, GaAs, InP, and AlGaAs are also amenable to beneficial processes described herein.Type: ApplicationFiled: October 11, 2010Publication date: March 31, 2011Applicant: Atmel CorporationInventors: Darwin G. Enicks, John Taylor Chaffee, Damian A. Carver
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Patent number: 7915640Abstract: A metamorphic buffer layer is formed on a semi-insulating substrate by an epitaxial growth method, a collector layer, a base layer, an emitter layer and an emitter cap layer are sequentially laminated on the metamorphic buffer layer, and a collector electrode is provided in contact with an upper layer of the metamorphic buffer layer. The metamorphic buffer layer is doped with an impurity, in a concentration equivalent to or higher than that in a conventional sub-collector layer, by an impurity doping process during crystal growth so that the metamorphic buffer layer will be able to play the role of guiding the collector current to the collector electrode. Since the sub-collector layer, which is often formed of a ternary mixed crystal or the like having a high thermal resistance, can be omitted, the heat generated in the semiconductor device can be rapidly released into the substrate.Type: GrantFiled: May 19, 2006Date of Patent: March 29, 2011Assignee: Sony CorporationInventor: Masaya Uemura
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Patent number: 7902571Abstract: A field effect transistor (FET) with high withstand voltage and high performance is realized by designing a buffer layer structure appropriately to reduce a leakage current to 1×10?9 A or less when a low voltage is applied. An epitaxial wafer for a field effect transistor comprising a buffer layer 2, an active layer, and a contact layer on a semi-insulating substrate 1 from the bottom, and the buffer layer 2 includes a plurality of layers, and a p-type buffer layer composed of p-type AlxGa1-xAs (0.3?x?1) is provided as a bottom layer (undermost layer) 2a. A Nd product of a film thickness of the p-type buffer layer and a p-type carrier concentration of the p-type buffer layer is within a range from 1×1010 to 1×1012/cm2.Type: GrantFiled: December 14, 2005Date of Patent: March 8, 2011Assignee: Hitachi Cable, Ltd.Inventors: Ryota Isono, Takashi Takeuchi
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Publication number: 20110049517Abstract: A bipolar transistor has a collector having a base layer provided thereon and a shallow trench isolation structure formed therein. A base poly layer is provided on the shallow trench isolation structure. The shallow trench isolation structure defines a step such that a surface of the collector projects from the shallow trench isolation structure adjacent the collector.Type: ApplicationFiled: September 2, 2010Publication date: March 3, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Klaus SCHIMPF, Manfred SCHIEKOFER, Carl David WILLIS, Michael WAITSCHULL, Wolfgang PLOSS
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Patent number: 7875523Abstract: A heterojunction bipolar transistor is formed with an emitter electrode that comprises an emitter epitaxy underlying an emitter metal cap and that has horizontal dimensions that are substantially equal to the emitter metal cap.Type: GrantFiled: June 16, 2005Date of Patent: January 25, 2011Assignee: HRL Laboratories, LLCInventor: Charles H. Fields
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Patent number: 7843006Abstract: A semiconductor component arrangement includes a power transistor and a temperature measurement circuit. The power transistor includes a gate electrode, a source zone, a drain zone and a body zone. The body zone is arranged in a first semiconductor zone of a first conduction type. The temperature measuring circuit comprises a temperature-dependent resistor and an evaluation circuit coupled to the temperature-dependent resistor. The resistor is formed by a portion of said first semiconductor zone.Type: GrantFiled: February 1, 2007Date of Patent: November 30, 2010Assignee: Infineon Technologies AGInventors: Rainald Sander, Markus Zundel
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Patent number: 7842973Abstract: A semiconductor device capable of avoiding generation of a barrier in a conduction band while maintaining high withstanding voltage and enabling high speed transistor operation at high current in a double hetero bipolar transistor, as well as a manufacturing method thereof, wherein a portion of the base and the collector is formed of a material with a forbidden band width narrower than that of a semiconductor substrate, a region where the forbidden band increases stepwise and continuously from the emitter side to the collector side is disposed in the inside of the base and the forbidden band width at the base-collector interface is designed so as to be larger than the minimum forbidden band width in the base, whereby the forbidden band width at the base layer edge on the collector side can be made closer to the forbidden band width of the semiconductor substrate than usual while sufficiently maintaining the hetero effect near the emitter-base thereby capable of decreasing the height of the energy barrier geneType: GrantFiled: July 13, 2006Date of Patent: November 30, 2010Assignee: Hitachi, Ltd.Inventors: Makoto Miura, Katsuyoshi Washio, Hiromi Shimamoto
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Publication number: 20100283084Abstract: The bipolar transistor includes a heterojunction intrinsic base layer epitaxially grown on a collector layer. The intrinsic base layer is disposed on the collector layer surrounded by an isolation layer, and an N-type impurity layer is formed in a surface portion of the collector layer. The impurity concentration of the N-type impurity layer is higher than the impurity concentration of the collector layer under the N-type impurity layer. Between the N-type impurity layer and the intrinsic base layer, an epitaxially grown layer is formed, where the epitaxially grown layer is lower in impurity concentration than the N-type impurity layer and the intrinsic base layer.Type: ApplicationFiled: March 24, 2010Publication date: November 11, 2010Inventors: Teruhito Ohnishi, Ken Idota, Atsushi Nakamura
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Patent number: 7821032Abstract: An enhancement mode III-nitride power semiconductor device that includes normally-off channels along the sidewalls of a recess and a process for fabricating the same, the device including a first power electrode, a second power electrode, and a gate disposed between the first power electrode and the second power electrode over at least a sidewall of the recess.Type: GrantFiled: January 26, 2007Date of Patent: October 26, 2010Assignee: International Rectifier CorporationInventor: Daniel M Kinzer
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Patent number: 7755161Abstract: A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The device further comprises a reach-through structure connecting the first and second sub-collectors and an N-well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. The device further comprises N+ diffusion regions in contact with the N-well, a P+ diffusion region in contact with the N-well, and shallow trench isolation structures between the N+ and P+ diffusion regions.Type: GrantFiled: September 24, 2008Date of Patent: July 13, 2010Assignee: International Business Machines CorporationInventors: Xuefeng Liu, Robert M. Rassel, Steven H. Voldman
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Publication number: 20100171151Abstract: An HBT according to this invention includes: a sub-collector layer; a collector layer formed on the sub-collector layer and the base layer including a first collector layer, a second collector layer, a third collector layer, and a fourth collector layer. The first collector layer is formed on the sub-collector layer, and is made of semiconductor different from semiconductor of which the second to the fourth collector layers are made. The fourth collector layer is formed on the first collector layer, and has an impurity concentration lower than an impurity concentration of the second collector layer. The second collector layer is formed on the fourth collector layer, and has an impurity concentration lower than an impurity concentration of the sub-collector layer and higher than an impurity concentration of the third collector layer. The third collector layer is formed between the second collector layer and the base layer.Type: ApplicationFiled: December 29, 2009Publication date: July 8, 2010Applicant: PANASONIC CORPORATIONInventors: Kenichi MIYAJIMA, Akiyoshi TAMURA, Keiichi MURAYAMA, Hirotaka MIYAMOTO
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Publication number: 20100159664Abstract: Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.Type: ApplicationFiled: March 8, 2010Publication date: June 24, 2010Applicant: International Business Machines CorporationInventors: Oleg Gluschenkov, Rajendran Krishnasamy, Kathryn T. Schonenberg
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Publication number: 20100140587Abstract: A method for manufacturing high-injection heterojunction bipolar transistor capable of being used as a photonic device is disclosed. A sub-collector layer is formed on a substrate. A collector layer is then deposited on top of the sub-collector layer. After a base layer has been deposited on top of the collector layer, a quantum well layer is deposited on top of the base layer. An emitter is subsequently formed on top of the quantum well layer.Type: ApplicationFiled: October 16, 2008Publication date: June 10, 2010Inventors: Daniel N. Carothers, Andrew T.S. Pomerene
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Publication number: 20100133586Abstract: Provided are a heterojunction bipolar transistor and a method of forming the same.Type: ApplicationFiled: May 8, 2009Publication date: June 3, 2010Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Byoung-Gue MIN, Jong-Min Lee, Seong-II Kim, Kyung-Ho Lee, Hyung-Sup Yoon, Eun-Soo Nam
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Publication number: 20100133549Abstract: A semiconductor device may include a semiconductor buffer layer having a first conductivity type and a semiconductor mesa having the first conductivity type on a surface of the buffer layer. In addition, a current shifting region having a second conductivity type may be provided adjacent a corner between the semiconductor mesa and the semiconductor buffer layer, and the first and second conductivity types may be different conductivity types. Related methods are also discussed.Type: ApplicationFiled: July 30, 2009Publication date: June 3, 2010Inventors: Qingchun Zhang, Anant K. Agarwal
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Patent number: 7723753Abstract: In a GaAs substrate as a semi-insulating substrate, a heterojunction bipolar transistor (HBT) is formed in an element formation region, while an isolation region is formed in an insulating region. The isolation region formed in the insulating region is formed by introducing helium into the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT. In an outer peripheral region, a conductive layer is formed to be exposed from protective films and coupled to a back surface electrode. Because a GND potential is supplied to the back surface electrode, the conductive layer is fixed to the GND potential. The conductive layer is formed of the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT.Type: GrantFiled: December 21, 2007Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventors: Kenji Sasaki, Ikuro Akazawa, Yoshinori Imamura, Atsushi Kurokawa, Tatsuhiko Ikeda, Hiroshi Inagawa, Yasunari Umemoto, Isao Obu
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Patent number: RE42423Abstract: Provided is a process for forming a contact for a compound semiconductor device without electrically shorting the device. In one embodiment, a highly doped compound semiconductor material is electrically connected to a compound semiconductor material of the same conductivity type through an opening in a compound semiconductor material of the opposite conductivity type. Another embodiment discloses a transistor including multiple compound semiconductor layers where a highly doped compound semiconductor material is electrically connected to a compound semiconductor layer of the same conductivity type through an opening in a compound semiconductor layer of the opposite conductivity type. Embodiments further include metal contacts electrically connected to the highly doped compound semiconductor material. A substantially planar semiconductor device is disclosed. In embodiments, the compound semiconductor material may be silicon carbide.Type: GrantFiled: November 7, 2008Date of Patent: June 7, 2011Assignee: Fairchild Semiconductor CorporationInventors: Martin E. Kordesch, Howard D. Bartlow, Richard L. Woodin