Abstract: Methods are provided for forming a device that includes merged vertical and lateral transistors with collector regions of a first conductivity type between upper and lower base regions of opposite conductivity type that are Ohmically coupled via intermediate regions of the same conductivity type and to the base contact. The emitter is provided in the upper base region and the collector contact is provided in outlying sinker regions extending to the thin collector regions and an underlying buried layer. As the collector voltage increases part of the thin collector regions become depleted of carriers from the top by the upper and from the bottom by the lower base regions. This clamps the collector regions' voltage well below the breakdown voltage of the PN junction formed between the buried layer and the lower base region. The gain and Early Voltage are increased and decoupled and a higher breakdown voltage is obtained.

Abstract: A power LDMOS device including a substrate, source and drain regions, gates and trench insulating structures is provided. The substrate has a finger tip area, a finger body area and a palm area. The source regions are in the substrate in the finger body area and further extend to the finger tip area. The neighboring source regions in the finger tip area are connected. The outmost two source regions further extend to the palm area and are connected. The drain regions are in the substrate in the finger body area and further extend to the palm area. The neighboring drain regions in the palm area are connected. The source and drain regions are disposed alternately. A gate is disposed between the neighboring source and drain regions. The trench insulating structures are in the substrate in the palm area and respectively surround ends of the drain regions.

Abstract: An improved device (20) is provided, comprising, merged vertical (251) and lateral transistors (252), comprising thin collector regions (34) of a first conductivity type sandwiched between upper (362) and lower (30) base regions of opposite conductivity type that are Ohmically coupled via intermediate regions (32, 361) of the same conductivity type and to the base contact (38). The emitter (40) is provided in the upper base region (362) and the collector contact (42) is provided in outlying sinker regions (28) extending to the thin collector regions (34) and an underlying buried layer (28). As the collector voltage increases part of the thin collector regions (34) become depleted of carriers from the top by the upper (362) and from the bottom by the lower (30) base regions. This clamps the thin collector regions' (34) voltage well below the breakdown voltage of the PN junction formed between the buried layer (28) and the lower base region (30).

Abstract: A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.

Abstract: A LDMOS structure includes a gate, a source, a drain and a bulk. The gate includes a polycrystalline silicon layer, the source includes a P-implanted layer, the drain includes the P-implanted layer, a P-well layer, and a deep P-well layer. A bulk terminal is connected through the P-implanted layer, the P-well layer, the deep P-well layer, and a P-type buried layer to the bulk. The LDMOS structure is able to be produced without any extra masking step, and it has compact structure, low on-resistance, and is able to withstand high current and high voltage.

Abstract: An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.

Abstract: A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.

Abstract: A lateral bipolar transistor with deep emitter and deep collector regions is formed using multiple epitaxial layers of the same conductivity type. Deep emitter and deep collector regions are formed without the use of trenches. Vertically aligned diffusion regions are formed in each epitaxial layer so that the diffusion regions merged into a contiguous diffusion region after annealing to function as emitter or collector or isolation structures. In another embodiment, a lateral trench PNP bipolar transistor is formed using trench emitter and trench collector regions. In yet another embodiment, a lateral PNP bipolar transistor with a merged LDMOS transistor is formed to achieve high performance.

Abstract: A semiconductor device includes a transistor with a substrate on which source and drain regions, both of a first conductivity type, and a channel region of a second conductivity type between the source and drain are formed, and a gate electrode formed in the channel region to bury a trench formed so the depth thereof changes intermittently in the width direction of the gate. In the channel region, each on a surface of the substrate and in a bottom portion of the trench, there are formed a second high-concentration region and a first high-concentration region, and the dopant concentration of the second conductivity type is higher than the dopant concentration of the second conductivity type in portions sideward from the trench. The dopant concentration of the second conductivity type in the first high-concentration region is higher than the dopant concentration of the second conductivity type in the second high-concentration region.

Abstract: An integrated circuit includes a bipolar transistor disposed over a substrate. The bipolar transistor includes a base electrode disposed around at least one germanium-containing layer. An emitter electrode is disposed over the at least one germanium-containing layer. At least one isolation structure is disposed between the emitter electrode and the at least one germanium-containing layer. A top surface of the at least one isolation structure is disposed between and electrically isolating a top surface of the emitter electrode from a top surface of the at least one germanium-containing layer.

Abstract: A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.

Abstract: The present invention provides a self-driven LDMOS which utilizes a parasitic resistor between a drain terminal and an auxiliary region. The parasitic resistor is formed between two depletion boundaries in a quasi-linked deep N-type well. When the two depletion boundaries pinch off, a gate-voltage potential at a gate terminal is clipped at a drain-voltage potential at said drain terminal. Since the gate-voltage potential is designed to be equal to or higher than a start-threshold voltage, the LDMOS is turned on accordingly. Besides, no additional die space and masking process are needed to manufacture the parasitic resistor. Furthermore, the parasitic resistor of the present invention does not lower the breakdown voltage and the operating speed of the LDMOS. In addition, when the two depletion boundaries pinch off, the gate-voltage potential does not vary in response to an increment of the drain-voltage potential.

Abstract: An electrostatic discharge (EDS) device includes a substrate, an external well of a first conductivity type in the substrate, and an internal well of a second conductivity type in the external well, the first conductivity type opposite the second conductivity type. The EDS device further includes a first heavily doped region of the first conductivity type located at a surface of the internal well, a second heavily doped region of the second conductivity type located at a surface of the internal well, and a third heavily doped region of the first conductivity type located at a surface of the external well. The second heavily doped region is interposed between and spaced from each of the first and third heavily doped regions, and at least one of a space between the first and second heavily doped regions and a space between the second and third heavily doped regions is devoid of a device isolation structure of electrical isolation material.

Abstract: A semiconductor on insulator device has an insulator layer, an active layer (40) on the insulator layer, a lateral arrangement of collector (10), emitter (30) and base (20) on the active layer, and a high Base-dose region (70) extending under the emitter towards the insulator to suppress vertical current flowing under the emitter. This region (70) reduces the dependence of current-gain and other properties on the substrate (Handle-wafer) voltage. This region can be formed of the same doping type as the base, but having a stronger doping. It can be formed by masked alignment in the same step as an n type layer used as the body for a P-type DMOS transistor.

Abstract: In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.

Abstract: An improved device (20) is provided, comprising, merged vertical (251) and lateral transistors (252), comprising thin collector regions (34) of a first conductivity type sandwiched between upper (362) and lower (30) base regions of opposite conductivity type that are Ohmically coupled via intermediate regions (32, 361) of the same conductivity type and to the base contact (38). The emitter (40) is provided in the upper base region (362) and the collector contact (42) is provided in outlying sinker regions (28) extending to the thin collector regions (34) and an underlying buried layer (28). As the collector voltage increases part of the thin collector regions (34) become depleted of carriers from the top by the upper (362) and from the bottom by the lower (30) base regions. This clamps the thin collector regions' (34) voltage well below the breakdown voltage of the PN junction formed between the buried layer (28) and the lower base region (30).

Abstract: An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.

Abstract: A semiconductor device includes at least one active component (18) having a p-n junction (26) on the semiconductor substrate in an active region (19) of the semiconductor substrate (4). A shallow trench isolation pattern is used to form a plurality of longitudinally extending shallow trenches (12) containing insulator (14). These trenches define a plurality of longitudinal active stripes (10) between the shallow trenches (12). The shallow trench isolation depth (ds?) is greater than the junction depth (dsO of the longitudinal active stripes and the width (wsO of the active stripes (10) is less than the depletion length (ldepi) of the p-n junction.

Abstract: Methods for manufacturing trench type semiconductor devices containing thermally unstable refill materials are provided. A disposable material is used to fill the trenches and is subsequently replaced by a thermally sensitive refill material after the high temperature processes are performed. Trench type semiconductor devices manufactured according to method embodiments are also provided.

Abstract: A method for forming a transmission line structure for a semiconductor device includes forming an interlevel dielectric layer over a first metallization level, removing a portion of the interlevel dielectric layer and forming a sacrificial material within one or more voids created by the removal of the portion of the interlevel dielectric layer. A signal transmission line is formed in a second metallization level formed over the interlevel dielectric layer, the signal transmission line being disposed over the sacrificial material. A portion of dielectric material included within the second metallization level is removed so as to expose the sacrificial material, wherein a portion of the sacrificial material is exposed through a plurality of access holes formed through the signal transmission line. The sacrificial material is removed so as to create an air gap beneath the signal transmission line.

Abstract: A method of forming a semiconductor device is disclosed. The method includes providing a floor for a semiconductor device by utilizing a CMOS process. The method further includes providing a BiCMOS-like process on top of the floor to further fabricate the semiconductor device, wherein the BiCMOS-like process and the CMOS process provides the semiconductor device.

Abstract: Conduction between source and drain or emitter and collector regions is an important characteristic in transistor operation, particularly for lateral bipolar transistors. Accordingly, techniques that can facilitate control over this characteristic can mitigate yield loss by promoting the production of transistors that have an increased likelihood of exhibiting desired operational performance. As disclosed herein, well regions are established in a semiconductor substrate to facilitate, among other things, control over the conduction between the source and drain regions of a lateral bipolar transistor, thus mitigating yield loss and other associated fabrication deficiencies. Importantly, an additional mask is not required in establishing the well regions, thus further mitigating (increased) costs associated with promoting desired device performance.

Abstract: An integrated circuit including a semiconductor assembly in thin-film SOI technology is disclosed. One embodiment provides a semiconductor assembly in thin-film SOI technology including a first semiconductor substrate structure of a second conductivity type inverse to a first conductivity type in a semiconductor substrate below a first semiconductor layer, a second semiconductor substrate structure of a second conductivity type in a semiconductor substrate below a second semiconductor layer structure, and a third semiconductor substrate structure of the first conductivity type below the first semiconductor layer structure in the semiconductor substrate and otherwise surrounded by the first semiconductor substrate structure.

Abstract: In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.

Abstract: A method for constructing a bipolar transistor comprising a collector, a base and an emitter, all located over a substrate, the method including steps of: creating a collector layer over the substrate; etching a path through the collector layer to the substrate; and filling the path with a heat-conductive material.

Abstract: A conventional semiconductor device, for example, a lateral PNP transistor has a problem that it is difficult to obtain a desired current-amplification factor while maintaining a breakdown voltage characteristic without increasing the device size. In a semiconductor device, that is a lateral PNP transistor, according to the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. The epitaxial layer is used as a base region. Moreover, molybdenum (Mo) is diffused in the substrate and the epitaxial layer. With this structure, the base current is adjusted, and thereby a desired current-amplification factor (hFE) of the lateral PNP transistor is achieved.