With Single Crystalline Emitter, Collector Or Base Including Extrinsic, Link Or Graft Base Formed On Th E Silicon Substrate, E.g., By Epitaxy, Recrystallization, After Insulating Device Isolation (epo) Patents (Class 257/E21.379)
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Patent number: 10090266Abstract: A semiconductor device includes a semiconductor chip having a semiconductor substrate with chip and boundary regions, and an integrated circuit on the chip region. A center pad is provided on the chip region and on the integrated circuit, and a boundary pad is provided on the boundary region. The semiconductor device further includes a first lower insulating structure having a contact hole exposing the center pad, a second lower insulating structure, at the same vertical level as the first lower insulating structure, and having a first opening exposing the boundary pad to an outside of the first lower insulating structure, a conductive pattern including a contact portion, a conductive line portion, and a bonding pad portion, and an upper insulating structure formed on the first lower insulating structure and the conductive pattern and having a second opening exposing the bonding pad portion to the outside of the semiconductor chip.Type: GrantFiled: July 8, 2016Date of Patent: October 2, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ae-Hee Choi, Sang-ki Kim, Ahyun Jo, Kyo-Seon Choi
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Patent number: 9780003Abstract: A method of forming a Bipolar Junction Transistor (BJT) includes forming an elongated collector line, forming an elongated emitter line parallel to the collector line, and forming an elongated base line parallel to the collector line and positioned between the collector line and the base line. The emitter line, the base line, and the collector line are formed over fin structures.Type: GrantFiled: August 15, 2016Date of Patent: October 3, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hsin Hu, Min-chang Liang, Sun-Jay Chang, Shien-Yang Wu
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Patent number: 9437581Abstract: The LED module includes: a light diffusing substrate having light transmissive properties; an LED chip bonded to a first surface of the light diffusing substrate with a transparent first bond in between; a color converter facing the first surface to cover the LED chip; and a mounting substrate. The color converter is made of transparent material containing phosphor which, when excited by light emitted from the LED chip, emits light having a different color from the LED chip. The mounting substrate includes a diffuse reflection layer diffusely reflecting light emitted from the LED chip and light emitted from the phosphor. The diffuse reflection layer is placed facing a second surface of the light diffusing substrate.Type: GrantFiled: May 24, 2013Date of Patent: September 6, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yoji Urano, Akifumi Nakamura, Hayato Ioka, Ryoji Imai, Jun Goda, Toru Hirano, Masanori Suzuki, Hideaki Hyuga
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Patent number: 9419087Abstract: A Bipolar Junction Transistor (BJT) includes an elongated collector line, an elongated emitter line parallel to the collector line, and an elongated base line parallel to the collector line and positioned between the collector line and the base line. The emitter line, the base line, and the collector line are formed over fin structures.Type: GrantFiled: November 4, 2013Date of Patent: August 16, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hsin Hu, Sun-Jay Chang, Min-Chang Liang, Shien-Yang Wu
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Patent number: 8963247Abstract: Provided is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and a method for the structure's fabrication. The structure comprises a gate situated on the top semiconductor layer, the top semiconductor layer situated over a base oxide layer, and the base oxide layer situated over a handle wafer. The top surface of the handle wafer is amorphized by an inert implant of Xenon or Argon to reduce carrier mobility in the handle wafer and improve electrical signal isolation between the adjacent devices situated in the top semiconductor layer.Type: GrantFiled: November 7, 2012Date of Patent: February 24, 2015Assignee: Newport Fab, LLCInventors: Paul D. Hurwitz, Robert L. Zwingman
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Patent number: 8803276Abstract: A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry.Type: GrantFiled: November 6, 2013Date of Patent: August 12, 2014Assignee: International Business Machines CorporationInventors: Shunhua Chang, Kiran V. Chatty, Robert J. Gauthier, Mujahid Muhammad
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Patent number: 8765584Abstract: A semiconductor device and a manufacturing method therefor, wherein, during lift-off, no cracks due to internal stresses occur in the compound semiconductor layer. A method for manufacturing a semiconductor device having a structure in which a semiconductor layer is bonded on a supporting substrate, including: a device region formation step of forming a device region including the semiconductor layer on a growth substrate through a lift-off layer; a columnar member formation step of forming a columnar member on the growth substrate; a bonding step of bonding the tops of the semiconductor layer and the columnar member to a supporting substrate; a lift-off step of separating the bottom face of the semiconductor layer from the growth substrate by removing the lift-off layer, and not separating the columnar member from the growth substrate; and a step of separating the columnar member from the supporting substrate.Type: GrantFiled: July 26, 2011Date of Patent: July 1, 2014Assignee: Dowa Electronics Materials Co., Ltd.Inventors: Yoshitaka Kadowaki, Tatsunori Toyota
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Patent number: 8609501Abstract: A method of fabricating an integrated circuit including bipolar transistors that reduces the effects of transistor performance degradation and transistor mismatch caused by charging during plasma etch, and the integrated circuit so formed. A fluorine implant is performed at those locations at which isolation dielectric structures between base and emitter are to be formed, prior to formation of the isolation dielectric. The isolation dielectric structures may be formed by either shallow trench isolation, in which the fluorine implant is performed after trench etch, or LOCOS oxidation, in which the fluorine implant is performed prior to thermal oxidation. The fluorine implant may be normal to the device surface or at an angle from the normal. Completion of the integrated circuit is then carried out, including the use of relatively thick copper metallization requiring plasma etch.Type: GrantFiled: April 19, 2012Date of Patent: December 17, 2013Assignee: Texas Instruments IncorporatedInventors: Weidong Tian, Ming-Yeh Chuang, Rajni J. Aggarwal
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Patent number: 8609451Abstract: Fabrication of a single crystal silicon solar cell with an insitu epitaxially deposited very highly doped p-type silicon back surface field obviates the need for the conventional aluminum screen printing step, thus enabling a thinner silicon solar cell because of no aluminum induced bow in the cell. Furthermore, fabrication of a single crystal silicon solar cell with insitu epitaxial p-n junction formation and very highly doped n-type silicon front surface field completely avoids the conventional dopant diffusion step and one screen printing step, thus enabling a cheaper manufacturing process.Type: GrantFiled: March 19, 2012Date of Patent: December 17, 2013Assignee: Crystal Solar Inc.Inventors: Tirunelveli S. Ravi, Ashish Asthana
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Patent number: 8597993Abstract: A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry.Type: GrantFiled: March 14, 2008Date of Patent: December 3, 2013Assignee: International Business Machines CorporationInventors: Shunhua Chang, Kiran V. Chatty, Robert J. Gauthier, Jr., Mujahid Muhammad
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Patent number: 8541812Abstract: A semiconductor device (10) comprising a bipolar transistor and a field effect transistor within a semiconductor body (1) comprising a projecting mesa (5) within which are at least a portion of a collector region (22d and 22e) and a base region (33d) of the bipolar transistor. The bipolar transistor is provided with a first insulating cavity (92) provided in the collector region (22d and 22e). The base region (33d) is narrower in the plane of the substrate than the collector region (22d and 22e) due to a second insulating cavity (94) provided around the base region (33d) and between the collector region (22d and 22e) and the emitter region (4). By blocking diffusion from the base region the first insulating cavity (92) provides a reduction in the base collector capacitance and can be described as defining the base contact.Type: GrantFiled: February 26, 2009Date of Patent: September 24, 2013Assignee: NXP B.V.Inventors: Philippe Meunier-Beillard, Mark C. J. C. M. Kramer, Johannes J. T. M. Donkers, Guillaume Boccardi
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Patent number: 8476675Abstract: A semiconductor device (10) comprising a bipolar transistor and a field 5 effect transistor within a semiconductor body (1) comprising a projecting mesa (5) within which are at least a portion of a collector region (22c and 22d) and a base region (33c) of the bipolar transistor. The bipolar transistor is provided with an insulating cavity (92b) provided in the collector region (22c and 22d). The insulating cavity (92b) may be provided by providing a layer (33a) in the collector region (22c), creating an access path, for example by selectively etching polysilicon towards monocrystalline, and removing a portion of the layer (33a) to provide the cavity using the access path. The layer (33a) provided in the collector region may be of SiGe:C. By blocking diffusion from the base region the insulating cavity (92b) provides a reduction in the base collector capacitance and can be described as defining the base contact.Type: GrantFiled: February 26, 2009Date of Patent: July 2, 2013Assignee: NXP B.V.Inventors: Philippe Meunier-Beillard, Johannes J. T. M. Donkers, Erwin Hijzen
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Patent number: 8318555Abstract: A method for producing a hybrid substrate includes preparing a first substrate including a mixed layer and an underlying electrically insulating continuous layer, the mixed layer made up of first single-crystal areas and second adjacent amorphous areas, the second areas making up at least part of the free surface of the first substrate. A second substrate is bonded to the first substrate, the second substrate including on the surface thereof, a reference layer with a predetermined crystallographic orientation. The first substrate is bonded to the second substrate by hydrophobic molecular bonding of at least the amorphous areas. A recrystallization of at least part of the amorphous areas to solid phase is carried out according to the crystallographic orientation of the reference layer, and the two substrates are separated at the bonding interface.Type: GrantFiled: October 29, 2009Date of Patent: November 27, 2012Assignee: Commissariat a l'Energie Atomique et aux Energies AlternativesInventors: Thomas Signamarcheix, Franck Fournel, Laurent Clavelier, Chrystel Deguet
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Patent number: 8227326Abstract: A crystallization method, a method of manufacturing a thin-film transistor, and a method of manufacturing a display device are provided. The crystallization method includes: forming a backup amorphous silicon layer on a substrate, forming nickel particles on the backup amorphous silicon layer, converting the backup amorphous silicon layer into an amorphous silicon layer by thermally processing the backup amorphous silicon layer so as to diffuse the nickel particles throughout said backup amorphous silicon layer; and irradiating the amorphous silicon layer with energy from a laser.Type: GrantFiled: December 16, 2010Date of Patent: July 24, 2012Assignee: Samsung Mobile Display Co., Ltd.Inventors: Kwang-Hae Kim, Moo-Jin Kim
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Patent number: 8216863Abstract: A method of manufacturing field-emitter arrays by a molding technique includes uniformly controlling a shape of mold holes to obtain field emitter tips having diameters below 100 nm and blunted side edges. Repeated oxidation and etching of a mold substrate formed of single-crystal semiconductor mold wafers is carried out, wherein the mold holes for individual emitters are fabricated by utilizing the crystal orientation dependence of the etching rate.Type: GrantFiled: May 29, 2009Date of Patent: July 10, 2012Assignee: Paul Scherrer InsitutInventors: Eugenie Kirk, Soichiro Tsujino
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Publication number: 20120032303Abstract: The present invention relates to semiconductor technologies, and more particularly to a bipolar junction transistor (BJT) in a CMOS base technology and methods of forming the same. The BJT includes a semiconductor substrate having an emitter region, a base having a first contact, and a collector having a second contact and a well plug; a first silicide film on the first contact; a second silicide film on the second contact; a first silicide blocking layer on or over the semiconductor substrate between the first and second silicide films, and a second silicide blocking layer on the semiconductor substrate between the first silicide film and the emitter region.Type: ApplicationFiled: October 29, 2010Publication date: February 9, 2012Inventors: Badih ELKAREH, Kyu Ok LEE, Sang Yong LEE
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Patent number: 8063438Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.Type: GrantFiled: February 27, 2009Date of Patent: November 22, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Hoon Son, Jong-Wook Lee, Jong-Hyuk Kang
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Patent number: 8039333Abstract: A method of fabricating a semiconductor device according to one embodiment includes: forming a SiGe crystal layer on a semiconductor substrate, the SiGe crystal layer having a first plane and a second plane inclined with respect to the first plane; forming an amorphous Si film on the SiGe crystal layer; crystallizing a portion located adjacent to the first and second planes of the amorphous Si film by applying heat treatment using the first and second planes of the SiGe crystal layer as a seed, thereby forming a Si crystal layer; selectively removing or thinning a portion of the amorphous Si film that is not crystallized by the heat treatment; applying oxidation treatment to a surface of the Si crystal layer, thereby forming a gate insulating film on the surface of the Si crystal layer; and forming a gate electrode on the gate insulating film.Type: GrantFiled: January 26, 2009Date of Patent: October 18, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Akio Kaneko, Seiji Inumiya, Tomonori Aoyama, Takuya Kobayashi
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Patent number: 8003423Abstract: A method for manufacturing a poly-crystal silicon photovoltaic device using horizontal metal induced crystallization comprises the steps of forming at least one layer of an amorphous silicon thin film on a substrate, forming at least one groove of which depth is less than or equal to that of the thin film on the amorphous silicon thin film, and horizontally crystallizing the amorphous silicon thin film by forming a metal layer on an upper portion of the groove. Since a crystal shape and a growth direction of the photovoltaic device can be adjusted by the method, a poly-crystal silicon thin film for improving current flow can be formed at a low-temperature.Type: GrantFiled: January 9, 2008Date of Patent: August 23, 2011Assignee: LG Electronics Inc.Inventors: Jung-Heum Yun, Kwy-Ro Lee, Don-Hee Lee, Heon-Min Lee
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Patent number: 7829358Abstract: Embodiments of an LED disclosed has an emitter layer shaped to a controlled depth or height relative to a substrate of the LED to maximize the light output of the LED and to achieve a desired intensity distribution. In some embodiments, the exit face of the LED may be selected to conserve radiance. In some embodiments, shaping the entire LED, including the substrate and sidewalls, or shaping the substrate alone can extract 100% or approximately 100% of the light generated at the emitter layers from the emitter layers. In some embodiments, the total efficiency is at least 90% or above. In some embodiments, the emitter layer can be shaped by etching, mechanical shaping, or a combination of various shaping methods. In some embodiments, only a portion of the emitter layer is shaped to form the tiny emitters. The unshaped portion forms a continuous electrical connection for the LED.Type: GrantFiled: February 6, 2009Date of Patent: November 9, 2010Assignee: Illumitex, Inc.Inventors: Dung T. Duong, Paul N. Winberg, Matthew R. Thomas, Elliot M. Pickering, Muhammad Khizar
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Patent number: 7795703Abstract: According to one exemplary embodiment, a bipolar transistor includes an active area situated between first and second isolation regions in a substrate. The bipolar transistor further includes an epitaxial extension layer situated on the active area, where the epitaxial extension layer extends over the first and second isolation regions. The bipolar transistor further includes a base layer situated on the epitaxial extension layer, where the base layer includes an epitaxial base, and where the epitaxial base includes a usable emitter formation area. The active area has a first width and the usable emitter formation area has a second width, where the second width is at least as large as the first width.Type: GrantFiled: November 5, 2008Date of Patent: September 14, 2010Assignee: Newport Fab, LLCInventor: Greg D. U'Ren
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Patent number: 7781295Abstract: A system and method is disclosed for manufacturing a bipolar junction transistor that comprises an emitter/base layer that is formed by a single deposition process. In one advantageous embodiment of the invention the emitter/base layer comprises an emitter layer that comprises an epitaxially grown mono-silicon emitter. The epitaxially grown mono-silicon emitter significantly reduces the electrical resistivity of the emitter. A non-dopant impurity such as germanium is added to the base layer to endpoint a dry plasma etch process that is applied to etch the emitter/base layer.Type: GrantFiled: July 13, 2006Date of Patent: August 24, 2010Assignee: National Semiconductor CorporationInventors: Jamal Ramdani, Craig Printy, Steven J. Adler, Andre P. Labonte
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Patent number: 7741680Abstract: The present invention relates to a semiconductor device including a substrate layer, a metal-oxide-semiconductor field-effect transistor (MOSFET), a backgate region, an isolation layer and a diode. The MOSFET includes a gate region, a source region and a drain region. The source and drain regions are embedded in the backgate region, which includes a voltage input terminal. The isolation layer is located between the backgate region and the substrate layer and has a doping type opposite that of the backgate region. The diode includes a first terminal connected to the isolation layer and a second terminal coupled to an isolation voltage source.Type: GrantFiled: August 13, 2008Date of Patent: June 22, 2010Assignee: Analog Devices, Inc.Inventors: Haiyang Zhu, David Foley
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Patent number: 7678621Abstract: Disclosed are a crystallization pattern, and a method for crystallizing amorphous silicon. The method includes the steps of forming an amorphous silicon film on a glass substrate, forming a crystallization pattern by patterning the amorphous silicon film, and crystallizing the crystallization pattern into polycrystalline silicon by irradiating a laser onto the crystallization pattern. The crystallization pattern includes a peripheral region located within a first distance from an edge of the crystallization pattern, and an internal region located away from the edge of the crystallization pattern by more than the first distance. The internal region is divided into at least one sub-region, each sub-region includes one crystallization inducement pattern, and an edge of each sub-region is located within a second distance from the crystallization inducement pattern.Type: GrantFiled: March 16, 2007Date of Patent: March 16, 2010Assignee: Hydis Technologies, Co., LtdInventors: Myung Kwan Ryu, Eok Su Kim, Kyoung Seok Son, Jang Soon Im
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Patent number: 7618871Abstract: For the production of an improved bipolar transistor comprising a low-resistance base terminal, a dielectric layer is deposited over the semiconductor substrate and is highly doped via an implantation mask. In a subsequent controlled thermal step, the dopant is then indiffused into the semiconductor substrate from the dielectric layer serving as a dopant repository. This gives rise to a low-resistance region with which the extrinsic base can be defined carefully.Type: GrantFiled: January 19, 2005Date of Patent: November 17, 2009Assignee: Austriamicrosystems AGInventors: Gerald Meinhardt, Jochen Kraft
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Patent number: 7615455Abstract: A bipolar transistor having a base region resting by its lower surface on a collector region and surrounded with a first insulating layer, a base contact conductive region in contact with an external upper peripheral region of the base region, a second insulating region in contact with an intermediary upper peripheral region of the base region, an emitter region in contact with the central portion of the base region. The level of the central portion is higher than the level of the intermediary portion.Type: GrantFiled: September 19, 2006Date of Patent: November 10, 2009Assignee: STMicroelectronics S.A.Inventors: Pascal Chevalier, Alain Chantre
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Patent number: 7611954Abstract: A self-aligned bipolar transistor structure having a raised extrinsic base comprising an outer region and an inner region of different doping concentrations and methods of fabricating the transistor are disclosed. More specifically, the self-alignment of the extrinsic base to the emitter is accomplished by forming the extrinsic base in two regions. First, a first material of silicon or polysilicon having a first doping concentration is provided to form an outer extrinsic base region. Then a first opening is formed in the first material layer by lithography within which a dummy emitter pedestal is formed, which results in forming a trench between the sidewall of the first opening and the dummy pedestal. A second material of a second doping concentration is then provided inside the trench forming a distinct inner extrinsic base extension region to self-align the raised extrinsic base edge to the dummy pedestal edge.Type: GrantFiled: June 13, 2005Date of Patent: November 3, 2009Assignee: International Business Machines CorporationInventors: Gregory G. Freeman, Marwan H. Khater, Francois Pagette
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Patent number: 7557010Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.Type: GrantFiled: February 12, 2007Date of Patent: July 7, 2009Assignee: Agere Systems Inc.Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh
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Patent number: 7547914Abstract: The process relates to the production of a layer of a single-crystal first material on a second material. The second material has at least one aperture exposing a surface portion of a single-crystal third material. The process generally includes forming an at least partially crystalline first layer of said first material on said surface portion of the third material. Then, an amorphous or partially crystalline second layer of the first material is formed on the at least partially crystalline first layer of the first material and on one part of the second material that is around said aperture. Finally, the process includes recrystallization annealing of the first material. Thus, it is possible to produce, within one and the same wafer, either transistors on a germanium-on-insulator substrate with transistors on a silicon-on-insulator substrate, or transistors on a germanium-on-insulator substrate with transistors on a silicon substrate.Type: GrantFiled: January 16, 2007Date of Patent: June 16, 2009Assignee: STMicroelectronics (Crolles 2) SASInventors: Olivier Kermarec, Yves Campidelli, Guillaume Pin
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Patent number: 7491617Abstract: A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.Type: GrantFiled: June 18, 2007Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: David R. Greenberg, Shwu-Jen Jeng
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Patent number: 7378324Abstract: Bipolar transistors and methods of forming the bipolar transistors. The method including forming a P-type collector in a silicon substrate; forming an intrinsic base on the collector, the intrinsic base including a first N-type dopant species, germanium and carbon; forming an N-type extrinsic base over a first region and a second region of the intrinsic base, the first region over the collector and the second region over a dielectric adjacent to the collector, the N-type extrinsic base containing or not containing carbon; and forming a P-type emitter on the first region of the intrinsic base.Type: GrantFiled: March 30, 2006Date of Patent: May 27, 2008Assignee: International Business Machines CorporationInventors: Thomas N. Adam, Rajendran Krishnasamy
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Patent number: 7368361Abstract: A substrate has a collector region of a first conductivity type, and a base layer of a single crystalline structure and including impurities of a second conductivity type is located over the collector region. An emitter region is defined at least in part by impurities of the first conductivity type contained in the base layer. An emitter electrode of the first conductivity type contacts the emitter region, and at least a portion of the emitter electrode which is in contact with the emitter region has a single crystalline structure.Type: GrantFiled: June 29, 2006Date of Patent: May 6, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Kangwook Park
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Patent number: 7364990Abstract: First and second preliminary epitaxial layers are grown from single-crystalline seeds in openings in an insulation layer until the first and second epitaxial layers are connected to each other. While the first and second preliminary epitaxial layers are being grown, a connection structure of a material having an amorphous state is formed on a portion of the insulation layer located between the first and second preliminary epitaxial layers. The material having an amorphous state is then changed into material having a single-crystalline state. Thus, portions of the first and second epitaxial layers are connected to each other through the connection structure so that the epitaxial layers and the connection structure constitute a single-crystalline structure layer that is free of voids for use as a channel layer or the like of a semiconductor device.Type: GrantFiled: December 13, 2005Date of Patent: April 29, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Hoon Son, Yu-Gyun Shin, Jong-Wook Lee
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Patent number: 7348246Abstract: A semiconductor memory device includes a substrate having first and second source/drain regions therein and a channel region therebetween. The device also includes first and second charge storage layers on the channel region, a first insulating layer on the channel region between the first and second charge storage layers, and a gate electrode on the insulating layer opposite the channel region and between inner sidewalls of the first and second charge storage layers. The gate electrode extends away from the substrate beyond the first and second charge storage layers. The device further includes second and third insulating layers extending from adjacent the inner sidewalls of the first and second charge storage layers along portions of the gate electrode beyond the first and second charge storage layers. Related methods of fabrication are also discussed.Type: GrantFiled: November 7, 2005Date of Patent: March 25, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-min Kim, Dong-won Kim, Eun-jung Yun
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Patent number: 7341878Abstract: A material such as a phosphor is optically coupled to a semiconductor structure including a light emitting region disposed between an n-type region and a p-type region, in order to efficiently extract light from the light emitting region into the phosphor. The phosphor may be phosphor grains in direct contact with a surface of the semiconductor structure, or a ceramic phosphor bonded to the semiconductor structure, or to a thin nucleation structure on which the semiconductor structure may be grown. The phosphor is preferably highly absorbent and highly efficient. When the semiconductor structure emits light into such a highly efficient, highly absorbent phosphor, the phosphor may efficiently extract light from the structure, reducing the optical losses present in prior art devices.Type: GrantFiled: March 14, 2005Date of Patent: March 11, 2008Assignee: Philips Lumileds Lighting Company, LLCInventors: Michael R. Krames, Gerd O. Mueller
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Patent number: 7323390Abstract: The semiconductor device according to the invention includes a substrate, a field insulating region which delimits an active region of the semiconductor substrate, a collector, at least one collector contact region associated with the collector, and a base with an associated base connection region. The collector and the collector contact region are formed in the same active region. In addition the base connection region extends partially over the active region and is separated from the surface of the active region by an insulator layer.Type: GrantFiled: December 2, 2002Date of Patent: January 29, 2008Assignee: IHP GmbH - Innovations for High Performance Microelectronics/Institut fur innovative MikroelektronikInventors: Bernd Heinemann, Dieter Knoll, Karl-Ernst Ehwald, Holger Rücker
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Patent number: 7282418Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post situated on the top surface of the base. The bipolar transistor also comprises a conformal layer situated on a first and a second side of the sacrificial post, where the conformal layer is not separated from the first and second sides of the sacrificial post by spacers. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer, the sacrificial post, and the base. The sacrificial planarizing layer has a first thickness in a first region between the first and second sides of the sacrificial post and a second thickness in a second region outside of the first and second sides of the sacrificial post, where the second thickness is greater than the first thickness.Type: GrantFiled: September 28, 2004Date of Patent: October 16, 2007Assignee: Newport Fab, LLCInventors: Amol Kalburge, Kevin Q. Yin
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Patent number: 7265409Abstract: A non-volatile semiconductor memory having a memory transistor including a stacked-layer film formed between a semiconductor substrate and a gate electrode and having a charge storage ability, a first conductivity type region of the semiconductor substrate in which a channel is formed under the control of the gate electrode via the stacked-layer film, and two second conductivity type regions formed at the semiconductor substrate sandwiching the first conductivity type region therebetween, the memory transistor having a channel length L which is between channel lengths L1 and L2. with the channel length L1 being estimated as the boundary of occurrence of a short channel effect at the time of a write operation and the channel length L2 the time of a read operation, with the channel length L1 being different from the channel length L2.Type: GrantFiled: June 14, 2005Date of Patent: September 4, 2007Assignee: Sony CorporationInventors: Toshio Kobayashi, Hideto Tomiie