Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. The structure includes a vertical silicon-controlled rectifier (SCR) connecting to an anode, and includes a buried layer of a first dopant type in electrical contact with an underlying buried layer a second dopant type split with an isolation region of the first dopant type within a substrate.

Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.

Abstract: Techniques facilitating resistive random-access memory device with step height difference are provided. A resistive random-access memory device can comprise a first electrode located within a trench of a dielectric layer. The resistive random-access memory device can also comprise a metal oxide layer comprising a first section located within the trench of the dielectric layer, and a second section located over the first electrode, and over a barrier metal layer. Further, the resistive random-access memory device can comprise a second electrode located over the metal oxide layer.

Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.

Abstract: A semiconductor device that includes a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer includes a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of at least two suspended channel structures. The inner spacer may be composed of an n-type or p-type doped glass.

Abstract: A method of making a semiconductor switch device. The method includes providing a semiconductor substrate having a major surface and a first semiconductor region having a first conductivity type located adjacent the major surface. The method also includes depositing a gate dielectric on the major surface. The method further includes implanting ions into the first semiconductor region through a mask positioned over the first semiconductor region, thereby to form a well region located in the first semiconductor region. The well region has a second conductivity type different to the first conductivity type. The method also includes depositing and patterning a gate electrode material on the gate dielectric to form a gate electrode located directly above the well region. The method further includes implanting ions into the first semiconductor region to form a source region and a drain region of the semiconductor switch device on either side of the gate electrode.

Abstract: A semiconductor structure is provided in which gallium-doped sacrificial epitaxial or polycrystalline germanium layer is formed on a silicon germanium substrate having a high percentage of germanium followed by annealing to diffuse the gallium into the silicon germanium substrate. The germanium layer is selectively removed to expose the surface of a gallium-doped silicon germanium region within the silicon germanium substrate. The process has application to the formation of electrically conductive regions within integrated circuits such as source/drain regions and junctions without the introduction of carbon into such regions.

Abstract: A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device is disclosed. The BiCMOS device includes a CMOS device in a CMOS region, a PNP bipolar device in a bipolar region, and an NPN bipolar device in the bipolar region. The BiCMOS device includes also includes a silicon-germanium (SiGe) layer over a base of the PNP bipolar device and over a selectively implanted collector of the NPN bipolar device, wherein a first portion of the SiGe layer forms a base of the NPN bipolar device, and a second portion of the SiGe layer forms an emitter of the PNP bipolar device.

Abstract: A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device is disclosed. The BiCMOS device includes a CMOS device in a CMOS region, a PNP bipolar device in a bipolar region, and an NPN bipolar device in the bipolar region. The NPN bipolar device has an extrinsic base being self-aligned with an emitter of the NPN bipolar device. The extrinsic base of the NPN bipolar device and an emitter of the PNP bipolar device share a P type dopant.

Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a first source/drain disposed in contact with a substrate. A second source/drain is disposed above the first source/drain. At least one fin structure is disposed between and in contact with the first source/drain and the second source/drain. A width of the first source/drain and the second source/drain gradually decreases towards the fin structure. The method includes forming an oxide in contact with an exposed portion of at least one fin structure. During formation of the oxide, different areas of the exposed fin structure portion are oxidized at different rates. This forms a first region and a second region of the exposed fin structure portion. These regions each have a width that is greater than a width of a third region of the exposed fin structure portion situated between the first and second regions.

Abstract: A bipolar junction transistor comprises a semiconductor layer disposed on an insulating material, at least a portion of the semiconductor layer forming a base region. The bipolar junction transistor further comprises a transistor emitter laterally disposed on a first side of the base region, where in the transistor emitter is a first doping type and has a first width, and wherein the first width is a lithographic feature size. The bipolar junction transistor further comprises a transistor collector laterally disposed on a second side of the base region, wherein the transistor collector is the first doping type and the first width. The bipolar junction transistor further comprises a central base contact laterally disposed on the base region between the transistor emitter and the transistor collector, wherein the central base contact is a second doping type and has a second width, and wherein the second width is a sub-lithographic feature size.

Abstract: An element isolation trench is formed in a substrate and is formed along each side of a polygon in a planar view. A first trench is formed in the substrate and extends in a direction different from that of any side of the trench. A first-conductivity type region is formed on/over apart located on the side of an end of the first trench in the substrate. Accordingly, when an impurity region that extends in a depth direction in the substrate is formed by forming the trench in the substrate and diagonally implanting an impurity into the trench, the impurity is prevented from being implanted into a side face of a groove such as a groove for element isolation and so forth impurity implantation into the side face of which is not desired.

Abstract: A bipolar junction transistor comprises a semiconductor layer disposed on an insulating material, at least a portion of the semiconductor layer forming a base region. The bipolar junction transistor further comprises a transistor emitter laterally disposed on a first side of the base region, where in the transistor emitter is a first doping type and has a first width, and wherein the first width is a lithographic feature size. The bipolar junction transistor further comprises a transistor collector laterally disposed on a second side of the base region, wherein the transistor collector is the first doping type and the first width. The bipolar junction transistor further comprises a central base contact laterally disposed on the base region between the transistor emitter and the transistor collector, wherein the central base contact is a second doping type and has a second width, and wherein the second width is a sub-lithographic feature size.

Abstract: A semiconductor device includes a body including a first junction region; a pillar positioned over the body, and including a vertical channel region and a second junction region over the vertical channel region; a gate trench exposing side surfaces of the pillar; a gate dielectric layer covering the gate trench; and a gate electrode embedded in the gate trench, with the gate dielectric layer interposed therebetween. The gate electrode includes a first work function liner overlapping with the vertical channel region, and including an aluminum-containing metal nitride; a second work function liner overlapping with the second junction region, and including a silicon-containing non-metal material; and an air gap positioned between the second work function liner and the second junction region.

Abstract: A semiconductor device includes a PFET transistor (a PMOS FET) having a poly(silicon) layer with a p-type doped portion and an n-type doped portion. The p-type doped portion is located above a channel region of the transistor and the n-type doped portion is located in an end portion of the poly layer outside the channel region. The poly layer may be formed by doping portions of an amorphous silicon layer with either the p-type dopant or the n-type dopant and then annealing the amorphous silicon layer to diffuse the dopants and crystallize the amorphous silicon to form polysilicon. The n-type doped portion of the poly layer may provide an electrical shunt in the end portion of the poly layer to reduce any effects of insufficient diffusion of the p-type dopant in the poly layer.

Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.

Abstract: A method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer by growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers then carrying out a device manufacturing process on a top side of the epitaxial layer with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.

Abstract: A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.

Abstract: The invention discloses a vertical parasitic PNP transistor in a BiCMOS process and manufacturing method of the same, wherein an active region is isolated by STIs. The transistor includes a collector region, a base region, an emitter region, pseudo buried layers, and N-type polysilicon. The pseudo buried layers, formed at the bottom of the STIs located on both sides of the collector region, extend laterally into the active region and contact with the collector region, whose electrodes are picked up through making deep-hole contacts in the STIs. The N-type polysilicon is formed on the base region and contacts with it, whose electrodes are picked up through making metal contacts on the N-type polysilicon. The transistors can be used as output devices in high-speed and high-gain circuits, efficiently reducing the transistors area, diminishing the collector resistance, and improving the transistors performance. The method can reduce the cost without additional technological conditions.

Abstract: The present invention discloses a vertical SOI bipolar junction transistor and a manufacturing method thereof. The bipolar junction transistor includes an SOI substrate from down to up including a body region, a buried oxide layer and a top silicon film; an active region located in the top silicon film formed by STI process; a collector region located in the active region deep close to the buried oxide layer formed by ion implantation; a base region located in the active region deep close to the top silicon film formed by ion implantation; an emitter and a base electrode both located over the base region; a side-wall spacer located around the emitter and the base electrode. The present invention utilizing a simple double poly silicon technology not only can improve the performance of the transistor, but also can reduce the area of the active region in order to increase the integration density.

Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.

Abstract: The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.

Abstract: A semiconductor device includes a first insulating film formed between a gate electrode and a first flat semiconductor layer, and a sidewall-shaped second insulating film formed to surround an upper sidewall of a first columnar silicon layer while contacting an upper surface of the gate electrode and to surround a sidewall of the gate electrode and the first insulating film. The semiconductor device further includes a metal-semiconductor compound formed on each of an upper surface of a first semiconductor layer of the second conductive type formed in the entirety or the upper portion of the first flat semiconductor layer, and an upper surface of the second semiconductor layer of the second conductive type formed in the upper portion of the first columnar semiconductor layer.

Abstract: Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated pocket and filled with a dielectric material while the dielectric material is deposited so as to line the walls and floor of the first trench. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.

Abstract: Bipolar junction transistors are provided in which at least one of an emitter contact, a base contact, or a collector contact thereof is formed by epitaxially growing a doped SixGe1-x layer, wherein x is 0?x?1, at a temperature of less than 500° C. The doped SixGe1-x layer comprises crystalline portions located on exposed surfaces of a crystalline semiconductor substrate and non-crystalline portions that are located on exposed surfaces of a passivation layer which can be formed and patterned on the crystalline semiconductor substrate. The doped SixGe1-x layer of the present disclosure, including the non-crystalline and crystalline portions, contains from 5 atomic percent to 40 atomic percent hydrogen.

Abstract: Vertical bipolar junction structures, methods of manufacture and design structures. The method includes forming one or more sacrificial structures for a bipolar junction transistor (BJT) in a first region of a chip. The method includes forming a mask over the one or more sacrificial structures. The method further includes etching an opening in the mask, aligned with the one or more sacrificial structures. The method includes forming a trench through the opening and extending into diffusion regions below the one or more sacrificial structures. The method includes forming a base region of the BJT by depositing an epitaxial material in the trench, in contact with the diffusion regions. The method includes forming an emitter contact by depositing a second epitaxial material on the base region within the trench. The epitaxial material for the emitter region is of an opposite dopant type than the epitaxial material of the base region.

Abstract: In conventional processes, a recombination rate of minority carrier accumulated between a diffusion layer of an anode and a diffusion layer of a cathode cannot be enhanced. An interlayer insulating film 20 is formed on a semiconductor substrate 10. An opening 22 (first opening), an opening 24 (second opening) and an opening 26 are formed in the interlayer insulating film 20. The opening 22 and the opening 26 are formed above respective the p-type diffusion layer 16 and the n-type diffusion layer 18. The opening 24 is formed above the gap region that is a region between the p-type diffusion layer 16 and the n-type diffusion layer 18. A contact plug 32, a contact plug 34 and a contact plug 36 are embedded in the opening 22, the opening 24 and the opening 26 respectively. Both regions of the semiconductor substrate 10 located under the opening 22 among and located under the opening 24 are doped with an impurity.

Abstract: According to one embodiment, a method is disclosed for manufacturing a nonvolatile memory device. The nonvolatile memory device includes a memory cell connected to a first interconnect and a second interconnect. The method can include forming a first electrode film on the first interconnect. The method can include forming a layer including a plurality of carbon nanotubes dispersed inside an insulator on the first electrode film. At least one carbon nanotube of the plurality of carbon nanotubes is exposed from a surface of the insulator. The method can include forming a second electrode film on the layer. In addition, the method can include forming a second interconnect on the second electrode film.

Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.

Abstract: A process for forming contacts to a field effect transistor provides edge relaxation of a buried stressor layer, inducing strain in an initially relaxed surface semiconductor layer above the buried stressor layer. A process can start with a silicon or silicon-on-insulator substrate with a buried silicon germanium layer having an appropriate thickness and germanium concentration. Other stressor materials can be used. Trenches are etched through a pre-metal dielectric to the contacts of the FET. Etching extends further into the substrate, through the surface silicon layer, through the silicon germanium layer and into the substrate below the silicon germanium layer. The further etch is performed to a depth to allow for sufficient edge relaxation to induce a desired level of longitudinal strain to the surface layer of the FET. Subsequent processing forms contacts extending through the pre-metal dielectric and at least partially into the trenches within the substrate.

Abstract: In an embodiment, a bipolar transistor structure is formed on a silicon-on-insulator (SOI) structure that includes a semiconductor substrate, a buried oxide layer formed on the semiconductor substrate and a top silicon layer formed on the buried oxide layer.

Abstract: A semiconductor memory device includes a semiconductor substrate, a semiconductor pillar extending from the semiconductor substrate, the semiconductor pillar comprising a first region, a second region, and a third region, the second region positioned between the first region and the third region, the third region positioned between the second region and the semiconductor substrate, immediately adjacent regions having different conductivity types, a first gate pattern disposed on the second region with a first insulating layer therebetween, and a second gate pattern disposed on the third region, wherein the second region is ohmically connected to the substrate by the second gate pattern.

Abstract: A method for forming a shielded gate trench field effect transistor (FET) includes forming trenches in a semiconductor region, forming a shield electrode in a bottom portion of each trench, and forming an inter-electrode dielectric (IED) extending over the shield electrode. The IED may comprise a low-k dielectric. The method also includes forming a gate electrode in an upper portion of each trench over the IED.

Abstract: A dynamic random access memory cell having vertical channel transistor includes a semiconductor pillar, a drain layer, an assisted gate, a control gate, a source layer, and a capacitor. The vertical channel transistor has an active region formed by the semiconductor pillar. The drain layer is formed at the bottom of the semiconductor pillar. The assisted gate is formed beside the drain layer, and separated from the drain layer by a first gate dielectric layer. The control gate is formed beside the semiconductor pillar, and separated from the active region by a second gate dielectric layer. The source layer is formed at the top of the semiconductor pillar. The capacitor is formed to electrical connect to the source layer.

Abstract: The invention discloses a vertical parasitic PNP transistor in a BiCMOS process and manufacturing method of the same, wherein an active region is isolated by STIs. The transistor includes a collector region, a base region, an emitter region, pseudo buried layers, and N-type polysilicon. The pseudo buried layers, formed at the bottom of the STIs located on both sides of the collector region, extend laterally into the active region and contact with the collector region, whose electrodes are picked up through making deep-hole contacts in the STIs. The N-type polysilicon is formed on the base region and contacts with it, whose electrodes are picked up through making metal contacts on the N-type polysilicon. The transistors can be used as output devices in high-speed and high-gain circuits, efficiently reducing the transistors area, diminishing the collector resistance, and improving the transistors performance. The method can reduce the cost without additional technological conditions.

Abstract: A semiconductor device and methods for its fabrication are provided. The semiconductor device comprises a trench formed in the semiconductor substrate and bounded by a trench wall extending from the semiconductor surface to a trench bottom. A drain region and a source region, spaced apart along the length of the trench, are formed along the trench wall, each extending from the surface toward the bottom. A channel region is formed in the substrate along the trench wall between the drain region and the source region and extending along the length of the trench parallel to the substrate surface. A gate insulator and a gate electrode are formed overlying the channel.

Abstract: A semiconductor structure includes a semiconductor substrate; an n-type tub extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the n-type tub comprises a bottom buried in the semiconductor substrate; a p-type buried layer (PBL) on a bottom of the tub, wherein the p-type buried layer is buried in the semiconductor substrate; and a high-voltage n-type metal-oxide-semiconductor (HVNMOS) device over the PBL and within a region encircled by sides of the n-type tub.

Abstract: Methods for manufacturing trench type semiconductor devices containing thermally unstable refill materials are provided. A disposable material is used to fill the trenches and is subsequently replaced by a thermally sensitive refill material after the high temperature processes are performed. Trench type semiconductor devices manufactured according to method embodiments are also provided.

Abstract: The present invention provides a semiconductor device (20) comprising a trench (5) formed in a semiconductor substrate formed of a stack (4) of layers (1,2,3), a layer (6) of a first, grown dielectric material covering sidewalls and bottom of the trench (5), the layer (6) including one or more notches (13) at the bottom of the trench (5) and one or more spacers (14) formed of a second, deposited dielectric material to fill the one or more notches (13) in the layer (6) formed of the first, grown dielectric material. The semiconductor device (20) according to the present invention shows improved breakdown voltage and on-resistance. The present invention furthermore provides a method for the manufacturing of such semiconductor devices (20).

Abstract: A MOSFET-type semiconductor device includes a monocrystalline semiconductor layer formed in a shape of a thin wall on a insulating film, a gate electrode straddling over the semiconductor layer around the middle portion of the wall-shaped semiconductor layer via a gate insulating film, source and drain regions formed at the both ends of the semiconductor layer, a first metal-semiconductor compound layer formed on one of the side walls of each of source and drain regions of the semiconductor layer, and a second metal-semiconductor compound layer having a different composition and Schottky barrier height from that of the first metal-semiconductor compound layer on the other side wall of each of source and drain regions of the semiconductor layer.

Abstract: A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.

Abstract: In the fabrication of an integrated circuit, a shallow trench for isolation of a vertical bipolar transistor comprised in the circuit is fabricated by providing a semiconductor substrate of a first doping type. A buried collector region of a second doping type for the bipolar transistor is formed in the substrate. A silicon layer is epitaxially grown on top of the substrate. An active region of the second doping type for the bipolar transistor is formed in the epitaxially grown silicon layer, the active region being located above the buried collector region. A first trench is formed in the epitaxially grown silicon layer and the silicon substrate, the first trench surrounding, in a horizontal plane, the active region and extending vertically a distance into the substrate. An electrically insulating material is formed in the first trench.

Abstract: A method for manufacturing a vertical MOS transistor comprising forming a protrusion-like region, forming a silicon oxide film on an exposed surface of the protrusion-like region and a surface of the silicon semiconductor substrate, increasing a film thickness of at least the silicon oxide film on the silicon semiconductor substrate by thermal oxidation to form a first insulating film, forming a lower impurity diffusion region, removing the silicon oxide film to expose a silicon side of the protrusion-like region, thermally oxidizing the silicon side to form a second insulating film having a thinner film thickness than a film thickness of the first insulating film, forming a gate electrode over a side of the protrusion-like region, and forming an upper impurity diffusion region.

Abstract: In a semiconductor device including a bipolar transistor, a base region has a two layer structure including a first base region, and a second base region which is provided around the first base region and has a lower impurity density than that of the first base region and has a shallower depth than that of the first base region.

Abstract: An integrated circuit having a substrate with a first conductivity type of semiconductor material. A buried layer is formed in the substrate. The buried layer has a second conductivity type of semiconductor material. A first semiconductor layer is formed over the buried layer. The first semiconductor layer has the second conductivity type of semiconductor material. A trench is formed through the first semiconductor layer and buried layer and extends into the substrate. The trench is lined with an insulating layer and filled with an insulating material. A second semiconductor layer is formed in the first semiconductor layer. The second semiconductor layer has the first conductivity type of semiconductor material. A third semiconductor layer is formed in the second semiconductor layer. The third semiconductor layer has the second conductivity type of semiconductor material. The first, second, and third semiconductor layers form the collector, base, and emitter of a bipolar transistor.

Abstract: A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over the base electrode; (d) forming a first spacer adjacent to the oxide nitride structure and the base electrode; (e) removing a top layer of the oxide nitride structure; (f) removing a first portion of the dielectric layer; (g) forming an epitaxial layer over the semiconductor substrate; (h) forming a second spacer over the epitaxial layer; and (i) forming an emitter electrode over the epitaxial layer and adjacent to the second spacer.

Abstract: High frequency performance of (e.g., silicon) bipolar devices (100, 100?) is improved by reducing the extrinsic base resistance Rbx. Emitter (160), base (161) and collector (190) are formed in or on a semiconductor substrate (110). The emitter contact (154) has a portion (154?) that overhangs a portion (1293, 293?) of the extrinsic base contact (129), thereby forming a cave-like cavity (181, 181?) between the overhanging portion (154?) of the emitter contact (154) and the underlying regions (1293, 1293?) of the extrinsic base contact (129). When the emitter contact and the extrinsic base contact are silicided, some of the metal atoms forming the silicide penetrate into the cavity (181, 181?) so that the highly conductive silicided extrinsic base contact extends under the edge of the emitter contact (154?) closer to the base (161, 163) itself, thereby reducing Rbx. Smaller Rbx provides transistors with higher fMAX.

Abstract: In a semiconductor device of the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. In the substrate and the epitaxial layer, an N type buried diffusion layer is formed on a P type buried diffusion layer. With this structure, an upward expansion of the P type buried diffusion layer is checked and a thickness of the epitaxial layer can be made small while maintaining the breakdown voltage characteristics of a power semiconductor element. Accordingly, a device size of a control semiconductor element can be reduced.

Abstract: The invention relates to a semiconductor structure for controlling a current (I), comprising a first n-conductive semiconductor region (2), a current path that runs within the first semiconductor region (2) and a channel region (22). The channel region (22) forms part of the first semiconductor region (2) and comprises a base doping. The current (I) in the channel region (22) can be influenced by means of at least one depletion zone (23, 24). The channel region (22) contains an n-conductive channel region (225) for conducting the current, said latter region having a higher level of doping than the base doping. The conductive channel region (225) is produced by ionic implantation in an epitaxial layer (262) that surrounds the channel region (22).

Abstract: An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of diffusion of the P type buried layer dopant is greater than the N type buried layer dopant so that connections can be made to the P type buried layer by P wells which have a lower dopant concentration than the N buried layer.