Abstract: Methods, systems, circuits, and devices for power-packet-switching power converters using bidirectional bipolar transistors (BTRANs) for switching. Four-terminal three-layer BTRANs provide substantially identical operation in either direction with forward voltages of less than a diode drop. BTRANs are fully symmetric merged double-base bidirectional bipolar opposite-faced devices which operate under conditions of high non-equilibrium carrier concentration, and which can have surprising synergies when used as bidirectional switches for power-packet-switching power converters. BTRANs are driven into a state of high carrier concentration, making the on-state voltage drop very low.

Abstract: Methods, systems, circuits, and devices for power-packet-switching power converters using bidirectional bipolar transistors (BTRANs) for switching. Four-terminal three-layer BTRANs provide substantially identical operation in either direction with forward voltages of less than a diode drop. BTRANs are fully symmetric merged double-base bidirectional bipolar opposite-faced devices which operate under conditions of high non-equilibrium carrier concentration, and which can have surprising synergies when used as bidirectional switches for power-packet-switching power converters. BTRANs are driven into a state of high carrier concentration, making the on-state voltage drop very low.

Abstract: A method of forming an integrated circuit is disclosed. A second material layer is formed on a first material layer. A patterned mask layer having a plurality of first features with a first pitch P1 is formed on the second material layer. The second material layer is etched by using the patterned mask layer as a mask to form the first features in the second material layer. The patterned mask layer is trimmed. A plurality of dopants is introduced into the second material layer not covered by the trimmed patterned mask layer. The trimmed patterned mask layer is removed to expose un-doped second material layer. The un-doped second material layer is selectively removed to form a plurality of second features with a second pitch P2. P2 is smaller than P1.

Abstract: A semiconductor device includes a body region of a first conductivity type and a gate pattern disposed on the body region. The gate pattern has a linear portion extending in a first direction and having a uniform width and a bending portion extending from one end of the linear portion. The portion of a channel region located beneath the bending portion constitutes a channel whose length is greater than the length of the channel constituted by the portion of the channel region located beneath the linear portion.

Abstract: In one embodiment, a power transistor device comprises a substrate that forms a PN junction with an overlying buffer layer. The power transistor device further includes a first region, a drift region that adjoins a top surface of the buffer layer, and a body region. The body region separates the first region from the drift region. First and second dielectric regions respectively adjoin opposing lateral sidewall portions of the drift region. The dielectric regions extend in a vertical direction from at least just beneath the body region down at least into the buffer layer. First and second field plates are respectively disposed in the first and second dielectric regions. A trench gate that controls forward conduction is disposed above the dielectric region adjacent to and insulated from the body region.

Abstract: A switching element according to the present invention includes an ion-conducting layer, first electrode 11 and second electrode 12 placed in contact with the ion-conducting layer, and third electrode 15 placed in contact with the ion-conducting layer and to control electrical conductivity between the first electrode and the second electrode, wherein the shortest distance between any two of first, second, and third electrodes 11, 12, and 13 is defined by the film thickness of the ion-conducting layer.

Abstract: A method of fabricating a semiconductor device according to one embodiment includes: laying out a first region, a second region, a third region and a fourth region on a semiconductor substrate by forming an element isolation region in the semiconductor substrate; forming a first insulating film on the first region and the second region; forming a first semiconductor film on the first insulating film; forming a second insulating film and an aluminum oxide film thereon on the fourth region after forming of the first semiconductor film; forming a third insulating film and a lanthanum oxide film thereon on the third region after forming of the first semiconductor film; forming a high dielectric constant film on the aluminum oxide film and the lanthanum oxide film; forming a metal film on the high dielectric constant film; forming a second semiconductor film on the first semiconductor film and the metal film; and patterning the first insulating film, the first semiconductor film, the second insulating film, the al

Abstract: A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features.

Abstract: In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.

Abstract: A method of recycling monitor wafers. The method includes: (a) providing a semiconductor wafer which includes a dopant layer extending from a top surface of the wafer into the wafer a distance less than a thickness of the wafer, the dopant layer containing dopant species; after (a), (b) attaching an adhesive tape to a bottom surface of the wafer; after (b), (c) removing the dopant layer; and after (c), (d) removing the adhesive tape.

Abstract: A power semiconductor device that includes a plurality of gate structure each having a gate insulation of a first thickness, and a termination region, the termination including a field insulation body surrounding the active region and having a recess that includes a bottom insulation thicker than the first thickness.

Abstract: A dynamic mask module is disclosed, which comprises a microcomputer system, a mask pattern generator and a light source. The mask pattern generator is disposed over a substrate and electrically connected to the microcomputer system. The microcomputer system transmits an image signal to the mask pattern generator. The light source is disposed over the mask pattern generator to a photo-resist layer on the substrate. The mask pattern generated by the dynamic mask module is a dynamic image and the mask pattern can be changed on anytime. In addition, the manufacturing cost can be and the manufacturing time can be reduced.

Abstract: In accordance with one embodiment of the present invention, a power semiconductor device includes a first drift region of a first conductivity type extending over a semiconductor substrate. The first drift region has a lower impurity concentration than the semiconductor substrate. A second drift region of the first conductivity type extends over the first drift region, and has a higher impurity concentration than the first drift region. A plurality of stripe-shaped body regions of a second conductivity type are formed in an upper portion of the second drift region. A third region of the first conductivity type is formed in an upper portion of each body region so as to form a channel region in each body region between the third region and the second drift region. A gate electrode laterally extends over but is insulated from: (i) the channel region in each body region, (ii) a surface area of the second drift region between adjacent stripes of body regions, and (iii) a surface portion of each source region.

Abstract: A semiconductor device composed of III-nitride materials is produced with epitaxial growth that permits vertical and lateral growth geometries to improve device characteristics. The resulting device has a greater breakdown voltage due to the greater integrity of the semiconductor material structure since no ion implantation processes are used. The epitaxially grown layers also exhibit greater thermal conductivity for improved operation with power semiconductor devices. The device may include a laterally grown charge compensated area to form a superjunction device. The resulting device may be bidirectional and have improved breakdown voltage in addition to higher current capacity for a given voltage rating.