Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.

Abstract: A manufacturing method of a semiconductor structure includes: providing a base; forming multiple bit line structures on the base, where the multiple bit line structures are parallel to each other and extend in a first direction, and a trench is formed between adjacent bit line structures; forming a first conductive layer in the trench, where a void is formed in the first conductive layer; removing a part of the first conductive layer to form a first groove, where the bottom of the first groove exposes the void; forming an epitaxial layer on an inner wall of the first groove; and allowing the epitaxial layer to epitaxially grow to form an extension portion, such that the extension portion fills the void.

Abstract: In an aspect, a process of forming an electronic device can include patterning a substrate to define a trench having a sidewall and forming a first semiconductor layer within the trench and along the sidewall. In an embodiment, the process can further include forming a barrier layer within the trench after forming the first semiconductor layer; forming a second semiconductor layer within the trench after forming the barrier layer, wherein within the trench, first and second portions of the second semiconductor layer contact each other adjacent to a vertical centerline of the trench; and exposing the second semiconductor layer to radiation sufficient to allow a void within second semiconductor layer to migrate toward the barrier layer. In another embodiment, after forming a semiconductor within the trench, the process can further include forming an insulating layer that substantially fills a remaining portion of the trench.

Abstract: Embodiments provide a method for fabricating a memory and a memory. This method includes: providing a substrate, the substrate being internally provided with a plurality of active areas, and each of the plurality of active areas including a first contact region and a second contact region; forming a plurality of bit lines on the substrate, each of the plurality of bit lines being connected to at least one of the first contact regions; forming an isolation layer on each of the plurality of bit lines, the isolation layer covering each of the plurality of bit lines and the substrate, the isolation layer being further provided with a plurality of filling holes corresponding to the plurality of second contact regions one to one; etching the isolation layer and the substrate along the plurality of filling holes, to fill in the plurality of second contact regions.

Abstract: A manufacturing method of a through substrate via includes at least the following steps. A protective liner is formed within an opening of a dielectric layer, where the opening exposes a portion of a semiconductor substrate underlying the dielectric layer. The portion of the semiconductor substrate is removed through the opening, where an overhang portion is formed at a top edge of the semiconductor substrate and masked by the protective liner after the removing. The overhang portion of the semiconductor substrate, the protective liner, and a portion of the dielectric layer adjoining the protective liner is removed to form a via hole. A conductive material is formed in the via hole.

Abstract: A capacitor structure, a method for manufacturing a capacitor structure and a method for operating a capacitor structure are provided. The capacitor structure includes a first electrode and a second electrode; a dielectric layer between the first electrode and the second electrode; and an oxygen donor layer between the dielectric layer and the first electrode. An oxygen concentration of the oxygen donor layer increases along a thickness direction from a first surface proximal to the dielectric layer to a second surface proximal to the first electrode.

Abstract: In one embodiment a semiconductor structure comprises a semiconductor substrate, a trench dielectric layer disposed in a trench of the semiconductor substrate, a first source/drain region disposed in contact with the semiconductor substrate, a gate and a second source/drain region. The gate is disposed between the first source/drain region and the second source/drain region. The semiconductor structure further comprises a dielectric isolation layer disposed between the semiconductor substrate and the second source/drain region.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first image sensing element and a second image sensing element arranged over a substrate. A first micro-lens is arranged over the first image sensing element, and a second micro-lens is arranged over the second image sensing element. A composite deep trench isolation structure is arranged between the first and second image sensing elements. The composite deep trench isolation structure includes a lower portion arranged over the substrate and an upper portion arranged over the lower portion. The lower portion includes a first material, and the upper portion includes a second material that has a higher reflectivity than the first material.

Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.

Abstract: A semiconductor device includes an integrated trench capacitor in a substrate, with a field oxide layer on the substrate. The trench capacitor includes trenches extending into semiconductor material of the substrate, and a capacitor dielectric in the trenches on the semiconductor material. The trench capacitor further includes an electrically conductive trench-fill material on the capacitor dielectric. A portion of the capacitor dielectric extends into the field oxide layer, between a first segment of the field oxide layer over the trench-fill material and a second segment of the field oxide layer over the semiconductor material. The integrated trench capacitor has a trench contact to the trench-fill material in each of the trenches, and substrate contacts to the semiconductor material around the trenches, with no substrate contacts between the trenches.

Abstract: A multilayer capacitive element and a design method of the same are provided. The capacitive element includes a substrate having a groove, a first aspect ratio modulation structure, and a plurality of conductive layers and a plurality of dielectric layers. The first aspect ratio modulation structure is located in the groove to define the groove as a first region and a first modulation region, wherein an aspect ratio of the first modulation region is different from that of the first region. The plurality of conductive layers and the plurality of dielectric layers are alternately stacked in the groove.

Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

Abstract: An integrated circuit device includes: a substrate including active regions; a device isolation film defining the active regions; a word line arranged over the active regions and the device isolation film and extending in a first horizontal direction; and a gate dielectric film arranged between the substrate and the word line and between the device isolation film and the word line, in which, in a second horizontal direction orthogonal to the first horizontal direction, a width of a second portion of the word line over the device isolation film is greater than a width of a first portion of the word line over the active regions. To manufacture the integrated circuit device, an impurity region is formed in the substrate and the device isolation film by implanting dopant ions into the substrate and the device isolation film, and a thickness of a portion of the impurity region is reduced.

Abstract: A method used in forming an array of capacitors comprises forming an array of vertically-elongated first capacitor electrodes that project vertically relative to an outer surface. An insulative ring is formed circumferentially about individual vertically-projecting portions of the first capacitor electrodes. The insulative rings about immediately-adjacent of the first capacitor electrodes in a first straight-line direction are laterally directly against one another. The insulative rings about immediately-adjacent of the first capacitor electrodes in a second straight-line direction that is angled relative to the first straight-line direction are laterally-spaced from one another. A capacitor insulator is formed over sidewalls of the first capacitor electrodes. At least one second capacitor electrode is formed over the capacitor insulator. Additional methods, including structure independent of method, are disclosed.

Abstract: A memory device is disclosed, in which node contacts extend into a substrate, where they are come into electrical connection with active areas. This allows greater contact areas between the node contacts and the active areas and electrical connection of the node contacts with high ion concentration portions of the active areas. As a result, even when voids are formed in the node contacts, the node contacts can still possess desired connection performance. For node contacts allowed to contain voids, this enables them to be fabricated faster with lower difficulty, thus increasing manufacturing throughput of the memory device.

Abstract: The present disclosure provides a semiconductor device and a preparation method thereof. The semiconductor device includes a semiconductor substrate, a semiconductor fin and a filled trench. The semiconductor fin extends upwards from the semiconductor substrate. The filled trench is formed in the semiconductor fin and includes a first sigma portion, a second sigma portion and a middle portion. The first sigma portion is partially filled by a semiconductor buffer region, and an unfilled part of the first sigma portion is filled by a doped semiconductor region grown on the semiconductor buffer region. The second sigma portion is filled by the semiconductor buffer region. The middle portion connects the first sigma portion to the second sigma portion, and the middle portion is filled by the semiconductor buffer region.

Abstract: There is provided a technique that includes (a) forming a film containing silicon, carbon and nitrogen having a carbon concentration within a range from 10 at % to 15 at % on a substrate; (b) performing an oxidation process with respect to the substrate where the film is exposed on a surface thereof; and (c) performing a process using hydrogen fluoride with respect to the substrate where the film is exposed on the surface thereof after the oxidation process is performed.

Abstract: A semiconductor device includes: a plurality of lower electrodes arranged on a substrate in a first direction, which is parallel to a main surface of the substrate, and a second direction parallel to the main surface of the substrate and perpendicular to the first direction; and a support structure pattern configured to connect the plurality of lower electrodes to each other to support the plurality of lower electrodes, on the substrate and including a plurality of open portions. The plurality of open portions have shapes extending longer in the second direction than in the first direction, and when viewed from inner sides of the plurality of open portions, the plurality of open portions are convex in the first direction and are concave in the second direction.

Abstract: A modified 1C1T cell detects when the charge in the memory cell drops below a predetermined voltage due to leakage and asserts a refresh signal indicating that refresh needs to be performed on those memory cells associated with the modified 1C1T memory cell. The associated memory cells may be a row, a bank, or other groupings of memory cells. Because temperature affects leakage current, the modified memory cell automatically adjusts for temperature.

Abstract: A semiconductor structure includes a dielectric layer having a trench formed therein and a barrier layer formed on a bottom and sidewalls of the trench, and on a top surface of the dielectric layer. The trench comprises a flared top gap opening and additional area at the bottom such that the top and bottom of the trench are wider than sidewalls of the trench. A thickness of the barrier layer on the bottom of the trench and on the top surface of the dielectric layer is controlled using one or more cycles comprising forming an oxidized layer using a neutral beam oxidation and removing the oxidized layer using an etching process, such that the thickness of the barrier layer on the bottom of the trench and on the top surface of the dielectric layer is substantially the same as the thickness of the barrier layer on sidewalls of the trench.

Abstract: A semiconductor device can include a plurality of landing pads arranged according to a layout on a substrate, wherein a cross-sectional shape of each of the landing pads has a diamond shape so that opposing interior angles of the diamond shape are equal to one another and adjacent interior angles of the diamond shape are unequal to one another.

Abstract: An arrangement for making electrical contact to a vertical capacitor having top and bottom metal layers separated by a dielectric, and at least one trench. Recesses are formed in an oxide layer over the capacitor to provide access to the top and bottom metal layers. The recesses include contacting portions preferably positioned such that there is no overlap between them and any of the trenches. Metal in the recesses, preferably copper, forms electrical contacts to the vertical capacitor's metal layers and enables reliable bonding to copper metallization on other layers such as an ROIC layer. ‘Dummy’ capacitors may be tiled on portions of the IC where there are no vertical capacitors, preferably with the top surfaces of their top metal at a height approximately equal to that of the top surface of the vertical capacitor's top metal, thereby enabling the IC to be planarized with a uniform planarization thickness.

Abstract: A method of semiconductor device fabrication includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer is formed over the first and second fin elements, where the first layer includes a gap. A laser anneal process is performed to the substrate to remove the gap in the first layer. An energy applied to the first layer during the laser anneal process is adjusted based on a height of the first layer.

Abstract: A method for performing a high aspect ratio etch is provided. A semiconductor substrate is provided with a hard mask layer arranged over the semiconductor substrate. A first etch is performed into the hard mask layer to form a hard mask opening exposing the semiconductor substrate. The hard mask opening has a bottom width. A second etch is performed into the semiconductor substrate, through the hard mask opening, to form a substrate opening with a top width that is about equal to the bottom width of the hard mask opening. A protective layer is formed lining a sidewall of the substrate opening. A third etch is performed into the semiconductor substrate, through the hard mask opening, to increase a height of the substrate opening. The top width of the substrate opening remains substantially unchanged during the third etch. A semiconductor structure with a high aspect ratio opening is also provided.

Abstract: The present disclosure provides a method of forming a capacitor structure and a capacitor structure. A semiconductor-on-insulator substrate is provided comprising a semiconductor layer, a buried insulating material layer and a semiconductor substrate material. A shallow trench isolation structure defining a first active region on the SOI substrate is formed, the first active region having a plurality of trenches formed therein. Within each trench, the semiconductor substrate material is exposed on inner sidewalls and a bottom face. A layer of insulating material covering the exposed semiconductor substrate material is formed, and an electrode material is deposited on the layer of insulating material in the first active region.

Abstract: A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.

Abstract: There is provided a method of filling a recess of a workpiece, which includes: forming a first thin film made of a semiconductor material along a wall surface defining a recess in a semiconductor substrate; annealing the workpiece within a vessel whose internal process is set to a first pressure, and forming an epitaxial region which is generated by crystallizing the semiconductor material of the first thin film, along a surface defining the recess, without moving the first thin film; forming a second thin film made of the semiconductor material along the wall surface defining the recess; and annealing the workpiece within the vessel whose internal pressure is set to a second pressure lower than the first pressure, and forming a further epitaxial region which is generated by crystallizing the semiconductor material of the second thin film which is moved toward a bottom of the recess.

Abstract: In some embodiments, silicon-filled openings are formed having no or a low occurrence of voids in the silicon fill, while maintaining a smooth exposed silicon surface. In some embodiments, an opening in a substrate may be filled with silicon, such as amorphous silicon. The deposited silicon may have interior voids. This deposited silicon is then exposed to a silicon mobility inhibitor, such as an oxygen-containing species and/or a semiconductor dopant. The deposited silicon fill is subsequently annealed. After the anneal, the voids may be reduced in size and, in some embodiments, this reduction in size may occur to such an extent that the voids are eliminated.

Abstract: Embodiments of the present invention provide a structure and method for fabrication of deep trenches in semiconductor-on-insulator structures. An upper portion of the deep trench cavity is formed to expose a sidewall of the buried insulator layer. A protective layer is disposed on the sidewall of the buried insulator layer. Then, the cavity is extended into the bulk substrate. The protective layer prevents over etch of the buried insulator layer during this process. The protective layer is then partially removed, such that the semiconductor-on-insulator (SOI) layer sidewall is exposed. The trench is then filled with a conductive fill material, such as polysilicon. The protection of the buried insulator (BOX) layer allows the trenches to be placed closer together while reducing the risk of a short circuit due to over etch, thereby increasing circuit density and product yield.

Abstract: An access device includes a plurality of first digit lines (DL) trenches extending along a first direction, buried digit lines between each DL trench, second and third trenches separating the digit lines, a filling material filling the digit line trenches comprising airgaps in each second trench, a plurality of word line (WL) trenches extending along a second direction, metal word lines deposited on the walls of the word line trenches, a filling material filling the word line trenches.

Abstract: Back end of the line (BEOL) capacitors and methods of manufacture are provided. The method includes forming wiring lines on a substrate, with spacing between adjacent wiring lines. The method further includes forming an air gap within spacing between the adjacent wiring lines by deposition of a capping material. The method further includes opening the air gap between selected adjacent wiring lines. The method further includes depositing conductive material within the opened air gap.

Abstract: At least one method, apparatus and system disclosed herein for forming an integrated circuit having a dual-orientation self aligned via. A first dielectric layer is formed on a semiconductor substrate. At least one first metal feature is formed in a first metal layer. A first cap feature is deposited over the first metal feature. A manganese silicate etch stop layer is formed above the dielectric layer. An etch process is performed for removing for at least removing the first cap feature. A second metal feature is formed in a second metal layer. A dual-orientation self aligned via connecting a portion of the second metal feature to the first metal feature is formed.

Abstract: A method for fabricating a semiconductor structure includes etching a first opening into a substrate; etching a chip singulation trench into the substrate to define a lamella between the first opening and the chip singulation trench; fabricating a sense element for sensing a deflection of the lamella; and singulating the semiconductor structure at the chip singulation trench.

Abstract: A semiconductor device includes a substrate including an active area; a gate formed on the active area and surrounded by a spacer along a sidewall; a first source/drain contact and a second source/drain contact positioned on opposing sides of the gate and in contact with the active area; a first recess formed in the first source/drain contact and a second recess formed in the second source/drain contact; a gate contact including a conductive material on and in contact with the gate and the spacer; and an insulating liner disposed along a sidewall of the gate contact and in the first recess in the first source/drain contact and the second recess in the second source/drain contact.

Abstract: In some embodiments, silicon-filled openings are formed having no or a low occurrence of voids in the silicon fill, while maintaining a smooth exposed silicon surface. In some embodiments, an opening in a substrate may be filled with silicon, such as amorphous silicon. The deposited silicon may have interior voids. This deposited silicon is then exposed to a silicon mobility inhibitor, such as an oxygen-containing species and/or a semiconductor dopant. The deposited silicon fill is subsequently annealed. After the anneal, the voids may be reduced in size and, in some embodiments, this reduction in size may occur to such an extent that the voids are eliminated.

Abstract: The invention provides a semiconductor device. A buried layer is formed in a substrate. A first deep trench contact structure is formed in the substrate. The first deep trench contact structure comprises a conductor and a liner layer formed on a sidewall of the conductor. A bottom surface of the first deep trench contact structure is in contact with the buried layer.

Abstract: A capacitor structure and method of forming thereof on a substrate is described. The capacitor structure includes a substrate having a plurality of capacitor electrodes formed within an insulative retaining material, and a collar layer structure in contact with the plurality of capacitor electrodes, wherein the collar layer structure interconnects the plurality of capacitor electrodes and exposes the underlying insulative retaining material through openings having an unguided, random self-assembly pattern. Furthermore, the insulative retaining material may be removed from the capacitor structure. The method includes using a self-assembly process to form the interconnecting collar layer structure.

Abstract: According to an embodiment, a semiconductor device includes a second semiconductor layer provided on a first semiconductor layer and including first pillars and second pillars. A first control electrode is provided in a trench of the second semiconductor layer and a second control electrode is provided on the second semiconductor layer and connected to the first control electrode. A first semiconductor region is provided on a surface of the second semiconductor layer except for a portion under the second control electrode. A second semiconductor region is provided on a surface of the first semiconductor region, the second semiconductor region being apart from the portion under the second control electrode and a third semiconductor region is provided on the first semiconductor region. A first major electrode is connected electrically to the first semiconductor layer and a second major electrode is connected electrically to the second and the third semiconductor region.

Abstract: A doped fullerene-based conductive material can be used as an electrode, which can contact a dielectric such as a high k dielectric. By aligning the dielectric with the band gap of the doped fullerene-based electrode, e.g., the conduction band minimum of the dielectric falls into one of the band gaps of the doped fullerene-based material, thermionic leakage through the dielectric can be reduced, since the excited electrons or holes in the electrode would need higher thermal excitation energy to overcome the band gap before passing through the dielectric layer.

Abstract: Methods, apparatuses, and systems for providing a body connection to a vertical access device. The vertical access device may include a digit line extending along a substrate to a digit line contact pillar, a body connection line extending along the substrate to a body connection line contact pillar, a body region disposed on the body connection line, an electrode disposed on the body region, and a word line extending to form a gate to the body region. A method for operation includes applying a first voltage to the body connection line, and applying a second voltage to the word line to cause a conductive channel to form through the body region. A memory cell array may include a plurality of vertical access devices.

Abstract: A method of forming a memory cell includes forming one of multivalent metal oxide material or oxygen-containing dielectric material over a first conductive structure. An outer surface of the multivalent metal oxide material or the oxygen-containing dielectric material is treated with an organic base. The other of the multivalent metal oxide material or oxygen-containing dielectric material is formed over the treated outer surface. A second conductive structure is formed over the other of the multivalent metal oxide material or oxygen-containing dielectric material.

Abstract: A method of forming improved spacer isolation in deep trench including recessing a node dielectric, a first conductive layer, and a second conductive layer each deposited within a deep trench formed in a silicon-on-insulator (SOI) substrate, to a level below a buried oxide layer of the SOI substrate, and creating an opening having a bottom surface in the deep trench. Further including depositing a spacer along a sidewall of the deep trench and the bottom surface of the opening, and removing the spacer from the bottom surface of the opening. Performing at least one of an ion implantation and an ion bombardment in one direction at an angle into an upper portion of the spacer. Removing the upper portion of the spacer from the sidewall of the deep trench. Depositing a third conductive layer within the opening.

Abstract: The embodiment provides a buried bit line process and scheme. The buried bit line is disposed in a trench formed in a substrate. The buried bit line includes a diffusion region formed in a portion of the substrate adjacent the trench. A blocking layer is formed on a portion sidewall of the trench. A conductive plug is formed in the trench, covering sidewalls of the diffusion region and the blocking layer.

Abstract: A method for manufacturing a TiN/Ta2O5/TiN capacitor, including the steps of forming a Ta2O5 layer on a TiN support by a plasma-enhanced atomic layer deposition method, or PEALD; and submitting the obtained structure to an N2O plasma for a duration sufficient to oxidize the Ta2O5 layer without oxidizing the TiN support.

Abstract: A semiconductor device comprises a circuit cell and a basic end cell. The circuit cell includes a plurality of elements aligned in a first direction, and the basic end cell is arranged adjacent to the circuit cell in the first direction and has a compensation capacitor capable of being connected to a supply voltage of the circuit cell. In the semiconductor device, a diffusion layer forming the compensation capacitor extends along the first direction in a predetermined region of the circuit cell.

Abstract: A method of forming improved spacer isolation in deep trench including recessing a node dielectric, a first conductive layer, and a second conductive layer each deposited within a deep trench formed in a silicon-on-insulator (SOI) substrate, to a level below a buried oxide layer of the SOI substrate, and creating an opening having a bottom surface in the deep trench. Further including depositing a spacer along a sidewall of the deep trench and the bottom surface of the opening, and removing the spacer from the bottom surface of the opening. Performing at least one of an ion implantation and an ion bombardment in one direction at an angle into an upper portion of the spacer. Removing the upper portion of the spacer from the sidewall of the deep trench. Depositing a third conductive layer within the opening.

Abstract: A method of forming a memory cell includes forming one of multivalent metal oxide material or oxygen-containing dielectric material over a first conductive structure. An outer surface of the multivalent metal oxide material or the oxygen-containing dielectric material is treated with an organic base. The other of the multivalent metal oxide material or oxygen-containing dielectric material is formed over the treated outer surface. A second conductive structure is formed over the other of the multivalent metal oxide material or oxygen-containing dielectric material.

Abstract: A capacitor structure for a pumping circuit includes a substrate, a U-shaped bottom electrode in the substrate, a T-shaped top electrode in the substrate and a dielectric layer disposed between the U-shaped bottom and T-shaped top electrode. The contact area of the capacitor structure between the U-shaped bottom and T-shaped top electrode is extended by means of the cubic engagement of the U-shaped bottom electrode and the T-shaped top electrode.