Abstract: A transistor device comprises: at least one individual transistor cell arranged in a transistor cell field on a semiconductor body, each individual transistor cell comprising a gate electrode; a gate contact, electrically coupled to the gate electrodes of the transistor cells and configured to switch on the at least one transistor cell by providing a gate current in a first direction and configured to switch off the at least one transistor cell by providing a gate current in a second direction, the second direction being opposite to the first direction; at least one gate-resistor structure monolithically integrated in the transistor device, the gate-resistor structure providing a first resistance for the gate current when the gate current flows in the first direction, and providing a second resistance for the gate current, which is different from the first resistance, when the gate current flows in the second direction.
Type:
Grant
Filed:
July 25, 2013
Date of Patent:
May 26, 2015
Assignee:
Infineon Technologies AG
Inventors:
Stephan Voss, Peter Tuerkes, Holger Huesken
Abstract: Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.
Type:
Grant
Filed:
April 1, 2012
Date of Patent:
October 30, 2012
Assignee:
International Business Machines Corporation
Inventors:
Anthony Correale, Jr., Benjamin J. Bowers, Douglass T. Lamb, Nishith Rohatgi
Abstract: The present invention relates to methods of manufacturing an electrochemical energy storage device, such as a hybrid capacitor. The method comprises saturating a porous electrically conductive material in a solution comprising an organic solvent and a metal complex or a mixture of metal complexes; assembling a capacitor comprising the positive electrode made of porous electrically conductive material saturated with a metal complex, a negative electrode, and a separator in a casing; introducing the electrolyte solution into the casing; sealing the casing; and subsequent charge-discharge cycling of the capacitor. The charge-discharge cycling deposits a layer of an energy-accumulating redox polymer on the positive electrode. The electrolyte solution for filling the hybrid capacitor contains an organic solvent, a metal complex, and substances soluble to a concentration of no less than 0.01 mol/L and containing ions that are electrochemically inactive within the range of potentials between ?3.0 V to +1.5 V.
Type:
Grant
Filed:
March 23, 2007
Date of Patent:
February 15, 2011
Assignee:
GEN 3 Partners, Inc.
Inventors:
Irina Chepurnaya, Alexander Timonov, Sergey Logvinov, Sam Kogan
Abstract: A semiconductor structure of a high side driver and method for manufacturing the same is disclosed. The semiconductor of a high side driver includes an ion-doped junction and an isolation layer formed on the ion-doped junction. The ion-doped junction has a number of ion-doped deep wells, and the ion-doped deep wells are separated but partially linked with each other.
Abstract: A method of forming a pre-patterned high-k dielectric film onto a support layer. The method includes: providing a support layer; providing a template defining template openings therein exhibiting a pattern that is a mirror image of a pattern of the pre-patterned high-k dielectric film; disposing the template onto the support layer; providing a high-k precursor material inside the template openings; curing the high-k precursor material inside the template openings to yield a cured film; and removing the template from the support layer after curing to leave the cured film on the conductive film.