Permeable Base Transistor (pbt) (epo) Patents (Class 257/E21.402)
  • Patent number: 7413958
    Abstract: An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: August 19, 2008
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Liberty L Gunter, Kanin Chu, Charles R Eddy, Jr., Theodore D Moustakas, Enrico Bellotti
  • Patent number: 7405131
    Abstract: The example embodiments disclose devices and methods to prevent silicide strapping of the Source/Drain to Body in semiconductor devices with S/D stressor. We provide isolation regions in the substrate and a gate structure over the substrate. We form recesses in the substrate adjacent to the gate structure with disposable spacers and adjacent to the isolation regions. We provide stressor regions filling the recesses. The stress region can have a pit adjacent the isolation regions. We form stressor spacers at least partially in the pit on the sidewalls of the stressor regions. We form silicide regions over the stressor regions. The spacer on the stressor regions sidewalls inhibit the formation of silicide at the stressor region edge during the silicide process, thus preventing silicide strapping of the Source/Drain to Body.
    Type: Grant
    Filed: July 16, 2005
    Date of Patent: July 29, 2008
    Assignees: Chartered Semiconductor Manufacturing, Ltd., International Business Machines Corporation (IBM)
    Inventors: Yung Fu Chong, Brian Joseph Greene
  • Patent number: RE42955
    Abstract: An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: November 22, 2011
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Liberty L. Gunter, Kanin Chu, Charles R. Eddy, Jr., Theodore D. Moustakas, Enrico Bellotti